Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298136
M. D. V. Martino, J. Martino, P. Agopian
The goal of this work is to analyze the suitability of TFET and FinFET transistors in a differential pair. A quantitative comparison has been made based on the differential gain, the common-mode gain and the common-mode rejection ratio for each case. The first part of this work focused on perfectly matched circuits and explained the difference observed in the absolute values and in the susceptibility to the input voltage variation. The obtained curves have been explained based on the prevailing transport mechanisms for each case and its consequence on parameters such as transistor transconductance and output resistance. The second part highlighted the impact of mismatched transistors on the extracted results. The variation and the final result for each parameter have been analyzed. It was observed that TFETs presented better absolute values for the three highlighted parameters and better behavior for higher channel lengths. However, these devices have been more susceptible to the input voltage variation and to the decrease of channel length.
{"title":"Performance comparison between TFET and FinFET differential pair","authors":"M. D. V. Martino, J. Martino, P. Agopian","doi":"10.1109/SBMICRO.2015.7298136","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298136","url":null,"abstract":"The goal of this work is to analyze the suitability of TFET and FinFET transistors in a differential pair. A quantitative comparison has been made based on the differential gain, the common-mode gain and the common-mode rejection ratio for each case. The first part of this work focused on perfectly matched circuits and explained the difference observed in the absolute values and in the susceptibility to the input voltage variation. The obtained curves have been explained based on the prevailing transport mechanisms for each case and its consequence on parameters such as transistor transconductance and output resistance. The second part highlighted the impact of mismatched transistors on the extracted results. The variation and the final result for each parameter have been analyzed. It was observed that TFETs presented better absolute values for the three highlighted parameters and better behavior for higher channel lengths. However, these devices have been more susceptible to the input voltage variation and to the decrease of channel length.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124925096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298106
Caroline I. Lisevski, A. L. F. Cauduro, P. Franzen, H. Boudinov, D. L. Baptista
Zinc oxide nanowires have been attracting much interest due to their potential use in electronics and optoelectonics devices. In this work, we report on the photoluminescence and electrical behavior of ZnO nanowires grown by vapor-liquid-solid method and irradiated with 1.2 MeV He+ ions at several doses. The results strongly indicates the existence of an enhanced dynamic annealing effect during the low fluence irradiations allowing it to heal low migration barrier point-defects such as oxygen interstitials (OI), zinc interstitials (ZnI), zinc antisites (ZnO) and oxygen antisites (OZn). On the other hand, highly stable defects such as oxygen vacancies (VO), which present higher migration barrier energy, seems to be more pronounced giving rise to short-infrared emission at 1.7 eV.
{"title":"Electrical and optical behavior of ZnO nanowires irradiated by ion beam","authors":"Caroline I. Lisevski, A. L. F. Cauduro, P. Franzen, H. Boudinov, D. L. Baptista","doi":"10.1109/SBMICRO.2015.7298106","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298106","url":null,"abstract":"Zinc oxide nanowires have been attracting much interest due to their potential use in electronics and optoelectonics devices. In this work, we report on the photoluminescence and electrical behavior of ZnO nanowires grown by vapor-liquid-solid method and irradiated with 1.2 MeV He+ ions at several doses. The results strongly indicates the existence of an enhanced dynamic annealing effect during the low fluence irradiations allowing it to heal low migration barrier point-defects such as oxygen interstitials (OI), zinc interstitials (ZnI), zinc antisites (ZnO) and oxygen antisites (OZn). On the other hand, highly stable defects such as oxygen vacancies (VO), which present higher migration barrier energy, seems to be more pronounced giving rise to short-infrared emission at 1.7 eV.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128773511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298149
M. V. P. D. Santos, Lucas P. B. Lima, R. Mayer, Jefferson Bettini, F. Béron, K. R. Pirota, José Alexandre Diniz
Nanowires (NW) have received much attention due to their shape anisotropy, high aspect ratio, relatively large surface area and particular electron transport properties. In addition, NW can be used as sensor devices for several applications, since they present high sensitivity to the environment. One of the major challenges when dealing with transport measurements in NW is to trap them between electrodes, which allows electrical characterization and therefore fabrication of nanowire-based devices. Electrically neutral NW can be deposited by dielectrophoresis (DEP) method, which requires the application of an alternating electric field between electrodes. In this work, Ni nanowires (NiNW) fabricated by electrodeposition technique and properly dispersed in a DMF solution were deposited on top of Pt electrodes using the DEP method. The deposited NiNW exhibit initially a Schottky-like current versus voltage behavior due to the high contact resistance between NiNW and electrode. Its reduction down to two orders of magnitude, reaching value less than the NiNW resistance, was achieved by depositing an ion beam-assisted 10 nm-thick Pt layer over the NW extremities. Therefore, this method presents a suitable process of NW deposition and electrical characterization. This can be used for investigation of electrical transport properties of individual NW and fabrication of NW-based devices, such as sensors and field effect transistors. Especially for ferromagnetic NW, one can use the present method for fabrication of magnetic field-effect transistors (MagFET).
{"title":"Electrical and structural characterization of electrodeposited Ni nanowires","authors":"M. V. P. D. Santos, Lucas P. B. Lima, R. Mayer, Jefferson Bettini, F. Béron, K. R. Pirota, José Alexandre Diniz","doi":"10.1109/SBMICRO.2015.7298149","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298149","url":null,"abstract":"Nanowires (NW) have received much attention due to their shape anisotropy, high aspect ratio, relatively large surface area and particular electron transport properties. In addition, NW can be used as sensor devices for several applications, since they present high sensitivity to the environment. One of the major challenges when dealing with transport measurements in NW is to trap them between electrodes, which allows electrical characterization and therefore fabrication of nanowire-based devices. Electrically neutral NW can be deposited by dielectrophoresis (DEP) method, which requires the application of an alternating electric field between electrodes. In this work, Ni nanowires (NiNW) fabricated by electrodeposition technique and properly dispersed in a DMF solution were deposited on top of Pt electrodes using the DEP method. The deposited NiNW exhibit initially a Schottky-like current versus voltage behavior due to the high contact resistance between NiNW and electrode. Its reduction down to two orders of magnitude, reaching value less than the NiNW resistance, was achieved by depositing an ion beam-assisted 10 nm-thick Pt layer over the NW extremities. Therefore, this method presents a suitable process of NW deposition and electrical characterization. This can be used for investigation of electrical transport properties of individual NW and fabrication of NW-based devices, such as sensors and field effect transistors. Especially for ferromagnetic NW, one can use the present method for fabrication of magnetic field-effect transistors (MagFET).","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116763695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298128
A. M. Rosa, J. A. Diniz, I. Doi, M. A. Canesqui, M. P. D. dos Santos, A. Vaz
In this work, hydrogenated amorphous silicon (a-Si:H) films were deposited by electron cyclotron resonance (ECR) - chemical vapor deposition (CVD) and used as spacer to implement the spacer lithography (SL) technique. This technique was employed to define silicon nanowires (SiNWs), which are three-dimensional (3D) structures on Si surface. With these SiNWs, 3D MOS (metal-oxide-semiconductor) capacitors were fabricated. Surface analyses were carried out by atomic force microscopy (AFM) and scanning electron microscopy (SEM) in order to verify the quality and integrity of SiNWs. From these measurements, it can be observed continuous and lengthy SINWs with heights of 17.7 nm and widths of 15.6 nm. Furthermore, the fabricated 3D MOS capacitors, with Al (500 nm)/ SiO2 (10 nm)/ SiNWs structures, were used to obtain capacitance-voltage (CxV) measurements. From CxV curves, it can be observed that the capacitors exhibited a perfectly defined, the accumulation, depletion and inversion regions of carriers in the Si substrate with SiNWs. Furthermore, also the effective charge density of about 1011 cm-2 and flat-band voltage of -1.1 V were extracted. From these results, it can be concluded that the proposed method of spacer lithography can be used to get 3D MOS devices, such as FinFETs and JunctionLess, which are based on SiNWs.
{"title":"Spacer lithography for 3D MOS devices using amorphous silicon deposited by ECR-CVD","authors":"A. M. Rosa, J. A. Diniz, I. Doi, M. A. Canesqui, M. P. D. dos Santos, A. Vaz","doi":"10.1109/SBMICRO.2015.7298128","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298128","url":null,"abstract":"In this work, hydrogenated amorphous silicon (a-Si:H) films were deposited by electron cyclotron resonance (ECR) - chemical vapor deposition (CVD) and used as spacer to implement the spacer lithography (SL) technique. This technique was employed to define silicon nanowires (SiNWs), which are three-dimensional (3D) structures on Si surface. With these SiNWs, 3D MOS (metal-oxide-semiconductor) capacitors were fabricated. Surface analyses were carried out by atomic force microscopy (AFM) and scanning electron microscopy (SEM) in order to verify the quality and integrity of SiNWs. From these measurements, it can be observed continuous and lengthy SINWs with heights of 17.7 nm and widths of 15.6 nm. Furthermore, the fabricated 3D MOS capacitors, with Al (500 nm)/ SiO2 (10 nm)/ SiNWs structures, were used to obtain capacitance-voltage (CxV) measurements. From CxV curves, it can be observed that the capacitors exhibited a perfectly defined, the accumulation, depletion and inversion regions of carriers in the Si substrate with SiNWs. Furthermore, also the effective charge density of about 1011 cm-2 and flat-band voltage of -1.1 V were extracted. From these results, it can be concluded that the proposed method of spacer lithography can be used to get 3D MOS devices, such as FinFETs and JunctionLess, which are based on SiNWs.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129400955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298111
G. Leal, Mariana Amorim Fraga, G. W. A. Cardoso, A. S. da Silva Sobrinho, M. Massi
There is a great interest in understanding the properties of sputtered DLC films in order to enable their wide application in electronic devices and sensors. In present study, metal-containing diamond-like carbon (Me-DLC) thin films were deposited on Si (100) substrates by DC magnetron co-sputtering using a carbon target under a fixed power (150 W) and a metal target (tin or tungsten) under varying power (10-30 W), while the other parameters were kept constant. The growth rate, chemical composition, structure and electrical resistivity of the Sn-DLC and W-DLC thin films were studied by mechanical profilometer, RBS, SEM, Raman spectroscopy and four points probe, respectively. The results showed that the growth rate of Sn-DLC thin film is higher than the W-DLC. Furthermore, the Sn incorporation in DLC films is higher than W-DLC for the same power applied to the metal target. Relationship between the electrical resistivity of both film types and the power applied was also observed.
{"title":"Effect of metal target power on the properties of co-sputtered Sn-DLC and W-DLC thin films","authors":"G. Leal, Mariana Amorim Fraga, G. W. A. Cardoso, A. S. da Silva Sobrinho, M. Massi","doi":"10.1109/SBMICRO.2015.7298111","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298111","url":null,"abstract":"There is a great interest in understanding the properties of sputtered DLC films in order to enable their wide application in electronic devices and sensors. In present study, metal-containing diamond-like carbon (Me-DLC) thin films were deposited on Si (100) substrates by DC magnetron co-sputtering using a carbon target under a fixed power (150 W) and a metal target (tin or tungsten) under varying power (10-30 W), while the other parameters were kept constant. The growth rate, chemical composition, structure and electrical resistivity of the Sn-DLC and W-DLC thin films were studied by mechanical profilometer, RBS, SEM, Raman spectroscopy and four points probe, respectively. The results showed that the growth rate of Sn-DLC thin film is higher than the W-DLC. Furthermore, the Sn incorporation in DLC films is higher than W-DLC for the same power applied to the metal target. Relationship between the electrical resistivity of both film types and the power applied was also observed.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133967260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298147
F. Avila Herrera, A. Cerdeira, B. Cardoso Paz, M. Estrada, M. Pavanello
A new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
{"title":"Analytical compact model for triple gate junctionless MOSFETs","authors":"F. Avila Herrera, A. Cerdeira, B. Cardoso Paz, M. Estrada, M. Pavanello","doi":"10.1109/SBMICRO.2015.7298147","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298147","url":null,"abstract":"A new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122798566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298124
D. M. Pedroso, A. Passaro
In this paper, the dark current in Quantum Well Infrared Photodetectors (QWIP) operating at the thermionic regime is computed by a semiclassical model based on the Ehrenfest Theorem. The model is independent of adjusting or empirical parameters. The corresponding wave functions are calculated considering a nonparabolic approximation and temperature-dependent energy gap. The theoretical results are compared with experimental data obtained from AlGaAs/GaAs QWIP with symmetric rectangular wells and were found to be in a good agreement.
{"title":"Modelling of dark current in AlGaAs/GaAs QWIPs","authors":"D. M. Pedroso, A. Passaro","doi":"10.1109/SBMICRO.2015.7298124","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298124","url":null,"abstract":"In this paper, the dark current in Quantum Well Infrared Photodetectors (QWIP) operating at the thermionic regime is computed by a semiclassical model based on the Ehrenfest Theorem. The model is independent of adjusting or empirical parameters. The corresponding wave functions are calculated considering a nonparabolic approximation and temperature-dependent energy gap. The theoretical results are compared with experimental data obtained from AlGaAs/GaAs QWIP with symmetric rectangular wells and were found to be in a good agreement.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125499058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298138
L. C. Costa, Artur S. B. de Mello, L. P. Salles, D. W. de Lima Monteiro
This paper presents experimental and simulated results of the Active Pixel Sensor (APS) circuit operating in 6 different cell designs. The optical sensor used was a silicon photodiode integrated with its electronics in a standard 350nm CMOS technology. Comparison between the types of circuits was made to determine the operational characteristics for different irradiance values. The results are important to guide choices for different applications.
{"title":"Comparative analysis of 350nm CMOS Active Pixel Sensor electronics","authors":"L. C. Costa, Artur S. B. de Mello, L. P. Salles, D. W. de Lima Monteiro","doi":"10.1109/SBMICRO.2015.7298138","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298138","url":null,"abstract":"This paper presents experimental and simulated results of the Active Pixel Sensor (APS) circuit operating in 6 different cell designs. The optical sensor used was a silicon photodiode integrated with its electronics in a standard 350nm CMOS technology. Comparison between the types of circuits was made to determine the operational characteristics for different irradiance values. The results are important to guide choices for different applications.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129744624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SBMICRO.2015.7298145
T. A. Ribeiro, E. Simoen, C. Claeys, J. Martino, M. Pavanello
This paper studies the transport parameters of n-type FinFETs extracted using the Y-Function methodology, by comparing their dependence on the fin width and the crystallographic orientation for standard and rotated substrates as well as the influence of biaxial strain. The Y-Function has been applied with a recursive algorithm to improve its accuracy. The results obtained show that the low-field mobility increases, for devices with narrow fin, just with the rotation of the substrate. With biaxial strain the mobility increases about 50% for the standard devices and about 30% for the rotated devices compared to non-strained devices. The mobility degradation is also extracted and evaluated showing strong coulomb scattering and surface roughness scattering, where the later is higher on standard and strained devices than on only rotated devices.
{"title":"Detailed analysis of transport properties of FinFETs through Y-Function method: Effects of substrate orientation and strain","authors":"T. A. Ribeiro, E. Simoen, C. Claeys, J. Martino, M. Pavanello","doi":"10.1109/SBMICRO.2015.7298145","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298145","url":null,"abstract":"This paper studies the transport parameters of n-type FinFETs extracted using the Y-Function methodology, by comparing their dependence on the fin width and the crystallographic orientation for standard and rotated substrates as well as the influence of biaxial strain. The Y-Function has been applied with a recursive algorithm to improve its accuracy. The results obtained show that the low-field mobility increases, for devices with narrow fin, just with the rotation of the substrate. With biaxial strain the mobility increases about 50% for the standard devices and about 30% for the rotated devices compared to non-strained devices. The mobility degradation is also extracted and evaluated showing strong coulomb scattering and surface roughness scattering, where the later is higher on standard and strained devices than on only rotated devices.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"489 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SBMICRO.2015.7298104
C. Claeys, Eddy Simoen, P. Agopian, J. Martino, M. Aoulaiche, B. Crețu, W. Fang, R. Rooyackers, A. Vandooren, Anabela Veloso, Malgorzata Jurczak, N. Collaert, Aaron Thean
Low frequency noise diagnostics is a powerful tool to study the quality of gate stacks and the different interfaces and also gives detailed information on the device performance and reliability. The influence of new materials, different processing treatments and alternative device concepts on the low frequency noise performance will be reviewed for a variety of advanced device technologies including aspects such as strain engineering, heteroexpitaxial growth, gate-first and gate-last or replacement metal gate integration schemes etc. Results for both planar and 3D structures (FinFETs, TFETs) will be reported and benchmarked with the LF noise specifications of the International Technology Roadmap for Semiconductors (ITRS).
{"title":"The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices","authors":"C. Claeys, Eddy Simoen, P. Agopian, J. Martino, M. Aoulaiche, B. Crețu, W. Fang, R. Rooyackers, A. Vandooren, Anabela Veloso, Malgorzata Jurczak, N. Collaert, Aaron Thean","doi":"10.1109/SBMICRO.2015.7298104","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298104","url":null,"abstract":"Low frequency noise diagnostics is a powerful tool to study the quality of gate stacks and the different interfaces and also gives detailed information on the device performance and reliability. The influence of new materials, different processing treatments and alternative device concepts on the low frequency noise performance will be reviewed for a variety of advanced device technologies including aspects such as strain engineering, heteroexpitaxial growth, gate-first and gate-last or replacement metal gate integration schemes etc. Results for both planar and 3D structures (FinFETs, TFETs) will be reported and benchmarked with the LF noise specifications of the International Technology Roadmap for Semiconductors (ITRS).","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132183993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：