Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770490
K. Maji, K. Mukherjee, Ashif Raja
TOAD based interferometric switch is analyzed in terms of time dependent gain. The dependence of gain on control pulse width is also shown. Output power of the transmitted and reflected port of the switch is calculated for a soliton pulse train. This is shows possibility of application in the implementation of optical logic gates and processors.
{"title":"Analysis of Tera Hertz Optical Asymmetric Demultiplexer(TOAD) based Optical Switch Using Soliton Pulse","authors":"K. Maji, K. Mukherjee, Ashif Raja","doi":"10.1109/EDKCON.2018.8770490","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770490","url":null,"abstract":"TOAD based interferometric switch is analyzed in terms of time dependent gain. The dependence of gain on control pulse width is also shown. Output power of the transmitted and reflected port of the switch is calculated for a soliton pulse train. This is shows possibility of application in the implementation of optical logic gates and processors.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132223598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/edkcon.2018.8770476
{"title":"Welcome message from General Chair, EDKCON","authors":"","doi":"10.1109/edkcon.2018.8770476","DOIUrl":"https://doi.org/10.1109/edkcon.2018.8770476","url":null,"abstract":"","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"526 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132381864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital information, being discrete in nature, possesses the capability to transfer more information at a faster rate with a significantly higher processing ease, all of which are in sharp contrast to analogue information. This has led to digital information being at the forefront of different types of media like image, video and audio. The only drawback of this has been the rise of copyright infringement issues, whereby the original owner becomes devoid of his claim over his uniquely designed creation because of duplicity and tampering by malicious users. Digital watermarking is a well sought out solution to this. The original user deliberately implants a distinctively identifiable impression onto the digital media for preventing copyright violation. The authors over here have focused on the specific domain of Medical Image Watermarking. Medical images like X-rays, USG, and MRI have revolutionized the medication fraternity by providing enhanced diagnosis and treatment of patients. But at the same time, copyright infringement of the medical images is a growing concern. To curb this problem, a notion of creating a binary masked image in comparison to the original medical image has been suggested. The mask helps in specifically identifying the region of interest (ROI)wherein the encrypted watermark has to be implanted for better imperceptibility and security. The encrypted watermark is embedded in the spatial domain, that is, the Least Significant Bit (LSB)of image pixels are modified in accordance to the watermarking bits. For a widespread acceptance of the proposed technique, the embedding and extracting methodologies have been implemented using Field Programmable Gate Array (FPGA). The imperceptibility, security and bit hiding capacity results are appreciably substantial. Further, a comparison of the suggested technique against some already relevant cutting edge techniques guarantees the superiority of the proposed technique.
{"title":"FPGA Realization of Medical Image Watermarking","authors":"Sandeep Bal, Sanjay Das, Soumadeb Dutta, Souma Das, Debamita Biswas, A. Basu","doi":"10.1109/EDKCON.2018.8770458","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770458","url":null,"abstract":"Digital information, being discrete in nature, possesses the capability to transfer more information at a faster rate with a significantly higher processing ease, all of which are in sharp contrast to analogue information. This has led to digital information being at the forefront of different types of media like image, video and audio. The only drawback of this has been the rise of copyright infringement issues, whereby the original owner becomes devoid of his claim over his uniquely designed creation because of duplicity and tampering by malicious users. Digital watermarking is a well sought out solution to this. The original user deliberately implants a distinctively identifiable impression onto the digital media for preventing copyright violation. The authors over here have focused on the specific domain of Medical Image Watermarking. Medical images like X-rays, USG, and MRI have revolutionized the medication fraternity by providing enhanced diagnosis and treatment of patients. But at the same time, copyright infringement of the medical images is a growing concern. To curb this problem, a notion of creating a binary masked image in comparison to the original medical image has been suggested. The mask helps in specifically identifying the region of interest (ROI)wherein the encrypted watermark has to be implanted for better imperceptibility and security. The encrypted watermark is embedded in the spatial domain, that is, the Least Significant Bit (LSB)of image pixels are modified in accordance to the watermarking bits. For a widespread acceptance of the proposed technique, the embedding and extracting methodologies have been implemented using Field Programmable Gate Array (FPGA). The imperceptibility, security and bit hiding capacity results are appreciably substantial. Further, a comparison of the suggested technique against some already relevant cutting edge techniques guarantees the superiority of the proposed technique.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116497038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770493
Narendra Deo Singh, R. Singh, R. Raj, Shivam Jyoti, A. Saha
Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL)based Ternary (base-3)logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2)number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage requirement and so on. Careful design with proper coarse and fine tuning of wave-pipelined circuit can improve the overall performance and reliability of digital SOC. DPL is a favourable candidate for wave-pipelining and is employed in this work. Ternary digit (“trit”)value “0”, “1” and “2” are coded with 0 V, 0.9 V and 1.8 V respectively. In order to validate proposed strategy the 2-input TXOR, TAND and TOR circuits are designed and the simulation results are verified. Speed-power performance of designed circuit is recorded. All the simulations are carried out on TSMC $0.18mumathrm{m}$ CMOS technology with 1.8 V supply rail and at 25°C temperature using Tanner EDA.V13.
{"title":"Novel Approach to Design DPL-based Ternary Logic Circuits","authors":"Narendra Deo Singh, R. Singh, R. Raj, Shivam Jyoti, A. Saha","doi":"10.1109/EDKCON.2018.8770493","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770493","url":null,"abstract":"Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL)based Ternary (base-3)logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2)number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage requirement and so on. Careful design with proper coarse and fine tuning of wave-pipelined circuit can improve the overall performance and reliability of digital SOC. DPL is a favourable candidate for wave-pipelining and is employed in this work. Ternary digit (“trit”)value “0”, “1” and “2” are coded with 0 V, 0.9 V and 1.8 V respectively. In order to validate proposed strategy the 2-input TXOR, TAND and TOR circuits are designed and the simulation results are verified. Speed-power performance of designed circuit is recorded. All the simulations are carried out on TSMC $0.18mumathrm{m}$ CMOS technology with 1.8 V supply rail and at 25°C temperature using Tanner EDA.V13.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116681954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770480
S. Tripathi, S. K. Sinha, G. Patel, S. Awasthi
This paper presents a low leakage pocket Six-Ge1-x, junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Six-Ge1-x, decreases tunneling distance and improves the $mathrm{I}_{mathrm{o}mathrm{n}}/mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.
{"title":"High Performance Low Leakage Pocket SixGe1-x Junction-Less Single-Gate Tunnel FET for 10 nm Technology","authors":"S. Tripathi, S. K. Sinha, G. Patel, S. Awasthi","doi":"10.1109/EDKCON.2018.8770480","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770480","url":null,"abstract":"This paper presents a low leakage pocket Six-Ge1-x, junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Six-Ge1-x, decreases tunneling distance and improves the $mathrm{I}_{mathrm{o}mathrm{n}}/mathrm{I}_{mathrm{o}mathrm{f}mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128268048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770388
I. Sil, Kalyan Biswas
This paper presents a Micro Electro Mechanical system (MEMS) based Vibration Energy Harvester (VEH) to harvest energy from external vibration sources and convert it to usable electrical output. Detailed simulation and analysis of Vibration Energy Harvester (VEH) is done to achieve better performance. Finite element analysis software ANSYS has been used for parametric analysis and measure beam displacement, resonant frequency, and output power of the VEH. Different important parameters like beam length, thickness, width, position of mass placement, different piezoelectric material etc. were varied to improve the performance of the device. The 33 mode of operation is used to get the output from the vibration energy harvester. Simulation result shown that to obtain better output from VEH (a) the beam length should be large, (b) beam thickness and width should be small, (iii) mass length, thickness and width should be large. For a Unimorph device of total size of 1500×900×500 μm3, an output voltage of 200 mV is obtained when 1N force is applied on the structure.
{"title":"Investigation of Design Parameters in MEMS Based Piezoelectric Vibration Energy Harvester","authors":"I. Sil, Kalyan Biswas","doi":"10.1109/EDKCON.2018.8770388","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770388","url":null,"abstract":"This paper presents a Micro Electro Mechanical system (MEMS) based Vibration Energy Harvester (VEH) to harvest energy from external vibration sources and convert it to usable electrical output. Detailed simulation and analysis of Vibration Energy Harvester (VEH) is done to achieve better performance. Finite element analysis software ANSYS has been used for parametric analysis and measure beam displacement, resonant frequency, and output power of the VEH. Different important parameters like beam length, thickness, width, position of mass placement, different piezoelectric material etc. were varied to improve the performance of the device. The 33 mode of operation is used to get the output from the vibration energy harvester. Simulation result shown that to obtain better output from VEH (a) the beam length should be large, (b) beam thickness and width should be small, (iii) mass length, thickness and width should be large. For a Unimorph device of total size of 1500×900×500 μm3, an output voltage of 200 mV is obtained when 1N force is applied on the structure.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770464
Rashmit Patel, Yash Agrawal, R. Parekh
A microprocessor or a computing system is a general purpose device which works on the user defined instructions. The simulation of a computing system requires complex stimuli to verify the design. It needs initialization and configuration of memory for required instructions and their execution. A Single Electron Transistors based computing system can be designed using Cadence Virtuoso environment. The traditional method of design verification is to simulate the design by applying inputs through multiple signal sources. Using this approach, the simulation is tedious and complicated. Cadence Spectre tool has a facility to simulate the design using a vector file which combines multiple signal sources in a text file. But, writing a vector file manually is complex and erroneous. To overcome this problem, we have designed a program that will generate a vector file based on the user selected instructions and parameters. It makes the simulation straightforward and accurate. This paper describes the design of the program for vector file generation.
{"title":"A Vector File Generation Program for Simulating Single Electron Transistor based Computing System","authors":"Rashmit Patel, Yash Agrawal, R. Parekh","doi":"10.1109/EDKCON.2018.8770464","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770464","url":null,"abstract":"A microprocessor or a computing system is a general purpose device which works on the user defined instructions. The simulation of a computing system requires complex stimuli to verify the design. It needs initialization and configuration of memory for required instructions and their execution. A Single Electron Transistors based computing system can be designed using Cadence Virtuoso environment. The traditional method of design verification is to simulate the design by applying inputs through multiple signal sources. Using this approach, the simulation is tedious and complicated. Cadence Spectre tool has a facility to simulate the design using a vector file which combines multiple signal sources in a text file. But, writing a vector file manually is complex and erroneous. To overcome this problem, we have designed a program that will generate a vector file based on the user selected instructions and parameters. It makes the simulation straightforward and accurate. This paper describes the design of the program for vector file generation.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133826836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770447
S. Biswal, Biswajit Baral, S. Swain, Sudhansu Kumar Pati
A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(gm) transconductancegeneration factor(TGF), intrinsic gain (gm/gds) output resistance (R0) unity gain cut-off frequency (fT) and Maximum Frequency of Oscillations (fmax) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.
{"title":"Performance Analysis of Down Scaling Effect of Si based SRG Tunnel FET","authors":"S. Biswal, Biswajit Baral, S. Swain, Sudhansu Kumar Pati","doi":"10.1109/EDKCON.2018.8770447","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770447","url":null,"abstract":"A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(gm) transconductancegeneration factor(TGF), intrinsic gain (gm/gds) output resistance (R0) unity gain cut-off frequency (fT) and Maximum Frequency of Oscillations (fmax) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134270952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770437
Raktim Chakraborty, J. K. Mandal, S. Biswas
A 6nm MOSFET and CMOS device presented in this paper. With 0.005v drain voltage a minimum channel length of 24nm and a optimized threshold voltage of 0.2360v is achieved in the present work. A 6nm n-type and p-type MOSFET is modelled and simulated to design CMOS device. The optimized device performance of the CMOS is presented. Indium Gallium Arsenide and Hafnium Oxide is used as semiconductor and oxide material. The electrical performance is evaluated in terms of supplied gate voltage $mathrm{V}_{mathrm{G}mathrm{S}}$, Drain to Source Voltage $mathrm{V}_{text{DS}}$, Threshold Voltage $mathrm{V}_{mathrm{T}mathrm{H}}$ and Drain Current ID. The 6nm gate length MOSFET device has achieved an optimized threshold voltage $(mathrm{V}_{mathrm{T}mathrm{H}})$ 0.2360v drive current $(mathrm{I}_{mathrm{O}mathrm{N}})$ of 19.152 ⨯ 10−5A/um, and leakage current $(mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}})$ of 37.33 ⨯ 10−10 A/um.
{"title":"Modelling of 6nm MOS and CMOS","authors":"Raktim Chakraborty, J. K. Mandal, S. Biswas","doi":"10.1109/EDKCON.2018.8770437","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770437","url":null,"abstract":"A 6nm MOSFET and CMOS device presented in this paper. With 0.005v drain voltage a minimum channel length of 24nm and a optimized threshold voltage of 0.2360v is achieved in the present work. A 6nm n-type and p-type MOSFET is modelled and simulated to design CMOS device. The optimized device performance of the CMOS is presented. Indium Gallium Arsenide and Hafnium Oxide is used as semiconductor and oxide material. The electrical performance is evaluated in terms of supplied gate voltage $mathrm{V}_{mathrm{G}mathrm{S}}$, Drain to Source Voltage $mathrm{V}_{text{DS}}$, Threshold Voltage $mathrm{V}_{mathrm{T}mathrm{H}}$ and Drain Current ID. The 6nm gate length MOSFET device has achieved an optimized threshold voltage $(mathrm{V}_{mathrm{T}mathrm{H}})$ 0.2360v drive current $(mathrm{I}_{mathrm{O}mathrm{N}})$ of 19.152 ⨯ 10−5A/um, and leakage current $(mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}})$ of 37.33 ⨯ 10−10 A/um.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"18 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133455518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770406
Anubha Goel, Sonam Rewari, S. Verma, R. Gupta
Dielectric Restrained Triple Metal Gate All Around (TG GAA)MOSFET is investigated as a bio-sensor to nail its applicability in biomedical field for DNA molecule and neutral species detection in particular proteins (Biotin & Streptavidin). In this paper nanoparticle with different bio molecular concentrations and different permittivity have been inserted in the cavity inside the oxide layer. The mutation in the drain current (Ids)and the threshold voltage (vth)is then studied in order to assimilate the sensitivity of the MOSFET. The performance of Triple Metal Gate All Around (TG GAA)MOSFET has been compared with that of Dual Metal Gate All Around (DG GAA)MOSFET and Single Metal Gate All Around (SG GAA)MOSFET. Nanogap Embedded TGGAA MOSFET is advantageous from the integration point of view due to the compatibility with CMOS process of the forthcoming silicon based Lab on Chip Systems as well as increased sensitivity.
{"title":"Dielectric Modulated Triple Metal Gate All Around MOSFET (TMGAA)for DNA Bio-Molecule Detection","authors":"Anubha Goel, Sonam Rewari, S. Verma, R. Gupta","doi":"10.1109/EDKCON.2018.8770406","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770406","url":null,"abstract":"Dielectric Restrained Triple Metal Gate All Around (TG GAA)MOSFET is investigated as a bio-sensor to nail its applicability in biomedical field for DNA molecule and neutral species detection in particular proteins (Biotin & Streptavidin). In this paper nanoparticle with different bio molecular concentrations and different permittivity have been inserted in the cavity inside the oxide layer. The mutation in the drain current (Ids)and the threshold voltage (vth)is then studied in order to assimilate the sensitivity of the MOSFET. The performance of Triple Metal Gate All Around (TG GAA)MOSFET has been compared with that of Dual Metal Gate All Around (DG GAA)MOSFET and Single Metal Gate All Around (SG GAA)MOSFET. Nanogap Embedded TGGAA MOSFET is advantageous from the integration point of view due to the compatibility with CMOS process of the forthcoming silicon based Lab on Chip Systems as well as increased sensitivity.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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