Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770400
K. G. Sravani, K. Guha, K. S. Rao
This paper presents the study of capacitance modeling of step structured non-uniform meander based capacitive RF MEMS shunt switch with etched holes on the beam. A new strategy of introducing perforation in the step structure beam minimizes the fringing field capacitance and enhances the switching speed. The switch is simulated using FEM tool for validation and the simulated results of upstate and down state capacitance is compared to the analytical results. Our outcomes reveal that proposed capacitance model defeats the existing models for satellite applications. The errors are estimated and analyzed by varying beam thickness and ligament efficiency. The proposed step structured switch having beam thickness of 1.5um with the minimal dielectric thickness results in high performance of the device with ligament efficiency of $mu=0.38$ comparing with the benchmark models for capacitance modelling. The proposed analytical model shows extraordinary accomplishment for higher bridge thickness of 1.5μm with an estimation of 0.2-2% error. Two bench mark models of capacitance are calculated and validated against the proposed model.
{"title":"An Investigation on Capacitance Modeling of Step Strcture RF MEMS Perforated Shunt Switch","authors":"K. G. Sravani, K. Guha, K. S. Rao","doi":"10.1109/EDKCON.2018.8770400","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770400","url":null,"abstract":"This paper presents the study of capacitance modeling of step structured non-uniform meander based capacitive RF MEMS shunt switch with etched holes on the beam. A new strategy of introducing perforation in the step structure beam minimizes the fringing field capacitance and enhances the switching speed. The switch is simulated using FEM tool for validation and the simulated results of upstate and down state capacitance is compared to the analytical results. Our outcomes reveal that proposed capacitance model defeats the existing models for satellite applications. The errors are estimated and analyzed by varying beam thickness and ligament efficiency. The proposed step structured switch having beam thickness of 1.5um with the minimal dielectric thickness results in high performance of the device with ligament efficiency of $mu=0.38$ comparing with the benchmark models for capacitance modelling. The proposed analytical model shows extraordinary accomplishment for higher bridge thickness of 1.5μm with an estimation of 0.2-2% error. Two bench mark models of capacitance are calculated and validated against the proposed model.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127572353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770409
Lalthanpuii Khiangte, Rudra Sankar Dhar
A heterostructure design with two strained silicon (s-Si) layers on both side of the middle layer strained silicon germanium (s-SiGe) layer, forming a tri-layered channel heterostructure-on-insulator (HOI) metal oxide semiconductor field effect transistor (MOSFET) have been developed. Quantum carrier confinement ensued within both the ultrathin s-Si layers, which instigates mobility enhancement, and hence counter balances the threshold voltage (Vth) roll-off due to the strained layers in the channel region. A comparison of the conventional single s-Si on relaxed SiGe channel HOI MOSFET with double s-Si channel HOI MOSFET have been perceived leading to eloquent drain current enhancement of $sim49%$ for channel length, Lg=100nm due to the captivity of carriers with trivial reduction in the threshold voltage caused on the additional bottom s-Si layer. An in depth analysis of the device in the nanoscale regime for Device-B (Lg=50nm) and Device-C (Lg=40nm) have exemplified superior device characteristic without scaling down the overall device geometry, leading to prominence of velocity overshoot condition under low-scattering effect, augmenting mobility and drift velocity, while approaching to the quasi ballistic carrier transport mechanism in the channel, therefore remarkably improving drive current of the nano-MOSFET.
本文提出了在中间层应变硅锗(s-SiGe)层两侧各有两层应变硅(s-Si)层的异质结构设计，形成三层沟道绝缘体上异质结构(HOI)金属氧化物半导体场效应晶体管(MOSFET)。在超薄s-Si层中都存在量子载流子约束，这增强了迁移率，从而抵消了由于通道区域的应变层而导致的阈值电压(Vth)滚降。将传统的单s-Si松弛SiGe沟道HOI MOSFET与双s-Si沟道HOI MOSFET进行比较，可以发现沟道长度为Lg=100nm时，由于载流子的束缚，导致阈值电压轻微降低，导致漏极电流增强$sim49%$。对device - b (Lg=50nm)和device - c (Lg=40nm)在纳米尺度下的器件深入分析表明，在不缩小器件整体几何尺寸的情况下，器件具有优越的特性，导致低散射效应下的速度超调条件突出，增加了迁移率和漂移速度，同时接近通道中的准弹道载流子输运机制，从而显著提高了纳米mosfet的驱动电流。
{"title":"Two Strained-Si Layers in Channel Region of HOI MOSFET","authors":"Lalthanpuii Khiangte, Rudra Sankar Dhar","doi":"10.1109/EDKCON.2018.8770409","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770409","url":null,"abstract":"A heterostructure design with two strained silicon (s-Si) layers on both side of the middle layer strained silicon germanium (s-SiGe) layer, forming a tri-layered channel heterostructure-on-insulator (HOI) metal oxide semiconductor field effect transistor (MOSFET) have been developed. Quantum carrier confinement ensued within both the ultrathin s-Si layers, which instigates mobility enhancement, and hence counter balances the threshold voltage (Vth) roll-off due to the strained layers in the channel region. A comparison of the conventional single s-Si on relaxed SiGe channel HOI MOSFET with double s-Si channel HOI MOSFET have been perceived leading to eloquent drain current enhancement of $sim49%$ for channel length, Lg=100nm due to the captivity of carriers with trivial reduction in the threshold voltage caused on the additional bottom s-Si layer. An in depth analysis of the device in the nanoscale regime for Device-B (Lg=50nm) and Device-C (Lg=40nm) have exemplified superior device characteristic without scaling down the overall device geometry, leading to prominence of velocity overshoot condition under low-scattering effect, augmenting mobility and drift velocity, while approaching to the quasi ballistic carrier transport mechanism in the channel, therefore remarkably improving drive current of the nano-MOSFET.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128851357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770393
T. Halder
The paper addresses that the role of voltage and current ripple components have an impact on the performance of the boost converters. The dimension and effect of the nipple components are not taken care to examine the activities of the converter many cases and applications. The substantial effects and sensitivity of the voltage and current ripples on the power capacitor and inductor are presumed to ascertain the practical predictions and better performance of the boost converter for the practical engineer.
{"title":"An Impact of the Voltage & Current Ripples in the Power Stages of the Boost Converter","authors":"T. Halder","doi":"10.1109/EDKCON.2018.8770393","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770393","url":null,"abstract":"The paper addresses that the role of voltage and current ripple components have an impact on the performance of the boost converters. The dimension and effect of the nipple components are not taken care to examine the activities of the converter many cases and applications. The substantial effects and sensitivity of the voltage and current ripples on the power capacitor and inductor are presumed to ascertain the practical predictions and better performance of the boost converter for the practical engineer.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133849335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770449
C. Pandey, S. Chaudhury
In the presented work, a Tunnel FET device with dual-metal graded-channel structure is proposed and investigated showing the influence of energy band modulation at channel-drain interface on the ambipolar conduction. Through two-dimensional numerical simulations, it is demonstrated that a heavily-doped channel region adjacent to drain terminal along with lower work function gate material modulates the alignment of energy band profile of channel and drain regions at drain-channel interface which, further, increases the tunneling width in Tunnel FETs. Eventually, it leads to a significant reduction in band-to-band generation of charge carriers tunneling at drain-channel interface, thus causing a noticeable suppression in the nature of ambipolarity. The device performances of the presented structure is analysed through TCAD simulations to optimize length and doping concentration of two channel regions. Additionally, it is shown that the presented structure does not deteriorate subthreshold swing and ON-state current of Tunnel FETs.
{"title":"Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction","authors":"C. Pandey, S. Chaudhury","doi":"10.1109/EDKCON.2018.8770449","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770449","url":null,"abstract":"In the presented work, a Tunnel FET device with dual-metal graded-channel structure is proposed and investigated showing the influence of energy band modulation at channel-drain interface on the ambipolar conduction. Through two-dimensional numerical simulations, it is demonstrated that a heavily-doped channel region adjacent to drain terminal along with lower work function gate material modulates the alignment of energy band profile of channel and drain regions at drain-channel interface which, further, increases the tunneling width in Tunnel FETs. Eventually, it leads to a significant reduction in band-to-band generation of charge carriers tunneling at drain-channel interface, thus causing a noticeable suppression in the nature of ambipolarity. The device performances of the presented structure is analysed through TCAD simulations to optimize length and doping concentration of two channel regions. Additionally, it is shown that the presented structure does not deteriorate subthreshold swing and ON-state current of Tunnel FETs.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133721197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770429
A. Kushwaha, Ashok Kumar, Prakash Pareek
A novel third order sinusoidal oscillator based on current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) is proposed. The proposed circuit configuration using single CCDDCCTA, two grounded resistor and three capacitors has voltage and current outputs. It can concurrently yield output voltages and current and an amplitude controllable output current. The PSPICE simulation results are represented, the stated results agree well with the theoretical estimation. The performances of proposed oscillator are analyse with ORCAD 16.6 simulator and the analog block has been depicted using 0.25 μm CMOS TSMC technology parameters.
{"title":"Third Order Sinusoidal Oscillator Employing Single CCDDCCTA","authors":"A. Kushwaha, Ashok Kumar, Prakash Pareek","doi":"10.1109/EDKCON.2018.8770429","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770429","url":null,"abstract":"A novel third order sinusoidal oscillator based on current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) is proposed. The proposed circuit configuration using single CCDDCCTA, two grounded resistor and three capacitors has voltage and current outputs. It can concurrently yield output voltages and current and an amplitude controllable output current. The PSPICE simulation results are represented, the stated results agree well with the theoretical estimation. The performances of proposed oscillator are analyse with ORCAD 16.6 simulator and the analog block has been depicted using 0.25 μm CMOS TSMC technology parameters.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115394735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770222
Anup Dey, Bikram Biswas, S. Sarkar
WO3-ZnO and gold modified WO3-ZnO based thin film sensors were successfully fabricated and prepared by sol-gel process at room temperature. The prepared and deposited film was characterized by field emission scanning electron microscopy(FESEM), X-ray diffraction (XRD)and TEM (transmission electron microscopy). The gas sensing properties of Au modified WO3-ZnO thin film showed that deposited metal oxides have greatly influenced on enhanced response towards CH4 gases. The response magnitude was determined by various methane gas concentration and different operating temperature ranges of 50°C-350°C. It was establish that at the operating temperature of 150°C, gold- modified WO3-ZnO thin film sensor has the highest response (65%)as compared to WO3-ZnO samples.
{"title":"Comparative Study of Unmodified WO3-ZnO and Au-Modified WO3-ZnO Based Thin Film Sensor Fabrication for Enhanced CH4 Gas Sensing Performance","authors":"Anup Dey, Bikram Biswas, S. Sarkar","doi":"10.1109/EDKCON.2018.8770222","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770222","url":null,"abstract":"WO3-ZnO and gold modified WO3-ZnO based thin film sensors were successfully fabricated and prepared by sol-gel process at room temperature. The prepared and deposited film was characterized by field emission scanning electron microscopy(FESEM), X-ray diffraction (XRD)and TEM (transmission electron microscopy). The gas sensing properties of Au modified WO3-ZnO thin film showed that deposited metal oxides have greatly influenced on enhanced response towards CH4 gases. The response magnitude was determined by various methane gas concentration and different operating temperature ranges of 50°C-350°C. It was establish that at the operating temperature of 150°C, gold- modified WO3-ZnO thin film sensor has the highest response (65%)as compared to WO3-ZnO samples.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770477
Madhabi Ganguly, Subhro Ghosal, D. Ghosh
As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the ION/IOFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the ION/IOFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.
{"title":"A Study on Sensitivity of ION/IOFF Ratio of JLT to Structural Parameters","authors":"Madhabi Ganguly, Subhro Ghosal, D. Ghosh","doi":"10.1109/EDKCON.2018.8770477","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770477","url":null,"abstract":"As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the ION/IOFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the ION/IOFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770510
Sritoma Paul, Shubham Mondal, A. Sarkar
Design and analysis of a novel Enhancement-mode 120nm Ti-gate GaN based High Electron Mobility Transistor (HEMT) has been presented and its behavior in typical real-world circuits has been explored. The DC characteristics of the device reveal an on-state current density of 26.4A/mm, simultaneously achieving a sub-threshold swing of 70mV/decade. The simulated results show a peak transconductance of 15700mS/mm. The proposed device has been used to design a resistive load inverter and its characteristics have been extensively studied. The voltage transfer characteristics (VTC) display a maximum noise margin (NMH and NML) of 2.16V and O.76V respectively at a supply voltage of 5V. The transient response of the inverter for a pulsed DC input voltage exhibits a negligible propagation delay of 6ps and very high switching speed. The effect of the supply voltage and Al molar fraction in the barrier layer of the HEMT on the inverter characteristics has been further analyzed. The authors have also successfully investigated the behavior of a cascode amplifier developed using the novel GaN-HEMT.
{"title":"A Novel GaN-Hemt based Inverter and Cascode Amplifier","authors":"Sritoma Paul, Shubham Mondal, A. Sarkar","doi":"10.1109/EDKCON.2018.8770510","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770510","url":null,"abstract":"Design and analysis of a novel Enhancement-mode 120nm Ti-gate GaN based High Electron Mobility Transistor (HEMT) has been presented and its behavior in typical real-world circuits has been explored. The DC characteristics of the device reveal an on-state current density of 26.4A/mm, simultaneously achieving a sub-threshold swing of 70mV/decade. The simulated results show a peak transconductance of 15700mS/mm. The proposed device has been used to design a resistive load inverter and its characteristics have been extensively studied. The voltage transfer characteristics (VTC) display a maximum noise margin (NMH and NML) of 2.16V and O.76V respectively at a supply voltage of 5V. The transient response of the inverter for a pulsed DC input voltage exhibits a negligible propagation delay of 6ps and very high switching speed. The effect of the supply voltage and Al molar fraction in the barrier layer of the HEMT on the inverter characteristics has been further analyzed. The authors have also successfully investigated the behavior of a cascode amplifier developed using the novel GaN-HEMT.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770448
S. Palo, T. Sahu, A. K. Panda, N. Sahoo
We analyze the importance of non-square coupled double quantum well (QW) potential on electron transport property, e.g., electron mobility $mu$ in the QW based field effect transistor (FET). A cubic double QW (CD-QW) structure made of $Al_{x}Ga_{1-x}As$ alloy is taken whose side barriers are Si $delta$ -doped. We consider impurity $(imp-)$ and alloy $(al-)$ scatterings to calculate $mu$. Additional interface roughness $(ir-)$ scattering is taken for square double QW (SD-QW). Mostly $mu$ is controlled by $imp-$ scatterings because of the reduced effect of $al-$ disorder. It is gratifying to show that in CD-QW enhanced $mu$ is obtained as compared to the conventional SD-QW structure. Our analysis will be helpful for improving the channel conductivity in QW based FETs.
{"title":"Electron Transport in AlxGa1-x As based Non-Square Double Quantum Well Field Effect Transistor Structure","authors":"S. Palo, T. Sahu, A. K. Panda, N. Sahoo","doi":"10.1109/EDKCON.2018.8770448","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770448","url":null,"abstract":"We analyze the importance of non-square coupled double quantum well (QW) potential on electron transport property, e.g., electron mobility <tex>$mu$</tex> in the QW based field effect transistor (FET). A cubic double QW (CD-QW) structure made of <tex>$Al_{x}Ga_{1-x}As$</tex> alloy is taken whose side barriers are Si <tex>$delta$</tex> -doped. We consider impurity <tex>$(imp-)$</tex> and alloy <tex>$(al-)$</tex> scatterings to calculate <tex>$mu$</tex>. Additional interface roughness <tex>$(ir-)$</tex> scattering is taken for square double QW (SD-QW). Mostly <tex>$mu$</tex> is controlled by <tex>$imp-$</tex> scatterings because of the reduced effect of <tex>$al-$</tex> disorder. It is gratifying to show that in CD-QW enhanced <tex>$mu$</tex> is obtained as compared to the conventional SD-QW structure. Our analysis will be helpful for improving the channel conductivity in QW based FETs.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770502
P. Guin, A. Mallick, A. Roy
Harnessing and usability of electrical energy from piezofilm-based energy harvester is investigated. Three possible combinations such as parallel, series-parallel and series configurations of piezofilms are investigated for load carrying capability. A total of six mass loaded piezofilms are employed in this study. An artificial vibrator is used to simulate the ambient vibration to generate electrical energy from the piezofilms. A commercial passive converter is used to convert generated ac power into usable dc power. Load characteristics are obtained at different vibrating frequency for all the three configurations. Among these three configurations, experimentally it is found the parallel combination of the piezofilms is the best configuration as far power generation capability is concerned, even at low vibrating frequency. It is also noticed that, the peak power is obtained at almost equal load for the first two configurations while the same is found to be at larger load resistance for the last configuration. The possible reasons for differences in the load characteristics of the three configurations are discussed.
{"title":"Experimental Investigation of Load Characteristics of Piezofilm-based Energy Harvester","authors":"P. Guin, A. Mallick, A. Roy","doi":"10.1109/EDKCON.2018.8770502","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770502","url":null,"abstract":"Harnessing and usability of electrical energy from piezofilm-based energy harvester is investigated. Three possible combinations such as parallel, series-parallel and series configurations of piezofilms are investigated for load carrying capability. A total of six mass loaded piezofilms are employed in this study. An artificial vibrator is used to simulate the ambient vibration to generate electrical energy from the piezofilms. A commercial passive converter is used to convert generated ac power into usable dc power. Load characteristics are obtained at different vibrating frequency for all the three configurations. Among these three configurations, experimentally it is found the parallel combination of the piezofilms is the best configuration as far power generation capability is concerned, even at low vibrating frequency. It is also noticed that, the peak power is obtained at almost equal load for the first two configurations while the same is found to be at larger load resistance for the last configuration. The possible reasons for differences in the load characteristics of the three configurations are discussed.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127473977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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