Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770500
Himanshu Diwakar, S. Nayak, Rohit Kumar
Un-intentional misalignment in the gate due to fabrication leads to undesirable device performances. In this paper, effect of gate misalignment has been presented in single-material double-gate (SMDG) MOSFET, based on simulation. The source and drain are considered to be doped with lateral Gaussian doping profile. A simulation study is performed to analyze the gate misalignment effects on the performance. A combination of total four misalignment is simulated, the effects on surface potential, device I-V characteristics and transconductance has been studied. We consider the misalignment at drain and source side of both front and back gate. When misalignment is there both trans-conductance and drain current decreases. Misalignment from drain and source side decreases trans-conductance similarly, but for 45% misalignment in the front gate, 34.8% degradation in the drain current is observed while similar misalignment in back gate causes 57.5% degradation. For simulations 2-D simulations by ATLAS™ from Silvaco Inc. is used and surface potential profile is obtained.
{"title":"Study of Gate Misalignment Effects in Single-Material Double-Gate (SMDG) MOSFET Considering Source and Drain Lateral Gaussian Doping Profile","authors":"Himanshu Diwakar, S. Nayak, Rohit Kumar","doi":"10.1109/EDKCON.2018.8770500","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770500","url":null,"abstract":"Un-intentional misalignment in the gate due to fabrication leads to undesirable device performances. In this paper, effect of gate misalignment has been presented in single-material double-gate (SMDG) MOSFET, based on simulation. The source and drain are considered to be doped with lateral Gaussian doping profile. A simulation study is performed to analyze the gate misalignment effects on the performance. A combination of total four misalignment is simulated, the effects on surface potential, device I-V characteristics and transconductance has been studied. We consider the misalignment at drain and source side of both front and back gate. When misalignment is there both trans-conductance and drain current decreases. Misalignment from drain and source side decreases trans-conductance similarly, but for 45% misalignment in the front gate, 34.8% degradation in the drain current is observed while similar misalignment in back gate causes 57.5% degradation. For simulations 2-D simulations by ATLAS™ from Silvaco Inc. is used and surface potential profile is obtained.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770507
S. Mondal, P. Gayen, Kabita Gupta
This paper studies on the impact of LC filter parameters on the load-side output of three-phase voltage source inverter (VSI) under variable loading conditions. In practice, variable active and reactive load powers have to be met up by VSI based stand-alone system. In this context, the output-side passive parameters of LC filter plays beneficial role for reducing harmonic levels at the load terminals. But, the improper choice of the LC filter parameters can restrict the range of operation of VSI under variable isolated loading conditions. Therefore, this paper focuses on the investigation of the output power limit by the designed values of LC parameters. The influencing factors, design steps of LC filter are presented in the paper to justify the obtained result. The MATLAB-SIMULINK 2014b software is used to study the above said effects.
{"title":"Study on Impact of LC-Filter Parameters Under Variable Loading Conditions of Three-Phase Voltage Source Inverter","authors":"S. Mondal, P. Gayen, Kabita Gupta","doi":"10.1109/EDKCON.2018.8770507","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770507","url":null,"abstract":"This paper studies on the impact of LC filter parameters on the load-side output of three-phase voltage source inverter (VSI) under variable loading conditions. In practice, variable active and reactive load powers have to be met up by VSI based stand-alone system. In this context, the output-side passive parameters of LC filter plays beneficial role for reducing harmonic levels at the load terminals. But, the improper choice of the LC filter parameters can restrict the range of operation of VSI under variable isolated loading conditions. Therefore, this paper focuses on the investigation of the output power limit by the designed values of LC parameters. The influencing factors, design steps of LC filter are presented in the paper to justify the obtained result. The MATLAB-SIMULINK 2014b software is used to study the above said effects.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122475560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770395
A. Bhattacharya, Debadipta Basak, S. Reddy, S. Sarkar
This paper confers the results of the analysis of source and drain doping engineering for a 2D TFET model. Two different models have been extensively studied that are composed of split source and split drain region with varying doping concentration. Both the models consist of split drain, one with split source and another with double split source and are specified as Split Source Split Drain TFET (SS-SD TFET)and Double Split Source Split Drain TFET (DSS-SD TFET). The device characteristics are compared with Split Drain (SD TFET)model and the improvements are registered that exhibits reduction in ambipolar conduction (OFF current)along with the increase of tunneling effect. Simulations are performed using Silvaco, Atlas.
{"title":"Impact of Source Engineering in Split Drain Tunnel Field Effect Transistor","authors":"A. Bhattacharya, Debadipta Basak, S. Reddy, S. Sarkar","doi":"10.1109/EDKCON.2018.8770395","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770395","url":null,"abstract":"This paper confers the results of the analysis of source and drain doping engineering for a 2D TFET model. Two different models have been extensively studied that are composed of split source and split drain region with varying doping concentration. Both the models consist of split drain, one with split source and another with double split source and are specified as Split Source Split Drain TFET (SS-SD TFET)and Double Split Source Split Drain TFET (DSS-SD TFET). The device characteristics are compared with Split Drain (SD TFET)model and the improvements are registered that exhibits reduction in ambipolar conduction (OFF current)along with the increase of tunneling effect. Simulations are performed using Silvaco, Atlas.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770424
Sarita Misra, Sudhanshu Mohan Biswal, B. Bara, Sanjit Kumar Swain, Sudhansu Kumar Pati
In this work, we have accomplished an efficient quantitative inquiry on the analog/RF performance of gate-all-around (GAA) junction less Metal oxide field effect transistor(JL MOSFET).Here, we have considered the down scaled gate length and underlap length as two vital design aspects to inquiry the RF/analog performance of the device. A detailed analysis of some figure of merit (FOMs) such as transconductance $(mathrm{g}_{mathrm{m}})$, Outputresistance $(mathrm{R}_{mathrm{o}mathrm{u}mathrm{t}})$, transconductance generation factor(TGF), intrinsic gain, cut off frequency $(mathrm{f}_{mathrm{T}})$, maximum frequency of oscillation $(mathrm{f}_{max})$ are carried out in accordance with regular down scaling of length of gate and different underlap length towards drain and source. In this work, the recommended device is created and its electrical characteristics are studied using ATLAS 2D device simulator. From the results obtained from simulation it is evident that the RF performances of GAA JL-MOSFET are superior in comparison to their analog counterpart with respect to continual downscaling of gate length. The channel is controlled in gate all around structure which reduces the short channel in terms of drain induced barrier lowering and threshold voltage $(mathrm{V}_{mathrm{t}mathrm{h}})$ variation. GAA JL MOSFET is not only more immune to short channel effect(SCEs) but also it is suitable for analog/RF applications because of its high value of $mathrm{g}_{mathrm{m}}$ and $mathrm{f}_{mathrm{T}}, mathrm{f}_{max}$. Hence, this work will be beneficial for upcoming generation of RF circuits needed for modern wireless communication systems and high speed switching application.
{"title":"Study of Effect of downscaling on the Analog/RF Performance of Gate all Around JLMOSFET","authors":"Sarita Misra, Sudhanshu Mohan Biswal, B. Bara, Sanjit Kumar Swain, Sudhansu Kumar Pati","doi":"10.1109/EDKCON.2018.8770424","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770424","url":null,"abstract":"In this work, we have accomplished an efficient quantitative inquiry on the analog/RF performance of gate-all-around (GAA) junction less Metal oxide field effect transistor(JL MOSFET).Here, we have considered the down scaled gate length and underlap length as two vital design aspects to inquiry the RF/analog performance of the device. A detailed analysis of some figure of merit (FOMs) such as transconductance $(mathrm{g}_{mathrm{m}})$, Outputresistance $(mathrm{R}_{mathrm{o}mathrm{u}mathrm{t}})$, transconductance generation factor(TGF), intrinsic gain, cut off frequency $(mathrm{f}_{mathrm{T}})$, maximum frequency of oscillation $(mathrm{f}_{max})$ are carried out in accordance with regular down scaling of length of gate and different underlap length towards drain and source. In this work, the recommended device is created and its electrical characteristics are studied using ATLAS 2D device simulator. From the results obtained from simulation it is evident that the RF performances of GAA JL-MOSFET are superior in comparison to their analog counterpart with respect to continual downscaling of gate length. The channel is controlled in gate all around structure which reduces the short channel in terms of drain induced barrier lowering and threshold voltage $(mathrm{V}_{mathrm{t}mathrm{h}})$ variation. GAA JL MOSFET is not only more immune to short channel effect(SCEs) but also it is suitable for analog/RF applications because of its high value of $mathrm{g}_{mathrm{m}}$ and $mathrm{f}_{mathrm{T}}, mathrm{f}_{max}$. Hence, this work will be beneficial for upcoming generation of RF circuits needed for modern wireless communication systems and high speed switching application.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126363475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770443
A. Mondal, B. Maiti, Anup Dey
In this article, effect of strain on quantum capacitance of 2D intrinsic graphene has been investigated and the theoretical basis of its evolution has been formulated. The variation of quantum capacitance with applied strain has extensively been studied. It is observed that quantum capacitance not only depends on magnitude of applied strain but also depends on its direction. Under anisotropic strain field, the expression of quantum capacitance is calculated from density of states (DOS) using anisotropic dispersion energy in tight-binding approximation (TBA). This anisotropy in strain field causes accumulation of charge carriers in graphene without external bias and generates energy band gap. The strain-tunable band gap is introduced in the expression of quantum capacitance that would help to control the performance of high speed graphene devices by tuning the band gap applying anisotropic strain and would open up the possibility of designing new kind of graphene based field effect devices with very thin gate dielectric.
{"title":"Effect of Strain on Quantum Capacitance of Two Dimensional Intrinsic Graphene","authors":"A. Mondal, B. Maiti, Anup Dey","doi":"10.1109/EDKCON.2018.8770443","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770443","url":null,"abstract":"In this article, effect of strain on quantum capacitance of 2D intrinsic graphene has been investigated and the theoretical basis of its evolution has been formulated. The variation of quantum capacitance with applied strain has extensively been studied. It is observed that quantum capacitance not only depends on magnitude of applied strain but also depends on its direction. Under anisotropic strain field, the expression of quantum capacitance is calculated from density of states (DOS) using anisotropic dispersion energy in tight-binding approximation (TBA). This anisotropy in strain field causes accumulation of charge carriers in graphene without external bias and generates energy band gap. The strain-tunable band gap is introduced in the expression of quantum capacitance that would help to control the performance of high speed graphene devices by tuning the band gap applying anisotropic strain and would open up the possibility of designing new kind of graphene based field effect devices with very thin gate dielectric.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770422
M. Sutagundar, B. G. Sheeparamatti, D. S. Jangamshetti
This paper presents design optimization of MEMS disk resonator using interior point method. Determining the optimized dimensions of disk resonator for a particular resonance frequency and quality factor along with minimum possible motional resistance is attempted. The algorithm is implemented using MATLAB. The results obtained are compared with a fabricated device. The developed method can provide faster design optimization compared to full wave simulators resulting in significant reduction of design time.
{"title":"Design Optimization of Microdisk Resonator Using Interior Point Algorithm","authors":"M. Sutagundar, B. G. Sheeparamatti, D. S. Jangamshetti","doi":"10.1109/EDKCON.2018.8770422","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770422","url":null,"abstract":"This paper presents design optimization of MEMS disk resonator using interior point method. Determining the optimized dimensions of disk resonator for a particular resonance frequency and quality factor along with minimum possible motional resistance is attempted. The algorithm is implemented using MATLAB. The results obtained are compared with a fabricated device. The developed method can provide faster design optimization compared to full wave simulators resulting in significant reduction of design time.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770439
Subhrapratim Nath, Anup Dey, Prithviraj Pachal, S. Chowdhury, J. Sing, S. Sarkar
Nano gas sensing technology finds its importance where gas sensors used for detecting the toxic gases have been fabricated and modified gradually to enhance its sensitivity and selectivity. Timely and precise monitoring of flammable and hazardous gases inside the mines can aid preventing accidents. Previously Graphene mono-layer has been used as sensing material along with addition of Gold nano-particles on its surface as a sensor device. Various wired and wireless communication with the sensor nodes like Zigbee protocol, IBM Bluemix have been established in recent past and implemented with Internet of Things (IoT)but with limitations. In this paper fabrication of Au based TiO2, CuO, ZnO, WO3 resistive type gas sensors array using sol gel method is proposed for better conduction and Node MCU(ESP8266)is employed as a Wireless Fidelity (WiFi)module in this study which when implemented using Message Queuing Telemetry Transport (MQTT)protocol ensures better efficiency and speed. With increased sensitivity, selectivity and better efficiency the paper aims in resulting a better mine hazard management system.
{"title":"Nano Structured Gas Sensing Device and Its Application in Underground Mines","authors":"Subhrapratim Nath, Anup Dey, Prithviraj Pachal, S. Chowdhury, J. Sing, S. Sarkar","doi":"10.1109/EDKCON.2018.8770439","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770439","url":null,"abstract":"Nano gas sensing technology finds its importance where gas sensors used for detecting the toxic gases have been fabricated and modified gradually to enhance its sensitivity and selectivity. Timely and precise monitoring of flammable and hazardous gases inside the mines can aid preventing accidents. Previously Graphene mono-layer has been used as sensing material along with addition of Gold nano-particles on its surface as a sensor device. Various wired and wireless communication with the sensor nodes like Zigbee protocol, IBM Bluemix have been established in recent past and implemented with Internet of Things (IoT)but with limitations. In this paper fabrication of Au based TiO2, CuO, ZnO, WO3 resistive type gas sensors array using sol gel method is proposed for better conduction and Node MCU(ESP8266)is employed as a Wireless Fidelity (WiFi)module in this study which when implemented using Message Queuing Telemetry Transport (MQTT)protocol ensures better efficiency and speed. With increased sensitivity, selectivity and better efficiency the paper aims in resulting a better mine hazard management system.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770485
V. Kumari, Ayush Kumar, Mridula Gupta, M. Saxena
Sub-threshold model for advanced shell doped Double Gate Junctionless transistor has been presented in this work. Electrical parameters such as potential, threshold voltage Vth, leakage current Ioff, sub-threshold slopes SS and Drain Induced Barrier Lowering DIBL are evaluated analytically and compared with the results extracted from ATLAS TCAD software. Different configurations of shell doping have been used in this work such as: high-low-high, low-high-low, low-low-high and uniform. Obtained results shows that high-low-high doping profile of DG-JL transistor suppresses the leakage current more efficiently and also provide good sub-threshold slope and DIBL compared to uniform and other doping profiles. In shell doped DG-JL transistor, additional tuning parameter is present (i.e. the thickness of individual doping layer)which further helps in optimizing the device design for sub-20nm circuits' applications.
{"title":"Sub-Threshold Drain Current Model of Shell-Core Architecture Double Gate JunctionLess Transistor","authors":"V. Kumari, Ayush Kumar, Mridula Gupta, M. Saxena","doi":"10.1109/EDKCON.2018.8770485","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770485","url":null,"abstract":"Sub-threshold model for advanced shell doped Double Gate Junctionless transistor has been presented in this work. Electrical parameters such as potential, threshold voltage Vth, leakage current Ioff, sub-threshold slopes SS and Drain Induced Barrier Lowering DIBL are evaluated analytically and compared with the results extracted from ATLAS TCAD software. Different configurations of shell doping have been used in this work such as: high-low-high, low-high-low, low-low-high and uniform. Obtained results shows that high-low-high doping profile of DG-JL transistor suppresses the leakage current more efficiently and also provide good sub-threshold slope and DIBL compared to uniform and other doping profiles. In shell doped DG-JL transistor, additional tuning parameter is present (i.e. the thickness of individual doping layer)which further helps in optimizing the device design for sub-20nm circuits' applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770496
A. Deyasi, Biplab Sen, G. Saha, A. Sarkar
Differential conductance of submicron HEMT is analytically investigated as a function of drain bias for different structural parameters and parasitic effects. Simulation is carried out for two different substrate based devices, Si and sapphire, and comparative study is carried out for those structural parameters at which VGS provides maximum transconductance. Poisson's equation and carrier density equations are simultaneously solved to get drain current variations and parasitic effects are invoked through boundary conditions for realistic results. Result speaks that effect of threshold voltage is negligible on sapphire based device over a wider range of horizontal bias. Nanometric channel length provides almost constant conductance profile with insignificant magnitude.
{"title":"Analytical Investigation of Differential Conductance in Submicron HEMT with Two Different Substrates","authors":"A. Deyasi, Biplab Sen, G. Saha, A. Sarkar","doi":"10.1109/EDKCON.2018.8770496","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770496","url":null,"abstract":"Differential conductance of submicron HEMT is analytically investigated as a function of drain bias for different structural parameters and parasitic effects. Simulation is carried out for two different substrate based devices, Si and sapphire, and comparative study is carried out for those structural parameters at which VGS provides maximum transconductance. Poisson's equation and carrier density equations are simultaneously solved to get drain current variations and parasitic effects are invoked through boundary conditions for realistic results. Result speaks that effect of threshold voltage is negligible on sapphire based device over a wider range of horizontal bias. Nanometric channel length provides almost constant conductance profile with insignificant magnitude.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117075556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770419
Subhashis Roy, Anup Dey, Bikram Biswas, Sudhabindu Roy, S. Sarkar
In this paper, highly selective and highly sensitive hydrogen $(mathrm{H}_{2})$ sensing heterostructure gas sensor device is reported with a low cost electronic circuit for easy transmission of hydrogen leakage information. Mixing two different materials $text{WO}_{3}$ and ZnO at 1: 1 ratio with further modification by palladium (Pd)doping results high sensitivity 83.1 % and high selectiveness towards H2and low response and recovery time at 1000ppm (0.1%)H2concentration with respect to other fabricated bare WO3 and bare ZnO sensors. The sensor characteristics are studied using Scanning Electron Microscopy (SEM)and X-Ray Diffraction (XRD) methods which reveal particle size and mixing ratio information in nanoscale region. An easily implementable, low cost and reliable electronic circuit based on multivibrator interfacing with hydrogen sensor is also proposed in the present work which results highly accurate signal frequency variation from 14.1 KHz to 50.3 KHz for $mathrm{H}_{2}$ concentration variation from 0.02%-0.1 % for Pd modified $text{WO}_{3}-$ ZnO sensor.
{"title":"Low Temperature and Highly Selective H2 Sensing System Using WO3-ZnO Heterostructure Decorated with Pd Nanoparticle","authors":"Subhashis Roy, Anup Dey, Bikram Biswas, Sudhabindu Roy, S. Sarkar","doi":"10.1109/EDKCON.2018.8770419","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770419","url":null,"abstract":"In this paper, highly selective and highly sensitive hydrogen $(mathrm{H}_{2})$ sensing heterostructure gas sensor device is reported with a low cost electronic circuit for easy transmission of hydrogen leakage information. Mixing two different materials $text{WO}_{3}$ and ZnO at 1: 1 ratio with further modification by palladium (Pd)doping results high sensitivity 83.1 % and high selectiveness towards H2and low response and recovery time at 1000ppm (0.1%)H2concentration with respect to other fabricated bare WO3 and bare ZnO sensors. The sensor characteristics are studied using Scanning Electron Microscopy (SEM)and X-Ray Diffraction (XRD) methods which reveal particle size and mixing ratio information in nanoscale region. An easily implementable, low cost and reliable electronic circuit based on multivibrator interfacing with hydrogen sensor is also proposed in the present work which results highly accurate signal frequency variation from 14.1 KHz to 50.3 KHz for $mathrm{H}_{2}$ concentration variation from 0.02%-0.1 % for Pd modified $text{WO}_{3}-$ ZnO sensor.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116636712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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