Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770431
Sabuj Sarkar, Mostafizur Rahman
Most recent technological advancement of solar photovoltaic (PV) devices have dramatically increased the significant part of renewable energy worldwide through the generation of electric energy. The present paper proposes a novel model for achieving optimum power-energy (PE) from simulation and graphical representation of solar photovoltaic device (SPV) models. First power and current versus voltage performance is characterized. Later PV device output current versus output voltage characteristic is explained for initial as well as optimal parameter criterions. Finally, optimum power-energy is obtained from graphical representation of output power versus output voltage characteristic for proposed model with varying irradiance and temperature conditions. From the simulated and graphical performance analysis, it clearly exhibits the significant enhancement of power-energy and optimal PE is achieved from the novel SPV device model.
{"title":"Power-Energy Optimization of Solar Photovoltaic Device Modeling","authors":"Sabuj Sarkar, Mostafizur Rahman","doi":"10.1109/EDKCON.2018.8770431","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770431","url":null,"abstract":"Most recent technological advancement of solar photovoltaic (PV) devices have dramatically increased the significant part of renewable energy worldwide through the generation of electric energy. The present paper proposes a novel model for achieving optimum power-energy (PE) from simulation and graphical representation of solar photovoltaic device (SPV) models. First power and current versus voltage performance is characterized. Later PV device output current versus output voltage characteristic is explained for initial as well as optimal parameter criterions. Finally, optimum power-energy is obtained from graphical representation of output power versus output voltage characteristic for proposed model with varying irradiance and temperature conditions. From the simulated and graphical performance analysis, it clearly exhibits the significant enhancement of power-energy and optimal PE is achieved from the novel SPV device model.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770498
D. Mishra, K. Agrawal, R. S. Yadav, Tanuja Pande, N. K. Shukla
Robotics always used to have an extraordinary contribution into multiple parts of operations in process industries such as oil and gas industries, the one presently discussed in this research paper deals with the mathematical analysis and real-time replication model of out pipe crawler robot used for thickness measurement of ferromagnetic pipelines in petrochemical plants and refineries. The aim of this paper is to evaluate and simulate the movement of the robot in a 2-dimensional plane over a black track motif as a pipeline line which infers the effect of real-time simulation prototype model. The analysis presented in this paper is very useful in developing a mathematical model and crafting a prototype of wheelbase mobile robot to traverse over an uneven surface of ferromagnetic pipelines with the help of an array of IR sensors used for estimation of the thickness of pipes.
{"title":"Mathematical Analysis & Simulation for Designing Two Dimensional Out Pipe Crawler for Oil Industry","authors":"D. Mishra, K. Agrawal, R. S. Yadav, Tanuja Pande, N. K. Shukla","doi":"10.1109/EDKCON.2018.8770498","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770498","url":null,"abstract":"Robotics always used to have an extraordinary contribution into multiple parts of operations in process industries such as oil and gas industries, the one presently discussed in this research paper deals with the mathematical analysis and real-time replication model of out pipe crawler robot used for thickness measurement of ferromagnetic pipelines in petrochemical plants and refineries. The aim of this paper is to evaluate and simulate the movement of the robot in a 2-dimensional plane over a black track motif as a pipeline line which infers the effect of real-time simulation prototype model. The analysis presented in this paper is very useful in developing a mathematical model and crafting a prototype of wheelbase mobile robot to traverse over an uneven surface of ferromagnetic pipelines with the help of an array of IR sensors used for estimation of the thickness of pipes.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130719420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770441
Avtar Singh, S. Chaudhury, C. Sarkar, I. Hussain, A. Ganguly
An effective way to get multiple threshold voltage modulation scheme in Silicon nano tube FET combining unbalanced halo doping is proposed and verified by 3D TCAD Simulator. The typical choice to accomplish multiple threshold voltages is by choosing the appropriate gate work-function for each device. But this results in higher process complexity. In this report we demonstrate the multiple Vtsolution for Si-NTFET at 14 nm technology node. Using HALO at source side, the simulated DIBL (Drain induced Barrier Lowering)characteristics shows notable improvement.
{"title":"A Multi Vt Approach for Silicon Nanotube FET with Halo Implantation for Improved DIBL","authors":"Avtar Singh, S. Chaudhury, C. Sarkar, I. Hussain, A. Ganguly","doi":"10.1109/EDKCON.2018.8770441","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770441","url":null,"abstract":"An effective way to get multiple threshold voltage modulation scheme in Silicon nano tube FET combining unbalanced halo doping is proposed and verified by 3D TCAD Simulator. The typical choice to accomplish multiple threshold voltages is by choosing the appropriate gate work-function for each device. But this results in higher process complexity. In this report we demonstrate the multiple Vtsolution for Si-NTFET at 14 nm technology node. Using HALO at source side, the simulated DIBL (Drain induced Barrier Lowering)characteristics shows notable improvement.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770392
Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena
This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.
{"title":"Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications","authors":"Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena","doi":"10.1109/EDKCON.2018.8770392","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770392","url":null,"abstract":"This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770459
A. Adhikari, A. Roy
Electromigration-induced resistance change carries lot of information about the failure phenomenon and is an important aspect of the degradation process. Hence modeling electromigration-induced resistance degradation is of paramount importance, especially for submicron dual-damascene Cu interconnects. On the other hand, Markov model is extensively used in reliability engineering. This study focuses on the nature of the time-domain discrete states in the failure process. We argue about the memoryless discrete states in Markovian model to predict the electromigration-induced resistance degradation. The physics behind the electromigration failure does not support the application of Markovian model in electromigration and the inadequacy of such application is described. In contrast to the memoryless states, the resistance change behavior can be better explained by considering very generic and dependent discrete states. Whenever required, simulations are performed to obtain the resistance change behaviors. Our findings are concurrence with the experimental observations.
{"title":"Inadequacy of Markov Model in Modeling of Electromigration-Induced Resistance Degradation","authors":"A. Adhikari, A. Roy","doi":"10.1109/EDKCON.2018.8770459","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770459","url":null,"abstract":"Electromigration-induced resistance change carries lot of information about the failure phenomenon and is an important aspect of the degradation process. Hence modeling electromigration-induced resistance degradation is of paramount importance, especially for submicron dual-damascene Cu interconnects. On the other hand, Markov model is extensively used in reliability engineering. This study focuses on the nature of the time-domain discrete states in the failure process. We argue about the memoryless discrete states in Markovian model to predict the electromigration-induced resistance degradation. The physics behind the electromigration failure does not support the application of Markovian model in electromigration and the inadequacy of such application is described. In contrast to the memoryless states, the resistance change behavior can be better explained by considering very generic and dependent discrete states. Whenever required, simulations are performed to obtain the resistance change behaviors. Our findings are concurrence with the experimental observations.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129001039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770515
Kalyan Biswas, C. Sarkar
MOSFET devices with multiple gates are well appropriate for low-voltage operation because of its superior performance against Short Channel Effects (SCEs) and better gate controllability. FinFET is considered as one of the promising device. However, Fin geometry has a big impact on its performance. In this paper, an analysis on the effect of Fin structure parameter like Fin aspect ratio (Fin height/Fin width) on the Analog/RF performance of the Junctionless FinFET is presented for its SoC application. Different important output parameters such as OFF current $(mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}})$ ON current $(mathrm{I}_{mathrm{O}mathrm{N}}),mathrm{I}_{mathrm{O}mathrm{N}}{/}mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}$ current ratio, Transconductance $(mathrm{g}_{mathrm{m}})$ Transconductance Generation Factor $(mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{d}mathrm{s}})$ Cut-off Frequency $(mathrm{f}_{mathrm{T}})$ and Maximum frequency of oscillation $(mathrm{f}_{max})$ have been analyzed using TCAD device simulator. From the analysis it is established that the device presented in this work shows better $mathrm{I}_{mathrm{O}mathrm{N}}, mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}, mathrm{I}_{mathrm{O}mathrm{N}}/mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}$ Transconductance, and Transconductance generation factor if Fin structure having higher aspect ratio is used. However, slight decrement in $mathrm{f}_{mathrm{T}}$ and fmaxare noticed when the Fin aspect ratio is high. Findings of this work will be helpful for design of devices for its specific applications.
{"title":"Optimizing Fin Aspect Ratio of Junctionless Bulk FinFET for Application in Analog/RF Circuit","authors":"Kalyan Biswas, C. Sarkar","doi":"10.1109/EDKCON.2018.8770515","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770515","url":null,"abstract":"MOSFET devices with multiple gates are well appropriate for low-voltage operation because of its superior performance against Short Channel Effects (SCEs) and better gate controllability. FinFET is considered as one of the promising device. However, Fin geometry has a big impact on its performance. In this paper, an analysis on the effect of Fin structure parameter like Fin aspect ratio (Fin height/Fin width) on the Analog/RF performance of the Junctionless FinFET is presented for its SoC application. Different important output parameters such as OFF current $(mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}})$ ON current $(mathrm{I}_{mathrm{O}mathrm{N}}),mathrm{I}_{mathrm{O}mathrm{N}}{/}mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}$ current ratio, Transconductance $(mathrm{g}_{mathrm{m}})$ Transconductance Generation Factor $(mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{d}mathrm{s}})$ Cut-off Frequency $(mathrm{f}_{mathrm{T}})$ and Maximum frequency of oscillation $(mathrm{f}_{max})$ have been analyzed using TCAD device simulator. From the analysis it is established that the device presented in this work shows better $mathrm{I}_{mathrm{O}mathrm{N}}, mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}, mathrm{I}_{mathrm{O}mathrm{N}}/mathrm{I}_{mathrm{O}mathrm{F}mathrm{F}}$ Transconductance, and Transconductance generation factor if Fin structure having higher aspect ratio is used. However, slight decrement in $mathrm{f}_{mathrm{T}}$ and fmaxare noticed when the Fin aspect ratio is high. Findings of this work will be helpful for design of devices for its specific applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123207793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770452
Mithun Maity, A. Maiti, S. Gangopadhyay, Himadri S. Mandal
Employing the simple power series expression for fundamental modal field by Chebyshev technique, we report investigation of the effective core area and index of refraction of single mode graded index fiber in presence of Kerr nonlinearity. In this context, we apply iterative method in order to take care of the concerned nonlinearity. Taking some typical step and parabolic index fibers as examples, we show that the results found by our formalism agree excellently with the available exact results which can be obtained rigorously by applying finite element technique. The execution of our formalism requires little computation. Thus our formalism can be treated as a simple but accurate alternative to the complicated methods available in literature. Thus the prescribed simple formalism will prove user friendly for the system engineers in respect of judicious selection of this kind of fiber from the standpoint of minimisation of modal noise due to nonlinearity.
{"title":"Prediction of Effective Core Area and Index of Refraction of Single-Mode Graded Index Fiber in Presence of Kerr Nonlinearity","authors":"Mithun Maity, A. Maiti, S. Gangopadhyay, Himadri S. Mandal","doi":"10.1109/EDKCON.2018.8770452","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770452","url":null,"abstract":"Employing the simple power series expression for fundamental modal field by Chebyshev technique, we report investigation of the effective core area and index of refraction of single mode graded index fiber in presence of Kerr nonlinearity. In this context, we apply iterative method in order to take care of the concerned nonlinearity. Taking some typical step and parabolic index fibers as examples, we show that the results found by our formalism agree excellently with the available exact results which can be obtained rigorously by applying finite element technique. The execution of our formalism requires little computation. Thus our formalism can be treated as a simple but accurate alternative to the complicated methods available in literature. Thus the prescribed simple formalism will prove user friendly for the system engineers in respect of judicious selection of this kind of fiber from the standpoint of minimisation of modal noise due to nonlinearity.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770518
A. Basak, A. Sarkar
We propose a new 2D analytical modeling of dual material double gate MOSFET which worked as unipolar junction transistor. A region of $mathrm{N}+$ on the source terminal and a P-region on the drain and gate terminals are used to construct the structure of unipolar junction as a novel dual material dual gate MOSFET by forming an unipolar junction at the drain side. Here we observed different variation such as surface potential of the structure, distribution of electric field, threshold voltage, DIBL, subthreshold swings. These observations are analytically modeled to solve 2D Poisson's equation by applying parabolic approximation method. A comparative study for conventional double gate MOSFET (CDG), Unipolar junction single material double gate MOSFET (UJ-SMG) and unipolar junction dual material double gate MOSFET (UJ-DMDG) structures has been observed. Results reveal that UJ-DMDG MOSFET structure provides better result to suppress the short channel effect as compared to CDG and UJ-SMG MOSFET.
{"title":"Analytical Study of Unipolar Junction Transistor as a Novel Dual Material Double Gate MOSFET to Suppress Short-Channel Effect","authors":"A. Basak, A. Sarkar","doi":"10.1109/EDKCON.2018.8770518","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770518","url":null,"abstract":"We propose a new 2D analytical modeling of dual material double gate MOSFET which worked as unipolar junction transistor. A region of $mathrm{N}+$ on the source terminal and a P-region on the drain and gate terminals are used to construct the structure of unipolar junction as a novel dual material dual gate MOSFET by forming an unipolar junction at the drain side. Here we observed different variation such as surface potential of the structure, distribution of electric field, threshold voltage, DIBL, subthreshold swings. These observations are analytically modeled to solve 2D Poisson's equation by applying parabolic approximation method. A comparative study for conventional double gate MOSFET (CDG), Unipolar junction single material double gate MOSFET (UJ-SMG) and unipolar junction dual material double gate MOSFET (UJ-DMDG) structures has been observed. Results reveal that UJ-DMDG MOSFET structure provides better result to suppress the short channel effect as compared to CDG and UJ-SMG MOSFET.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122307138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770455
S. Srivastava, Shreya Nandy, Sonam Rewari, R. Gupta
In this paper, we have proposed Oxide Stack Engineered Double Surrounding Gate (OSE-DSG) MOSFET For Submillimeter Analog Application using SILVACO ATLAS 3D device simulator. Here, we have shown the comparison between the simulated results of OSE-DSG and the traditional MOSFETs- Surrounding Gate (SG-MOSFET), Surrounding Gate with Gate Stack MOSFET (SG-GS MOSFET) and Double Surrounding Gate MOSFET (DSG MOSFET) to analyze its performance and applications. It is observed that OSE-DSG MOSFET shows better performance as it has high Drain Current, Current Gain, Transconductance (gm) and Maximam Transducer Power Gain (MTPG). The subthreshold slope obtained for OSE-DSG MOSFET is 65 mV/decade which is nearest to the ideal value of 60 mV/decade so it is highly desirable for high-frequency applications.
{"title":"Oxide Stack Engineered Double Surrounding Gate (OSE-DSG) MOSFET for Submillimeter Analog Application","authors":"S. Srivastava, Shreya Nandy, Sonam Rewari, R. Gupta","doi":"10.1109/EDKCON.2018.8770455","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770455","url":null,"abstract":"In this paper, we have proposed Oxide Stack Engineered Double Surrounding Gate (OSE-DSG) MOSFET For Submillimeter Analog Application using SILVACO ATLAS 3D device simulator. Here, we have shown the comparison between the simulated results of OSE-DSG and the traditional MOSFETs- Surrounding Gate (SG-MOSFET), Surrounding Gate with Gate Stack MOSFET (SG-GS MOSFET) and Double Surrounding Gate MOSFET (DSG MOSFET) to analyze its performance and applications. It is observed that OSE-DSG MOSFET shows better performance as it has high Drain Current, Current Gain, Transconductance (gm) and Maximam Transducer Power Gain (MTPG). The subthreshold slope obtained for OSE-DSG MOSFET is 65 mV/decade which is nearest to the ideal value of 60 mV/decade so it is highly desirable for high-frequency applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770434
A. Hazra
Single and double layered TiO2nanotube array were synthesized by anodic oxidation method. Anodization voltage was varied to develop double layered TiO2nanotube array. Developed materials were characterized structurally and morphologically by X-ray diffraction spectroscopy (XRD)and field emission scanning electron microscopy (FESEM)respectively. Sandwich structure devices with Au top electrode and Ti bottom electrode were fabricated by using both single and double layered TiO2nanotubes for vapor sensing application. A simplified device modeling was introduced to establish the sensing mechanism of both the TiO2nanotube arrays. Additional interlayer junctions in double layered TiO2nanotubes array, enhanced the vapor sensing performance significantly. Double layered TiO2nanotubes array was able to show 92.4% of response magnitude for ethanol concentration of 160 ppm at 300 K where 55.2% response was observed for mono-layered TiO2nanotube array.
{"title":"Device Modeling of Double Layered TiO2 Nanotube Array Based Resistive Vapor Sensor","authors":"A. Hazra","doi":"10.1109/EDKCON.2018.8770434","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770434","url":null,"abstract":"Single and double layered TiO2nanotube array were synthesized by anodic oxidation method. Anodization voltage was varied to develop double layered TiO2nanotube array. Developed materials were characterized structurally and morphologically by X-ray diffraction spectroscopy (XRD)and field emission scanning electron microscopy (FESEM)respectively. Sandwich structure devices with Au top electrode and Ti bottom electrode were fabricated by using both single and double layered TiO2nanotubes for vapor sensing application. A simplified device modeling was introduced to establish the sensing mechanism of both the TiO2nanotube arrays. Additional interlayer junctions in double layered TiO2nanotubes array, enhanced the vapor sensing performance significantly. Double layered TiO2nanotubes array was able to show 92.4% of response magnitude for ethanol concentration of 160 ppm at 300 K where 55.2% response was observed for mono-layered TiO2nanotube array.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116169363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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