Pub Date : 2018-11-01DOI: 10.1109/edkcon.2018.8770497
{"title":"Proceedings of International conference on 2018 IEEE Electron Device Kolkata Conference (EDKCON)","authors":"","doi":"10.1109/edkcon.2018.8770497","DOIUrl":"https://doi.org/10.1109/edkcon.2018.8770497","url":null,"abstract":"","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770472
Priyanka Kakoty, M. Bhuyan
The work presented here focuses on the synthesis of Ag doped SnO2 based metal oxide semiconductor gas sensor using co-precipitation method and its performance evaluation towards some vital compounds responsible for the appealing aroma in tea. The sensor is tested to evaluate its response towards four noteworthy compounds (linalool, geraniol, methyl salicylate and trans-2-hexenal) present in the aroma matrix of black tea under diverse working temperature conditions. The prepared Ag doped SnO2 gas sensor exhibits improved sensitivity at a comparatively lesser working temperature (150°C) than the undoped SnO2 gas sensor. The proposed Ag doped sensor yields the highest sensitivity towards methyl salicylate(64.69%), an organic ester naturally synthesized by tea plants and is found in green, oolong and black tea. The physical characterization of the sensing material is carried out using XRD(x-ray diffraction), EDS(Energy dispersive X-ray spectroscopy) and SEM (scanning electron microscope). This research will aid in selecting an appropriate sensing material for detection of methyl salicylate which could help in the quality determination of tea.
{"title":"Study of Ag Doped SnO2 Film and its Response Towards Aromatic Compounds Present in Tea","authors":"Priyanka Kakoty, M. Bhuyan","doi":"10.1109/EDKCON.2018.8770472","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770472","url":null,"abstract":"The work presented here focuses on the synthesis of Ag doped SnO2 based metal oxide semiconductor gas sensor using co-precipitation method and its performance evaluation towards some vital compounds responsible for the appealing aroma in tea. The sensor is tested to evaluate its response towards four noteworthy compounds (linalool, geraniol, methyl salicylate and trans-2-hexenal) present in the aroma matrix of black tea under diverse working temperature conditions. The prepared Ag doped SnO2 gas sensor exhibits improved sensitivity at a comparatively lesser working temperature (150°C) than the undoped SnO2 gas sensor. The proposed Ag doped sensor yields the highest sensitivity towards methyl salicylate(64.69%), an organic ester naturally synthesized by tea plants and is found in green, oolong and black tea. The physical characterization of the sensing material is carried out using XRD(x-ray diffraction), EDS(Energy dispersive X-ray spectroscopy) and SEM (scanning electron microscope). This research will aid in selecting an appropriate sensing material for detection of methyl salicylate which could help in the quality determination of tea.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114765237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770442
S. Nayak, J. C. Dash, Himanshu Diwakar
RF switch is the potential alternative to replace the conventional electronic switch in high-speed applications. In this research, the design of an ohmic type piezoelectric actuated RF switch using two different piezo material such as PZT and ZnO are carried out. The switch is designed initially with the help of mathematical modeling and the modeling results are verified in the simulation environment. The fabrication steps are also highlighted for the switch along with the return loss and insertion loss associated with it.
{"title":"Low Loss Ohmic Type Piezoelectric Actuated RF MEMS Switch Designed with PZT and ZnO","authors":"S. Nayak, J. C. Dash, Himanshu Diwakar","doi":"10.1109/EDKCON.2018.8770442","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770442","url":null,"abstract":"RF switch is the potential alternative to replace the conventional electronic switch in high-speed applications. In this research, the design of an ohmic type piezoelectric actuated RF switch using two different piezo material such as PZT and ZnO are carried out. The switch is designed initially with the help of mathematical modeling and the modeling results are verified in the simulation environment. The fabrication steps are also highlighted for the switch along with the return loss and insertion loss associated with it.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127414774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770223
K. Girija Sravani, K. Guha, K. L. Baishnab, G. Shanti, K. S. Rao
In this paper, we have designed a novel step-down structure RF MEMS switch with low actuation voltage and high performance characteristics for K - band applications. A material for the beam and dielectric layer is chosen by the Ashby's methodology based on the key performance indices. The device has optimized by the parameters like Pull-In voltage, capacitance ratio and switching time. The stress distribution analysis and C - V characteristics ensures that the reliability of the switch. The switch is simulated using FEM tool to observe the electromechanical and electromagnetic performance characteristics. The proposed RF MEMS switch shows high isolation of −61dB is observed at 27 GHz during OFF state. During ON state, the switch exhibits a low insertion loss less than −1dB and low return loss of less than −10 dB in the K-band frequency range. The proposed switch structure is highly compatible to integrate with Antenna which is highly preferable technique to reconfigure antenna characteristics.
{"title":"Design of Low Pull-In Voltage and High Isolation of Step Structure Capacitive RF MEMS Switch for Satellite Applications","authors":"K. Girija Sravani, K. Guha, K. L. Baishnab, G. Shanti, K. S. Rao","doi":"10.1109/EDKCON.2018.8770223","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770223","url":null,"abstract":"In this paper, we have designed a novel step-down structure RF MEMS switch with low actuation voltage and high performance characteristics for K - band applications. A material for the beam and dielectric layer is chosen by the Ashby's methodology based on the key performance indices. The device has optimized by the parameters like Pull-In voltage, capacitance ratio and switching time. The stress distribution analysis and C - V characteristics ensures that the reliability of the switch. The switch is simulated using FEM tool to observe the electromechanical and electromagnetic performance characteristics. The proposed RF MEMS switch shows high isolation of −61dB is observed at 27 GHz during OFF state. During ON state, the switch exhibits a low insertion loss less than −1dB and low return loss of less than −10 dB in the K-band frequency range. The proposed switch structure is highly compatible to integrate with Antenna which is highly preferable technique to reconfigure antenna characteristics.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770408
Vikram Maharshi, V. Mere, A. Agarwal
This paper presents fabrication of thermally actuated multi-layered micro actuator for out of plane actuation application. Multi-layered actuators are fabricated using ammonium per sulphate based TMAH etching with metal passivation. Multi-layered $[text{Au}/text{Si}_{3}mathrm{N}_{4}/text{SiO}_{2}]$ micro actuators with straight and cross-heaters are characterized using I-V and LDV measurements. Gold as upper layer of micro actuator is fully protected during the release process. Fundamental mode or resonant frequency of fabricated multi-layered micro actuator is measured by Laser Doppler Vibrometer which is observed around 20 KHz.
{"title":"Multi -Layered Thermal Actuator Realization Using Metal Passivated TMAH Micro-Machining","authors":"Vikram Maharshi, V. Mere, A. Agarwal","doi":"10.1109/EDKCON.2018.8770408","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770408","url":null,"abstract":"This paper presents fabrication of thermally actuated multi-layered micro actuator for out of plane actuation application. Multi-layered actuators are fabricated using ammonium per sulphate based TMAH etching with metal passivation. Multi-layered $[text{Au}/text{Si}_{3}mathrm{N}_{4}/text{SiO}_{2}]$ micro actuators with straight and cross-heaters are characterized using I-V and LDV measurements. Gold as upper layer of micro actuator is fully protected during the release process. Fundamental mode or resonant frequency of fabricated multi-layered micro actuator is measured by Laser Doppler Vibrometer which is observed around 20 KHz.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770462
Jaya Madan, Rupinder Kaur, Rajnish Sharma, R. Pandey, R. Chaujar
Tunnel Field Effect Transistors (TFET)offers low leakage current and allows good scalability, however, they suffer from low ON-current. Here, in this work, the gate metal engineering scheme and n+ source pocket scheme has been integrated to overcome the major roadblocks of TFET. In this regard, 4 types of TFET architectures, namely the double gate TFET (DG-TFET), gate metal engineered DG-TFET (GME-DG-TFET), source pocket DG-TFET (SP-DG-TFET), and GME-SP-DG-TFET (which integrate the merits of GME and SP engineering)are investigated. The electrical characteristics and analog parameters in terms of surface potential, energy bands, band to band tunneling rate, electric field, drain current, current switching ratio, ambipolar current, threshold voltage, and subthreshold swing are assessed for all the devices. It is investigated that the combined merits of GME and SP consequently result in superior analog performance of DG-TFET. Remarkable improvement in terms of the ON-state drain current from an order of 1010 A to 1012A and decrease in Vth of 27.71% has been obtained for GME-SP-DG-TFET as compared to DG-TFET.
{"title":"Electrical Characteristics Assessment of Gate Metal and Source Pocket Engineered DG-TFET for Low Power Analog Applications","authors":"Jaya Madan, Rupinder Kaur, Rajnish Sharma, R. Pandey, R. Chaujar","doi":"10.1109/EDKCON.2018.8770462","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770462","url":null,"abstract":"Tunnel Field Effect Transistors (TFET)offers low leakage current and allows good scalability, however, they suffer from low ON-current. Here, in this work, the gate metal engineering scheme and n+ source pocket scheme has been integrated to overcome the major roadblocks of TFET. In this regard, 4 types of TFET architectures, namely the double gate TFET (DG-TFET), gate metal engineered DG-TFET (GME-DG-TFET), source pocket DG-TFET (SP-DG-TFET), and GME-SP-DG-TFET (which integrate the merits of GME and SP engineering)are investigated. The electrical characteristics and analog parameters in terms of surface potential, energy bands, band to band tunneling rate, electric field, drain current, current switching ratio, ambipolar current, threshold voltage, and subthreshold swing are assessed for all the devices. It is investigated that the combined merits of GME and SP consequently result in superior analog performance of DG-TFET. Remarkable improvement in terms of the ON-state drain current from an order of 1010 A to 1012A and decrease in Vth of 27.71% has been obtained for GME-SP-DG-TFET as compared to DG-TFET.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128113118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770394
N. Tripathy, S. Ghosh, D. Pradhan, J. Kar
Calcium copper titanate (CCTO) thin films were deposited on p-Si (100) substrates by RF magnetron sputtering technique. In order to improve the crystalline properties and to promote the phase formation, post-deposition annealing has been carried out by 3 different type of technique namely; conventional, rapid thermal and sequential annealing. All films have shown the evolution of CCTO peak in XRD pattern confirming the phase formation at 950 °C. Conventionally annealed films have shown better crystalline properties with lower FWHM. Al/CCTO/Si metal oxide semiconductor (MOS)structures were fabricated for electrical measurements. All films have shown bipolar resistive switching behavior with the sweep of bias voltage. Conventionally annealed film has shown good on/off ratio of 826 as compared to other samples. Double logarithmic plots of current-voltage behavior have depicted space charge limited conduction in all the films.
{"title":"Resistive Switching Behavior of RF Sputtered Calcium Copper Titanate Thin Films with Various Annealing Approach","authors":"N. Tripathy, S. Ghosh, D. Pradhan, J. Kar","doi":"10.1109/EDKCON.2018.8770394","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770394","url":null,"abstract":"Calcium copper titanate (CCTO) thin films were deposited on p-Si (100) substrates by RF magnetron sputtering technique. In order to improve the crystalline properties and to promote the phase formation, post-deposition annealing has been carried out by 3 different type of technique namely; conventional, rapid thermal and sequential annealing. All films have shown the evolution of CCTO peak in XRD pattern confirming the phase formation at 950 °C. Conventionally annealed films have shown better crystalline properties with lower FWHM. Al/CCTO/Si metal oxide semiconductor (MOS)structures were fabricated for electrical measurements. All films have shown bipolar resistive switching behavior with the sweep of bias voltage. Conventionally annealed film has shown good on/off ratio of 826 as compared to other samples. Double logarithmic plots of current-voltage behavior have depicted space charge limited conduction in all the films.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124820337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770492
Savio Jay Sengupta, Samarthi Chakraborty, Tamal Sarkar, Md. Zishan Iqbal, M. Chanda
Adiabatic logic style is efficient for the design and implementation of the low power, digital system, with reduced circuit delay. In this paper, effect of high K gate dielectric on the power dissipation and delay of the adiabatic logic circuits in sub-threshold regime for ultra-low power applications have been analysed in depth. Hence Energy Efficient Sub-Threshold Adiabatic Logic (EESAL)has been adopted as reference circuit. Besides, analytic models have been detailed to analyse the impact of temperature, supply voltage, capacitive load and frequency have been detailed for adiabatic logic circuits having different gate dielectric. Extensive SPICE simulations have been done to validate the analytical data. The analysis would be efficacious to choose the selective gate materials for the applications in the low power regime.
{"title":"Effect of High-K Dielectric on the Performances of Adiabatic Logic Circuits in Sub-Threshold Regime","authors":"Savio Jay Sengupta, Samarthi Chakraborty, Tamal Sarkar, Md. Zishan Iqbal, M. Chanda","doi":"10.1109/EDKCON.2018.8770492","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770492","url":null,"abstract":"Adiabatic logic style is efficient for the design and implementation of the low power, digital system, with reduced circuit delay. In this paper, effect of high K gate dielectric on the power dissipation and delay of the adiabatic logic circuits in sub-threshold regime for ultra-low power applications have been analysed in depth. Hence Energy Efficient Sub-Threshold Adiabatic Logic (EESAL)has been adopted as reference circuit. Besides, analytic models have been detailed to analyse the impact of temperature, supply voltage, capacitive load and frequency have been detailed for adiabatic logic circuits having different gate dielectric. Extensive SPICE simulations have been done to validate the analytical data. The analysis would be efficacious to choose the selective gate materials for the applications in the low power regime.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770474
S. Shaw, Sashank Poddar, Vivek Singh, Sudip Dogra
India being the largest democracy faces a lot of issues during elections. Lot of controversies are reported about voting system, voting machines, authentication of voting, corruptions during elections etc [1]. In our paper we have described a secured system that can eliminate such controversies involving elections in our country. In our present work we have developed a prototype and tested successfully an Arduino UNO based Aadhar facilitated electronic voting machine possessing a Two-Tier fingerprint security. The main purpose of this system is to give a straight and fair elections and to curb all other factors that affect it, this goal has been achieved by providing dual verification of the voters based on their fingerprint and unique id. In this System all the relevant information are taken from the voters and are stored in the database, then they are provided with unique ID. The process of verification involves matching of this id and fingerprint from the database. This is a faster and more secured way of holding elections. Our system is secured, reliable and also cost-effective.
{"title":"Design and Implementation of Arduino Based Voting Machine","authors":"S. Shaw, Sashank Poddar, Vivek Singh, Sudip Dogra","doi":"10.1109/EDKCON.2018.8770474","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770474","url":null,"abstract":"India being the largest democracy faces a lot of issues during elections. Lot of controversies are reported about voting system, voting machines, authentication of voting, corruptions during elections etc [1]. In our paper we have described a secured system that can eliminate such controversies involving elections in our country. In our present work we have developed a prototype and tested successfully an Arduino UNO based Aadhar facilitated electronic voting machine possessing a Two-Tier fingerprint security. The main purpose of this system is to give a straight and fair elections and to curb all other factors that affect it, this goal has been achieved by providing dual verification of the voters based on their fingerprint and unique id. In this System all the relevant information are taken from the voters and are stored in the database, then they are provided with unique ID. The process of verification involves matching of this id and fingerprint from the database. This is a faster and more secured way of holding elections. Our system is secured, reliable and also cost-effective.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770491
Rupinder Kaur, Jaya Madan, Rajnish Sharma, R. Pandey, R. Chaujar
Tunnel FETs overcome the limitations of conventional MOSFETs and offer wide scope for high speed switching analog/RF applications. In most of the research papers, the main focus is to improve the ION current and decrease the ambipolar current in TFETs. However, the parasitic capacitances and ambient temperature also play a crucial role in the performance analysis of the device. Here, in this research work, a Hetero-Material gate, n+ source pocket, dual-gate, TFET (HMG-PNIN-DG-TFET)is proposed for superior switching ratio and its CV analysis is presented for distinct temperature range. The parasitic capacitances have been analyzed with respect to gate and drain biasing for temperature range from 200K to 400K. In addition to it, the influence of temperature variations on transconductance (gm), cut-off frequency (fT)and intrinsic delay (τ)has also been evaluated. Analysis gives a huge prospect to realize efficient analog and RF circuitry with the device proposed (i.e. HMG-PNIN-DG-TFET)in this paper.
{"title":"Capacitive Analysis of Hetero Material Gate PNIN-DG-TFET Over Diverge Temperature Range for Superior RF/Microwave Performance","authors":"Rupinder Kaur, Jaya Madan, Rajnish Sharma, R. Pandey, R. Chaujar","doi":"10.1109/EDKCON.2018.8770491","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770491","url":null,"abstract":"Tunnel FETs overcome the limitations of conventional MOSFETs and offer wide scope for high speed switching analog/RF applications. In most of the research papers, the main focus is to improve the ION current and decrease the ambipolar current in TFETs. However, the parasitic capacitances and ambient temperature also play a crucial role in the performance analysis of the device. Here, in this research work, a Hetero-Material gate, n+ source pocket, dual-gate, TFET (HMG-PNIN-DG-TFET)is proposed for superior switching ratio and its CV analysis is presented for distinct temperature range. The parasitic capacitances have been analyzed with respect to gate and drain biasing for temperature range from 200K to 400K. In addition to it, the influence of temperature variations on transconductance (gm), cut-off frequency (fT)and intrinsic delay (τ)has also been evaluated. Analysis gives a huge prospect to realize efficient analog and RF circuitry with the device proposed (i.e. HMG-PNIN-DG-TFET)in this paper.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116569175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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