Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147463
Mitsuki Takahashi, H. Yano, N. Iwamuro, S. Harada
This study investigated the residual damage to 1.2 kV SiC trench MOSFETs after being subjected to single or multiple short-circuit stress tests. The SiC trench MOSFETs showed higher gate leakage current ($I_{mathrm{G}}$) than $S$ iC planar MOSFETs with short-circuit transient. However, the SiC planar MOSFETs showed a large positive shift of the $I_{mathrm{D}}-V_{text{GS}}$ curve after single short-circuit stress tests despite lower $I_{mathrm{G}}$, while the $S$ iC trench MOSFETs with higher $I_{mathrm{G}}$ did not show such degradation. This could be caused by electrons trapped in the higher density oxide traps in the SiC planar MOSFETs during the single short-circuit stress tests regardless of the size of $I_{mathrm{G}}$. It was also found that multiple short-circuit stress tests to the $S$ iC trench MOSFETs did not affect $I_{mathrm{D}}-V_{text{GS}}$ stability. These results indicate that SiC trench MOSFETs have superior stability against short-circuit stress compared to SiC planar MOSFETs.
{"title":"Investigations of Residual Damage in SiC Trench MOSFETs after Single and Multiple Short-Circuit Stress","authors":"Mitsuki Takahashi, H. Yano, N. Iwamuro, S. Harada","doi":"10.1109/ISPSD57135.2023.10147463","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147463","url":null,"abstract":"This study investigated the residual damage to 1.2 kV SiC trench MOSFETs after being subjected to single or multiple short-circuit stress tests. The SiC trench MOSFETs showed higher gate leakage current ($I_{mathrm{G}}$) than $S$ iC planar MOSFETs with short-circuit transient. However, the SiC planar MOSFETs showed a large positive shift of the $I_{mathrm{D}}-V_{text{GS}}$ curve after single short-circuit stress tests despite lower $I_{mathrm{G}}$, while the $S$ iC trench MOSFETs with higher $I_{mathrm{G}}$ did not show such degradation. This could be caused by electrons trapped in the higher density oxide traps in the SiC planar MOSFETs during the single short-circuit stress tests regardless of the size of $I_{mathrm{G}}$. It was also found that multiple short-circuit stress tests to the $S$ iC trench MOSFETs did not affect $I_{mathrm{D}}-V_{text{GS}}$ stability. These results indicate that SiC trench MOSFETs have superior stability against short-circuit stress compared to SiC planar MOSFETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128534581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147445
Chao Liu, Ziwen Chen, Qingyu Liu, Ruize Sun, Wanjun Chen, Zhaoji Li, Bo Zhang, Heng Deng, Yijun Shi
In this work, the dV/dt characteristics of silicon carbide super gate turn-off thyristor (SiC SGTO) is experimentally demonstrated and investigated for the first time. An analytical model of SiC GTO dV/dt immunity is established, which presents the mechanism of dV/dt effect on SiC SGTO. A specially designed SiC SGTO is fabricated and tested at different dV/dt conditions. It is shown that the fabricated SiC SGTO exhibits a high pulse current capability with peak current of 2.4 kA/cm2. And the dV/dt immunity of SiC SGTO changes with varying external gate resistance ($R_{load}$). At $R_{load}=0 Omega$, the device under test (DUT) does not be triggered at dV/dt of $124.8 text{kV}/mumathrm{s}$. While at $R_{load}=51 Omega$, the DUT is triggered at a relatively low dV/dt of $31.8 text{kV}/mumathrm{s}$.
{"title":"Experimental Demonstration of dV/dt Effect on Silicon Carbon SGTO for Pulse Power Applications","authors":"Chao Liu, Ziwen Chen, Qingyu Liu, Ruize Sun, Wanjun Chen, Zhaoji Li, Bo Zhang, Heng Deng, Yijun Shi","doi":"10.1109/ISPSD57135.2023.10147445","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147445","url":null,"abstract":"In this work, the dV/dt characteristics of silicon carbide super gate turn-off thyristor (SiC SGTO) is experimentally demonstrated and investigated for the first time. An analytical model of SiC GTO dV/dt immunity is established, which presents the mechanism of dV/dt effect on SiC SGTO. A specially designed SiC SGTO is fabricated and tested at different dV/dt conditions. It is shown that the fabricated SiC SGTO exhibits a high pulse current capability with peak current of 2.4 kA/cm2. And the dV/dt immunity of SiC SGTO changes with varying external gate resistance ($R_{load}$). At $R_{load}=0 Omega$, the device under test (DUT) does not be triggered at dV/dt of $124.8 text{kV}/mumathrm{s}$. While at $R_{load}=51 Omega$, the DUT is triggered at a relatively low dV/dt of $31.8 text{kV}/mumathrm{s}$.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125900841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147584
A. Takatsuka, Hironobu Miyamoto, K. Sasaki, A. Kuramata
Ampere-class $beta$-Ga2O3 trench heterojunction barrier Schottky diodes (THJBSs) were successfully developed for the first time. In fabrication, a lift-off process replacing an etching process was used to form $p$-type Cu2O that works as a heterojunction component, which contributed to the realization of ampere-class devices. Experimental results with the fabricated $beta$-Ga2O3 THJBSs indicate a turn-on voltage of 1.1 V, maximum current of 3.5 A, and specific on-resistance of $21 mathrm{m}Omegacdot text{cm}^{2}$ in forward characteristics. The breakdown voltage was −986 V with leakage current of $1.3times 10^{-3} mathrm{A}/text{cm}^{2}$ in reverse characteristics. In double-pulse measurements, the devices exhibited fast and low-loss switching behavior similar to general Schottky barrier diodes (SBDs), suggesting that the device operated with only majority carriers. In addition, from a high-temperature reverse-bias (HTRB) test, steady reverse current without breakdown was confirmed under the stress for 428 h. These results confirm that the ampere-class $beta$-Ga2O3 THJBSs are suitable for applications requiring fast switching, low loss, and high reliability.
{"title":"Fabrication of Ampere-Class $p$-Cu2O/$n-beta$-Ga2O3 Trench Heterojunction Barrier Schottky Diodes and Double-Pulse Evaluation","authors":"A. Takatsuka, Hironobu Miyamoto, K. Sasaki, A. Kuramata","doi":"10.1109/ISPSD57135.2023.10147584","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147584","url":null,"abstract":"Ampere-class <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> trench heterojunction barrier Schottky diodes (THJBSs) were successfully developed for the first time. In fabrication, a lift-off process replacing an etching process was used to form <tex>$p$</tex>-type Cu<inf>2</inf>O that works as a heterojunction component, which contributed to the realization of ampere-class devices. Experimental results with the fabricated <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> THJBSs indicate a turn-on voltage of 1.1 V, maximum current of 3.5 A, and specific on-resistance of <tex>$21 mathrm{m}Omegacdot text{cm}^{2}$</tex> in forward characteristics. The breakdown voltage was −986 V with leakage current of <tex>$1.3times 10^{-3} mathrm{A}/text{cm}^{2}$</tex> in reverse characteristics. In double-pulse measurements, the devices exhibited fast and low-loss switching behavior similar to general Schottky barrier diodes (SBDs), suggesting that the device operated with only majority carriers. In addition, from a high-temperature reverse-bias (HTRB) test, steady reverse current without breakdown was confirmed under the stress for 428 h. These results confirm that the ampere-class <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> THJBSs are suitable for applications requiring fast switching, low loss, and high reliability.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147719
Xing Liu, Xupeng Li, C. Herrmann, T. Basler
The impact of the dead-time on the body diode reverse recovery behavior for 1.2 kV silicon carbide MOSFETs has been studied in this paper. The plasma formation behavior of the body diode at different temperatures and load currents is investigated firstly. The time for the plasma stabilization can be estimated. Afterwards, the influence of the load current amplitude, the operating temperature, and the switching speed have been investigated with standard double-pulse tests. Different MOSFET cell designs of various manufacturers were compared. It has been found that selecting a suitable dead-time and switching speed is essential for the optimization of the overall losses, especially at higher operation temperatures.
{"title":"The Impact of the Dead-Time on the Reverse Recovery Behavior of SiC-MOSFET Body Diodes","authors":"Xing Liu, Xupeng Li, C. Herrmann, T. Basler","doi":"10.1109/ISPSD57135.2023.10147719","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147719","url":null,"abstract":"The impact of the dead-time on the body diode reverse recovery behavior for 1.2 kV silicon carbide MOSFETs has been studied in this paper. The plasma formation behavior of the body diode at different temperatures and load currents is investigated firstly. The time for the plasma stabilization can be estimated. Afterwards, the influence of the load current amplitude, the operating temperature, and the switching speed have been investigated with standard double-pulse tests. Different MOSFET cell designs of various manufacturers were compared. It has been found that selecting a suitable dead-time and switching speed is essential for the optimization of the overall losses, especially at higher operation temperatures.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147591
Junpei Okawara, Masaru Senoo, T. Nishiwaki, Y. Yamashita, S. Machida, Yuma Kagata, Masaki Konishi
We developed a new 1200-V reverse conducting insulated gate bipolar transistor with a structure called Schottky and multi-layered anode (a unique carrier injection control approach without lifetime-control) for TOYOTA's 5th generation hybrid electric vehicle and plug-in hybrid electric vehicle systems. The developed devices reduced total losses (conduction and switching losses) by 10% compared to the conventional product. It also reduced the number of parts for the power module and contributed to its 25% size reduction, ultimately contributing to the downsizing of 13% of the power control unit.
{"title":"Design of 1200-V RC-IGBT for TOYOTA's 5th generation HEV/PHEV systems","authors":"Junpei Okawara, Masaru Senoo, T. Nishiwaki, Y. Yamashita, S. Machida, Yuma Kagata, Masaki Konishi","doi":"10.1109/ISPSD57135.2023.10147591","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147591","url":null,"abstract":"We developed a new 1200-V reverse conducting insulated gate bipolar transistor with a structure called Schottky and multi-layered anode (a unique carrier injection control approach without lifetime-control) for TOYOTA's 5th generation hybrid electric vehicle and plug-in hybrid electric vehicle systems. The developed devices reduced total losses (conduction and switching losses) by 10% compared to the conventional product. It also reduced the number of parts for the power module and contributed to its 25% size reduction, ultimately contributing to the downsizing of 13% of the power control unit.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133118974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
700 V/2.5 A enhancement-mode (E-mode) ultrathin-barrier (UTB)-AlGaN (<6nm)/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) device was demonstrated on 6-inch GaN-on-Si wafers without AlGaN barrier recess. A combination of plasma-enhanced atomic-layer-deposited (PEALD) AlN and low-pressure chemical-vapor-deposited (LPCVD) SiNx passivation layer is adopted for the recovery of the two-dimensional electron gas (2DEG) in the access region of the E-mode UTB-AlGaN/GaN MIS-HEMTs. Compared to a controlled MOS-Channel-HEMT (MOSC-HEMT) with a fully recessed gate, the fabricated AlGaN-recess-free E-mode GaN-on-Si MIS-HEMTs exhibit a threshold voltage ($V_{text{TH}}$) of 0.1 V with good uniformity, a maximum drain current of 2.5 A, and a breakdown voltage over 700 V. The device also features a decent gate overdrive window and positive bias temperature instability (PBTI). The UTB-AlGaN/GaN-on-Si technology platform is highly preferred for an AlGaN-recess-free fabrication and integration of GaN-based power devices and ICs.
{"title":"700 V/2.5 A Normally-off Ultrathin-barrier AlGaN(<6nm)/GaN MIS-HEMTs with Improved Gate Overdrive Window and PBTI","authors":"T. Luan, Sen Huang, Yixu Yao, Q. Jiang, Yuhao Wang, Yifei Huang, Chao Feng, Xinhua Wang, Xinyu Liu, Ronghua Wang, Yongshuo Ren, Wanxi Cheng, Huinan Liang","doi":"10.1109/ISPSD57135.2023.10147548","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147548","url":null,"abstract":"700 V/2.5 A enhancement-mode (E-mode) ultrathin-barrier (UTB)-AlGaN (<6nm)/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) device was demonstrated on 6-inch GaN-on-Si wafers without AlGaN barrier recess. A combination of plasma-enhanced atomic-layer-deposited (PEALD) AlN and low-pressure chemical-vapor-deposited (LPCVD) SiNx passivation layer is adopted for the recovery of the two-dimensional electron gas (2DEG) in the access region of the E-mode UTB-AlGaN/GaN MIS-HEMTs. Compared to a controlled MOS-Channel-HEMT (MOSC-HEMT) with a fully recessed gate, the fabricated AlGaN-recess-free E-mode GaN-on-Si MIS-HEMTs exhibit a threshold voltage ($V_{text{TH}}$) of 0.1 V with good uniformity, a maximum drain current of 2.5 A, and a breakdown voltage over 700 V. The device also features a decent gate overdrive window and positive bias temperature instability (PBTI). The UTB-AlGaN/GaN-on-Si technology platform is highly preferred for an AlGaN-recess-free fabrication and integration of GaN-based power devices and ICs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131635973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147734
Zhen-Hong Huang, Wei-Syuan Lin, T. Lo, Shun-Wei Tang, Szu-Chia Chen, D. Wellekens, M. Borga, N. Posthuma, B. Bakeroot, S. Decoutere, Tian-Li Wu
Ultra-fast positive gate bias stress (<100ns) in p-GaN HEMTs is reported for the first time to investigate the hole injection/trapping phenomena in power p-GaN HEMTs, including the analysis from the time-dependent TCAD simulations. The results indicate that the negative threshold voltage (VTH) shift caused by the hole injection and trapping can be minimized under the ultra-fast positive gate bias, suggesting that p-GaN power HEMTs are promising for the fast turn-on operation that can be immune to PBTI instability.
{"title":"Ultra-Fast Positive Gate Bias Stress (<100ns) to Understand the Hole Injection in Power p-GaN HEMTs","authors":"Zhen-Hong Huang, Wei-Syuan Lin, T. Lo, Shun-Wei Tang, Szu-Chia Chen, D. Wellekens, M. Borga, N. Posthuma, B. Bakeroot, S. Decoutere, Tian-Li Wu","doi":"10.1109/ISPSD57135.2023.10147734","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147734","url":null,"abstract":"Ultra-fast positive gate bias stress (<100ns) in p-GaN HEMTs is reported for the first time to investigate the hole injection/trapping phenomena in power p-GaN HEMTs, including the analysis from the time-dependent TCAD simulations. The results indicate that the negative threshold voltage (VTH) shift caused by the hole injection and trapping can be minimized under the ultra-fast positive gate bias, suggesting that p-GaN power HEMTs are promising for the fast turn-on operation that can be immune to PBTI instability.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133846503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147729
Junji Cheng, Tao Zhong, B. Yi, Haimeng Huang, Keqiang Ma, Xinkai Guo, Hongqiang Yang, Zhiming Wang, Guoyi Zhang
A novel lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with fourfold charge-compensation is proposed. The first feature of the proposed device is that a P-bury layer and a surface high-$k$ (HK) film jointly compensate the drift region in an all-round way. The second feature is that the HK film is also contributed to resisting the adverse effects caused by charge deviations. Hence, due to the above two features, the proposed device is able to obtain not only excellent performance but also good robustness. According to the simulation results, in comparison with the conventional LDMOS with single, double and triple charge-compensation, the proposed one gets a specific on-resistance reduced by 48%, 37% and 17%, respectively. Its figure of merit reaches 15.7 MW/cm2, which is superior to the prior art. Moreover, the proposed device presents much better immunity to the charge deviations and the interface charges.
{"title":"A Novel Lateral Power MOSFET with Ultra-low Energy Consumption and Extraordinary Robustness","authors":"Junji Cheng, Tao Zhong, B. Yi, Haimeng Huang, Keqiang Ma, Xinkai Guo, Hongqiang Yang, Zhiming Wang, Guoyi Zhang","doi":"10.1109/ISPSD57135.2023.10147729","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147729","url":null,"abstract":"A novel lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with fourfold charge-compensation is proposed. The first feature of the proposed device is that a P-bury layer and a surface high-$k$ (HK) film jointly compensate the drift region in an all-round way. The second feature is that the HK film is also contributed to resisting the adverse effects caused by charge deviations. Hence, due to the above two features, the proposed device is able to obtain not only excellent performance but also good robustness. According to the simulation results, in comparison with the conventional LDMOS with single, double and triple charge-compensation, the proposed one gets a specific on-resistance reduced by 48%, 37% and 17%, respectively. Its figure of merit reaches 15.7 MW/cm2, which is superior to the prior art. Moreover, the proposed device presents much better immunity to the charge deviations and the interface charges.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147490
Jiawei Cui, Yanlin Wu, Junjie Yang, Jingjing Yu, Teng Li, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei
This study presents an investigation of high-voltage enhancement-mode p-GaN gate HEMTs on a sapphire substrate. The breakdown voltage of the devices shows a linear relationship with the $L_{text{GD}}$. For $L_{text{GD}}=27 mumathrm{m}$, the device exhibits a high breakdown voltage of 1412 V. The threshold voltage is 0.9 V. The $R_{text{on}}$ is $17.7 Omegacdot text{mm}$, and the specific on-resistance $R_{text{sp}}$ is $6.73 mathrm{m}Omegacdot text{cm}^{2}$. To measure the depletion region directly for high-voltage devices, depletion-testing structures were fabricated alongside the HEMTs. The depletion lengths were determined based on the I-$V$ characteristics of the structures, with the pinch-off voltage of the I-$V$ characteristics correlated to the depletion length. Additionally, using pulse waveforms as the gate control signals, the formation of the depletion region under dynamic conditions was revealed.
{"title":"Method to Study Dynamic Depletion Behaviors in High-Voltage ($BV=1.4 text{kV}$) p-GaN Gate HEMT on Sapphire Substrate","authors":"Jiawei Cui, Yanlin Wu, Junjie Yang, Jingjing Yu, Teng Li, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei","doi":"10.1109/ISPSD57135.2023.10147490","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147490","url":null,"abstract":"This study presents an investigation of high-voltage enhancement-mode p-GaN gate HEMTs on a sapphire substrate. The breakdown voltage of the devices shows a linear relationship with the $L_{text{GD}}$. For $L_{text{GD}}=27 mumathrm{m}$, the device exhibits a high breakdown voltage of 1412 V. The threshold voltage is 0.9 V. The $R_{text{on}}$ is $17.7 Omegacdot text{mm}$, and the specific on-resistance $R_{text{sp}}$ is $6.73 mathrm{m}Omegacdot text{cm}^{2}$. To measure the depletion region directly for high-voltage devices, depletion-testing structures were fabricated alongside the HEMTs. The depletion lengths were determined based on the I-$V$ characteristics of the structures, with the pinch-off voltage of the I-$V$ characteristics correlated to the depletion length. Additionally, using pulse waveforms as the gate control signals, the formation of the depletion region under dynamic conditions was revealed.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147581
Chun-wang Zhuang, Xin Ming, Zijie Ye, Yao Qin, Zhikang Lin, W. Li, H. Yan, Bo Zhang
For monolithic GaN LiDAR driver, in order to achieve high speed narrow pulse and low power consumption, pre-boosting and robust dead time (PBRD) control is proposed to enhance pull-up capability and limit short-through current during transient. A non-BGR under-voltage lockout (UVLO) is also provided for preventing the driver from operating in the event of supply voltage failure. Experimental results show that the proposed driver achieves peak load current of 10A and 2ns pulse width at the operation frequency of 20MHz. The fall and rise time of output pulse are 310ps and 334ps, respectively, and measured dynamic power is 80mW at the operation frequency of 10MHz.
{"title":"Monolithic FET-Controlled GaN Driver with Pre-Boosting and Robust Dead Time Control for DToF LiDAR Application","authors":"Chun-wang Zhuang, Xin Ming, Zijie Ye, Yao Qin, Zhikang Lin, W. Li, H. Yan, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147581","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147581","url":null,"abstract":"For monolithic GaN LiDAR driver, in order to achieve high speed narrow pulse and low power consumption, pre-boosting and robust dead time (PBRD) control is proposed to enhance pull-up capability and limit short-through current during transient. A non-BGR under-voltage lockout (UVLO) is also provided for preventing the driver from operating in the event of supply voltage failure. Experimental results show that the proposed driver achieves peak load current of 10A and 2ns pulse width at the operation frequency of 20MHz. The fall and rise time of output pulse are 310ps and 334ps, respectively, and measured dynamic power is 80mW at the operation frequency of 10MHz.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116543299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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