Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147580
C. Scognamillo, A. P. Catalano, Enzo D'Alessandro, H. J. Jaber, A. Castellazzi
This paper presents the development of a fully-coupled electro-thermal model for a highly integrated half-brdige GaN power switch in surface mount packaging. The device under test represents a relatively complex system, characterized by 3D electrical and thermal interconnectivity and very challenging, if not impossible, comprehensive thermal characterization. Thus, the development and validation of an accurate, yet computationally efficient simulation model is a powerful tool for the design and development of high-frequency high-power-density power conversion solutions based on GaN technology.
{"title":"Coupled structural and functional characterization and modelling of integrated GaN half-bridge power switches","authors":"C. Scognamillo, A. P. Catalano, Enzo D'Alessandro, H. J. Jaber, A. Castellazzi","doi":"10.1109/ISPSD57135.2023.10147580","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147580","url":null,"abstract":"This paper presents the development of a fully-coupled electro-thermal model for a highly integrated half-brdige GaN power switch in surface mount packaging. The device under test represents a relatively complex system, characterized by 3D electrical and thermal interconnectivity and very challenging, if not impossible, comprehensive thermal characterization. Thus, the development and validation of an accurate, yet computationally efficient simulation model is a powerful tool for the design and development of high-frequency high-power-density power conversion solutions based on GaN technology.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147712
T. Pham, J. Franchi, K. Lee, M. Domeij
The paper extends the investigation of the body diode (BD) turn-off process for 1.2 kV SiC MOSFETs [1]. Here, we investigate the devices under high current density (J=675 A/cm2), fast switching (turn-on di/dt up to 6 A/ns) and high temperature conditions (T=175°C). The different aspects of body diode (BD) channel conduction, on-state carrier plasma and parasitic turn-on (PTO) are analysed in detail.
本文扩展了1.2 kV SiC mosfet体二极管(BD)关断过程的研究[1]。在这里，我们研究了高电流密度(J=675 A/cm2)、快速开关(开通di/dt高达6 A/ns)和高温条件(T=175℃)下的器件。详细分析了体二极管(BD)通道导通、导通状态载流子等离子体和寄生导通(PTO)的不同方面。
{"title":"1.2 kV SiC MOSFET Body Diode Turn-Off in Fast Switching: Channel Conduction, Carrier Plasma and Parasitic Turn-On","authors":"T. Pham, J. Franchi, K. Lee, M. Domeij","doi":"10.1109/ISPSD57135.2023.10147712","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147712","url":null,"abstract":"The paper extends the investigation of the body diode (BD) turn-off process for 1.2 kV SiC MOSFETs [1]. Here, we investigate the devices under high current density (J=675 A/cm2), fast switching (turn-on di/dt up to 6 A/ns) and high temperature conditions (T=175°C). The different aspects of body diode (BD) channel conduction, on-state carrier plasma and parasitic turn-on (PTO) are analysed in detail.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147424
Akifumi Iijima, K. Kawahara, Katsutoshi Sugawara, S. Hino, Katsuhiro Fujiyoshi, Y. Oritsuki, Takeshi Murakami, Tetsuo Takahashi, Y. Kagawa, Yoichi Hironaka, K. Nishikawa
A novel structure named bipolar mode activation cell (BMA cell) is demonstrated to prevent current crowding in parallel connections of SBD-embedded SiC-MOSFETs during a surge current event. In a BMA cell, where the SBD area is partly filled with p-body to inactivate the corresponding part of SBD, I-V characteristics are uniform for each parallel-connected device under a surge condition. The parallel-connected devices with BMA cell have more than 5 times higher surge current capability compared with the conventional devices owing to the absence of current crowding.
{"title":"Improving Surge Current Capability of SBD-Embedded SiC-MOSFETs in Parallel Connection by Applying Bipolar Mode Activation Cells","authors":"Akifumi Iijima, K. Kawahara, Katsutoshi Sugawara, S. Hino, Katsuhiro Fujiyoshi, Y. Oritsuki, Takeshi Murakami, Tetsuo Takahashi, Y. Kagawa, Yoichi Hironaka, K. Nishikawa","doi":"10.1109/ISPSD57135.2023.10147424","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147424","url":null,"abstract":"A novel structure named bipolar mode activation cell (BMA cell) is demonstrated to prevent current crowding in parallel connections of SBD-embedded SiC-MOSFETs during a surge current event. In a BMA cell, where the SBD area is partly filled with p-body to inactivate the corresponding part of SBD, I-V characteristics are uniform for each parallel-connected device under a surge condition. The parallel-connected devices with BMA cell have more than 5 times higher surge current capability compared with the conventional devices owing to the absence of current crowding.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130212813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147511
Nathan Yee, A. Lu, Y. Wang, M. Porter, Yuhao Zhang, H. Wong
GaN-on-GaN vertical diode is a promising device for next-generation power electronics. Its breakdown voltage (BV) is limited by edge termination designs such as guard rings. The design space of guard rings is huge and it is difficult to optimize manually. In this paper, we propose an effective inverse design strategy to co-optimize BV and (VFQ)−1, where BV, VF, and Q are the breakdown voltage, forward voltage, and reserve capacitive charge of the diode, respectively. Using rapid Technology Computer-Aided-Design (TCAD) simulations, neural network (NN), and Pareto front generation, a GaN-on-GaN diode is optimized within 24 hours. We can obtain structures with 200V higher BV at medium (VFQ)−1 or find a nearly ideal BV structure with 25% higher BV2/Ron compared to the best randomly generated TCAD data.
{"title":"Rapid Inverse Design of GaN-on-GaN Diode with Guard Ring Termination for BV and (VFQ)−1 Co-Optimization","authors":"Nathan Yee, A. Lu, Y. Wang, M. Porter, Yuhao Zhang, H. Wong","doi":"10.1109/ISPSD57135.2023.10147511","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147511","url":null,"abstract":"GaN-on-GaN vertical diode is a promising device for next-generation power electronics. Its breakdown voltage (BV) is limited by edge termination designs such as guard rings. The design space of guard rings is huge and it is difficult to optimize manually. In this paper, we propose an effective inverse design strategy to co-optimize BV and (VFQ)−1, where BV, VF, and Q are the breakdown voltage, forward voltage, and reserve capacitive charge of the diode, respectively. Using rapid Technology Computer-Aided-Design (TCAD) simulations, neural network (NN), and Pareto front generation, a GaN-on-GaN diode is optimized within 24 hours. We can obtain structures with 200V higher BV at medium (VFQ)−1 or find a nearly ideal BV structure with 25% higher BV2/Ron compared to the best randomly generated TCAD data.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134348239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147450
F. Zhou, Weizong Xu, Yulei Jin, Tianyang Zhou, F. Ren, Dong Zhou, Yuanyang Xia, Leke Wu, Yih-Juan Li, T. Zhu, Dunjun Chen, Rong Zhang, Youdou Zheng, Hai Lu
In this work, the low-loss reverse conduction and high threshold voltage characteristics are simultaneously demonstrated in 1 kV/10 A $p$-GaN high electron mobility transistors (HEMTs) on an existing 6-inch process platform, thanks to the combined advantages of the uniquely designed source-controlled p-GaN hybrid structure and improved gate-stack layer. The reverse-conduction turn-on voltage of the resultant device is effectively decoupled from the threshold voltage and gate bias, which is different from the conventional p-GaN gate HEMTs. In addition, superior dynamic performances with nanosecond reverse recovery and switching characteristics are also realized, revealing the notable potentials of the high-$V_{text{TH}}$ low-loss p-GaN HEMTs for high-power and high-frequency applications.
在这项工作中，由于独特设计的源控p-GaN混合结构和改进的栅极堆叠层的综合优势，在现有的6英寸工艺平台上，在1 kV/10 A p-GaN高电子迁移率晶体管(hemt)中同时展示了低损耗反导和高阈值电压特性。与传统的p-GaN栅极hemt不同，该器件的反向导通电压与阈值电压和栅极偏置有效解耦。此外，还实现了具有纳秒级反向恢复和开关特性的优异动态性能，揭示了高V_{text{TH}}$低损耗p-GaN hemt在高功率和高频应用中的显着潜力。
{"title":"3.0-V-Threshold-Voltage p-GaN HEMTs with Low-Loss Reverse Conduction capability","authors":"F. Zhou, Weizong Xu, Yulei Jin, Tianyang Zhou, F. Ren, Dong Zhou, Yuanyang Xia, Leke Wu, Yih-Juan Li, T. Zhu, Dunjun Chen, Rong Zhang, Youdou Zheng, Hai Lu","doi":"10.1109/ISPSD57135.2023.10147450","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147450","url":null,"abstract":"In this work, the low-loss reverse conduction and high threshold voltage characteristics are simultaneously demonstrated in 1 kV/10 A $p$-GaN high electron mobility transistors (HEMTs) on an existing 6-inch process platform, thanks to the combined advantages of the uniquely designed source-controlled p-GaN hybrid structure and improved gate-stack layer. The reverse-conduction turn-on voltage of the resultant device is effectively decoupled from the threshold voltage and gate bias, which is different from the conventional p-GaN gate HEMTs. In addition, superior dynamic performances with nanosecond reverse recovery and switching characteristics are also realized, revealing the notable potentials of the high-$V_{text{TH}}$ low-loss p-GaN HEMTs for high-power and high-frequency applications.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114055455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For most of the vertical power devices, the n-GaN drift layers were fabricated by Metal Organic Chemical Vapor Deposition (MOCVD), which would unintentionally introduce carbon atoms related to deep levels within the band gap of the GaN epitaxial layer1, 2, 3. Further, in order to reduce the power consumption, many works have been done to reduce the on-resistance ($R_{ON}$) and turn-on voltage ($V_{ON}$) of devices4, 5, 6. In this work, high quality n-GaN drift layer with low carbon impurity concentration grown by Hydride Vapor Phase Epitaxy (HVPE) was first demonstrated. Also, indium tin oxide (ITO) technology and O2 plasma treatment (OPT) were employed to achieve the $R_{ON}(1.24 mathrm{m}Omegacdot text{cm}^{2})$ and $V_{ON}$ (0.37 V) for the ∼1.2 kV Schottky barrier diode.
{"title":"Vertical GaN Schottky Barrier Diode with Record High FOM (1.23GW/cm2) Fully Grown by Hydride Vapor Phase Epitaxy","authors":"Ping Zou, Haofan Wang, Junye Wu, Zeliang Liao, Shuangwu Huang, Z. Zhong, Xiaobo Li, Feng Qiu, Wenrong Zhuang, Longkou Chen, Xinke Liu","doi":"10.1109/ISPSD57135.2023.10147551","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147551","url":null,"abstract":"For most of the vertical power devices, the n-GaN drift layers were fabricated by Metal Organic Chemical Vapor Deposition (MOCVD), which would unintentionally introduce carbon atoms related to deep levels within the band gap of the GaN epitaxial layer1, 2, 3. Further, in order to reduce the power consumption, many works have been done to reduce the on-resistance ($R_{ON}$) and turn-on voltage ($V_{ON}$) of devices4, 5, 6. In this work, high quality n-GaN drift layer with low carbon impurity concentration grown by Hydride Vapor Phase Epitaxy (HVPE) was first demonstrated. Also, indium tin oxide (ITO) technology and O2 plasma treatment (OPT) were employed to achieve the $R_{ON}(1.24 mathrm{m}Omegacdot text{cm}^{2})$ and $V_{ON}$ (0.37 V) for the ∼1.2 kV Schottky barrier diode.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147434
Hang Liao, Zheyang Zheng, Tao Chen, Li Zhang, Yan Cheng, Long Chen, Li Yuan, K. J. Chen
We present an enhancement-mode (E-mode) $p$-GaN gate high-electron-mobility transistor (HEMT) featuring a double-channel (DC) structure. An AlN layer (1 nm) inserted at 6 nm below the conventional $p$-GaN/AlGaN/AlN/GaN heterojunction enables the simultaneous formation of a second lower two-dimensional electron gas (2DEG) channel and a barrier layer that can block and confine holes injected from the overlaying $p$-GaN gate at sufficiently large positive gate bias. The injected holes are confined in close vicinity between the upper and lower channels yet are spatially separated from electrons to prolong the minority (i.e., hole) lifetime, which is otherwise very short in the direct-bandgap GaN. Such vicinal hole storage (VHS) can induce more electrons in 2DEG channels, leading to clear enhancement of conductivity. The VHS and its impact on enhanced channel conductivity are also evidenced by simulation results.
{"title":"Conductivity Enhancement Induced by Confined Vicinal Hole Storage in Enhancement-mode $p$-GaN Gate Double-Channel HEMTs","authors":"Hang Liao, Zheyang Zheng, Tao Chen, Li Zhang, Yan Cheng, Long Chen, Li Yuan, K. J. Chen","doi":"10.1109/ISPSD57135.2023.10147434","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147434","url":null,"abstract":"We present an enhancement-mode (E-mode) $p$-GaN gate high-electron-mobility transistor (HEMT) featuring a double-channel (DC) structure. An AlN layer (1 nm) inserted at 6 nm below the conventional $p$-GaN/AlGaN/AlN/GaN heterojunction enables the simultaneous formation of a second lower two-dimensional electron gas (2DEG) channel and a barrier layer that can block and confine holes injected from the overlaying $p$-GaN gate at sufficiently large positive gate bias. The injected holes are confined in close vicinity between the upper and lower channels yet are spatially separated from electrons to prolong the minority (i.e., hole) lifetime, which is otherwise very short in the direct-bandgap GaN. Such vicinal hole storage (VHS) can induce more electrons in 2DEG channels, leading to clear enhancement of conductivity. The VHS and its impact on enhanced channel conductivity are also evidenced by simulation results.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127395003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a $beta$-Ga2O3 metal-heterojunction composite field effect transistor (ME-HJFET) has been proposed that combines the merits of both the Schottky gate, as well as the NiOX pn heterojunction gate. Meanwhile, a conventional heterojunction field effect transistor (CHJ-FET) has been fabricated. The study addresses the critical metrics of BV (breakdown voltage) and specific on-resistance ($R_{text{ON},text{SP}}$) and at the same time achieves a significant improvement of these parameters in comparison to the previously reported state-of-the-art designs. A high breakdown voltage (BV) of around 2160 V and an RON, SP of $6.35 mathrm{m}Omegacdottext{cm}^{2}$ for ME-HJFET and a BV of around 2340 V and an RON, SP of $21.9 mathrm{m}Omegacdottext{cm}^{2}$ for CHJ-FET were achieved. Also, a P-FOM of 0.73 GW/cm2 was achieved, which is near twice the value for a CHJ-FET (0.37 GW/cm2). This is also the highest value reported so far for any E-mode Ga2O3 FETs.
{"title":"An E-mode $beta$-Ga2O3 metal-heterojunction composite field effect transistor with a record high P-FOM of 0.73 GW/cm2","authors":"Xichen Wang, Xiaoli Lu, Yunlong He, Peng Liu, Yv Shao, Jianing Li, Yitong Yang, Yuan Li, Yue Hao, Xiao-hua Ma","doi":"10.1109/ISPSD57135.2023.10147570","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147570","url":null,"abstract":"In this work, a <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> metal-heterojunction composite field effect transistor (ME-HJFET) has been proposed that combines the merits of both the Schottky gate, as well as the NiO<inf>X</inf> pn heterojunction gate. Meanwhile, a conventional heterojunction field effect transistor (CHJ-FET) has been fabricated. The study addresses the critical metrics of BV (breakdown voltage) and specific on-resistance (<tex>$R_{text{ON},text{SP}}$</tex>) and at the same time achieves a significant improvement of these parameters in comparison to the previously reported state-of-the-art designs. A high breakdown voltage (BV) of around 2160 V and an R<inf>ON, SP</inf> of <tex>$6.35 mathrm{m}Omegacdottext{cm}^{2}$</tex> for ME-HJFET and a BV of around 2340 V and an RON, SP of <tex>$21.9 mathrm{m}Omegacdottext{cm}^{2}$</tex> for CHJ-FET were achieved. Also, a P-FOM of 0.73 GW/cm<sup>2</sup> was achieved, which is near twice the value for a CHJ-FET (0.37 GW/cm<sup>2</sup>). This is also the highest value reported so far for any E-mode Ga<inf>2</inf>O<inf>3</inf> FETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126268777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147517
Zijian Zhang, Xuehao Tang, Kai Chen, Suyang Liu, M. Inuishi
This work proposes the structures for n-channel and p-channel lateral IGBT on bulk silicon to achieve the complementary inverter leg. The double buried layer for n-channel and the triple buried layer for p-channel are introduced. These structures can eliminate the substrate current of bulk silicon completely, achieving perfect isolation. Also, with sufficient thickness of epitaxial layer to support the voltage drop, the forward blocking voltage can be ensured. Furthermore, the top buried layers of the n-channel and the p-channel IGBT are formed to extract minority carriers to achieve the fast turn-off time. Finally, it is verified that the emitter follower type complementary inverter leg can be operated without penetration current.
{"title":"Novel Complementary Lateral IGBTs on Bulk Silicon with Multiple Buried Layers for Perfect Isolation and High Performance","authors":"Zijian Zhang, Xuehao Tang, Kai Chen, Suyang Liu, M. Inuishi","doi":"10.1109/ISPSD57135.2023.10147517","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147517","url":null,"abstract":"This work proposes the structures for n-channel and p-channel lateral IGBT on bulk silicon to achieve the complementary inverter leg. The double buried layer for n-channel and the triple buried layer for p-channel are introduced. These structures can eliminate the substrate current of bulk silicon completely, achieving perfect isolation. Also, with sufficient thickness of epitaxial layer to support the voltage drop, the forward blocking voltage can be ensured. Furthermore, the top buried layers of the n-channel and the p-channel IGBT are formed to extract minority carriers to achieve the fast turn-off time. Finally, it is verified that the emitter follower type complementary inverter leg can be operated without penetration current.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147690
Yanlin Wu, Muqin Nuo, Junjie Yang, Zheyang Zheng, Li Zhang, K. J. Chen, M. Hua, Y. Hao, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei
The dynamic stability of E-mode active-passivation p-GaN gate HEMT (AP- HEMT) is investigated, including dynamic $V_{text{th}}$ shift, dynamic $R_{text{ON}}$ degradation, and dynamic leakage current. The AP-HEMT features an ohmic-type gate/p-GaN contact that results in a stable dynamic $V_{text{th}}$, as the charge storage effect associated with the floating p-GaN layer is avoided. At a 650- V $V_{text{DS}}$ stress, the AP- HEMT exhibits a low dynamic $R_{text{ON}}$/static $R_{text{ON}}$ ratio of 1.4, which can be attributed to the presence of the p-GaN active-passivation layer that screens the influence of surface traps. The hole injection in the p-GaN gate HEMT is expected to increase the dynamic OFF-state leakage current, as the holes reduce the energy barrier of the buffer layer. Despite a larger injector area, the AP-HEMT exhibits a lower dynamic leakage current increase, which is due to the relocation of the electric field peak from the gate edge towards the drain. This relocation suppresses the lowering of the energy barrier under the gate. Overall, the unique device structure of the AP-HEMT leads to a negligible dynamic $V_{text{th}}$ shift, a low dynamic $R_{text{ON}}$, and a small OFF-state dynamic leakage increase.
研究了e模主动钝化p-GaN栅极HEMT (AP- HEMT)的动态稳定性，包括动态V_{text{th}}$移位、动态R_{text{ON}}$退化和动态漏电流。AP-HEMT具有欧姆型栅极/p-GaN接触，由于避免了与浮动p-GaN层相关的电荷存储效应，因此可以产生稳定的动态$V_{text{th}}$。在650- V $V_{text{DS}}$应力下，AP- HEMT表现出较低的动态$R_{text{ON}}$/静态$R_{text{ON}}$比值，为1.4，这可归因于p-GaN主动钝化层的存在，该钝化层屏蔽了表面陷阱的影响。由于空穴降低了缓冲层的能量势垒，p-GaN栅极HEMT中的空穴注入有望增加动态off状态泄漏电流。尽管注入面积较大，AP-HEMT表现出较低的动态泄漏电流增长，这是由于电场峰值从栅极边缘向漏极移动所致。这种重新安置抑制了闸下能量势垒的降低。总的来说，AP-HEMT独特的器件结构导致动态$V_{text{th}}$移位可以忽略，动态$R_{text{ON}}$很小，关闭状态动态泄漏增加很小。
{"title":"High Dynamic Stability in Enhancement-Mode Active-Passivation p-GaN Gate HEMT","authors":"Yanlin Wu, Muqin Nuo, Junjie Yang, Zheyang Zheng, Li Zhang, K. J. Chen, M. Hua, Y. Hao, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei","doi":"10.1109/ISPSD57135.2023.10147690","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147690","url":null,"abstract":"The dynamic stability of E-mode active-passivation p-GaN gate HEMT (AP- HEMT) is investigated, including dynamic $V_{text{th}}$ shift, dynamic $R_{text{ON}}$ degradation, and dynamic leakage current. The AP-HEMT features an ohmic-type gate/p-GaN contact that results in a stable dynamic $V_{text{th}}$, as the charge storage effect associated with the floating p-GaN layer is avoided. At a 650- V $V_{text{DS}}$ stress, the AP- HEMT exhibits a low dynamic $R_{text{ON}}$/static $R_{text{ON}}$ ratio of 1.4, which can be attributed to the presence of the p-GaN active-passivation layer that screens the influence of surface traps. The hole injection in the p-GaN gate HEMT is expected to increase the dynamic OFF-state leakage current, as the holes reduce the energy barrier of the buffer layer. Despite a larger injector area, the AP-HEMT exhibits a lower dynamic leakage current increase, which is due to the relocation of the electric field peak from the gate edge towards the drain. This relocation suppresses the lowering of the energy barrier under the gate. Overall, the unique device structure of the AP-HEMT leads to a negligible dynamic $V_{text{th}}$ shift, a low dynamic $R_{text{ON}}$, and a small OFF-state dynamic leakage increase.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126664950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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