Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147711
J. Pjencak, Ladislav Seliga
In the recent decade, the modern Smart Power Applications drive BCD technologies to higher voltage nodes (>100V), lower cost and isolation improvement. Thick SOI technology is one of the options providing sufficient breakdown and desired power. Doping of device wafer is setup low to support necessary spread of depletion region. Typical HV diode is made by implanting a layer of opposite dopant type. Lateral distance between anode and cathode contacts is then defining diode area and become more significant for higher operating voltage. Our work demonstrates a new approach that enable significantly smaller size without additional cost.
{"title":"Compact 200V Diode Constructed on Thick SOI Wafer","authors":"J. Pjencak, Ladislav Seliga","doi":"10.1109/ISPSD57135.2023.10147711","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147711","url":null,"abstract":"In the recent decade, the modern Smart Power Applications drive BCD technologies to higher voltage nodes (>100V), lower cost and isolation improvement. Thick SOI technology is one of the options providing sufficient breakdown and desired power. Doping of device wafer is setup low to support necessary spread of depletion region. Typical HV diode is made by implanting a layer of opposite dopant type. Lateral distance between anode and cathode contacts is then defining diode area and become more significant for higher operating voltage. Our work demonstrates a new approach that enable significantly smaller size without additional cost.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147699
Yifei Huang, Q. Jiang, Sen Huang, Xinyu Liu
In this work, three testing modes, including continuous hard switching testing (HSW), high-voltage DC stress testing (DC) and recovery testing (RE), are implemented to characterize time-resolved dynamic $R_{text{ON}}$ behaviors of GaN HEMT devices, based on the inductive-load evaluation platform. The proposed stressing pattern (DC-HSW-DC-RE) enables the separation of de-stress- and transient-stress-induced dynamic $R_{text{ON}}$. Based on the stressing pattern, a novel physical-based characterization method is proposed to identify the irreversible degradation of dynamic $R_{text{ON}}$, featuring excellent sensitivity when compared with the traditional methods. In addition, lifetime acceleration experiments are carried out, and the irreversible $R_{text{ON}}$ degradation exhibits a strong dependence on voltage and current, but a weak dependence on temperature.
{"title":"A Systematic Characterization Method for Time-resolved Stability and Reliability Issues on Lateral GaN Power Devices","authors":"Yifei Huang, Q. Jiang, Sen Huang, Xinyu Liu","doi":"10.1109/ISPSD57135.2023.10147699","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147699","url":null,"abstract":"In this work, three testing modes, including continuous hard switching testing (HSW), high-voltage DC stress testing (DC) and recovery testing (RE), are implemented to characterize time-resolved dynamic $R_{text{ON}}$ behaviors of GaN HEMT devices, based on the inductive-load evaluation platform. The proposed stressing pattern (DC-HSW-DC-RE) enables the separation of de-stress- and transient-stress-induced dynamic $R_{text{ON}}$. Based on the stressing pattern, a novel physical-based characterization method is proposed to identify the irreversible degradation of dynamic $R_{text{ON}}$, featuring excellent sensitivity when compared with the traditional methods. In addition, lifetime acceleration experiments are carried out, and the irreversible $R_{text{ON}}$ degradation exhibits a strong dependence on voltage and current, but a weak dependence on temperature.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"754 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147707
Y. Yamashita, S. Machida, J. Saito, Masaru Senoo
Reverse conducting integrated gate bipolar transistor (RC-IGBT) features a monolithically integrated diode. In the case of diodes, a lifetime killer is generally introduced because of large switching losses caused by accumulated carriers during forward conduction. However, lifetime killer causes an increase in IGBT on-resistance. This study proposes Schottky and Multi-layered Anode (SMA) structures for low loss RC-IGBT to control diode performance while maintaining IGBT characteristics. Results show that the proposed structure reduces the reverse recovery charge by 41 % compared to a conventional structure. In contrast, in the IGBT characteristics, the threshold voltage, on-voltage, and turn-off characteristics remain practically unchanged.
{"title":"Novel Diode Structure for Ultra-Law-Loss RC-IGBTs","authors":"Y. Yamashita, S. Machida, J. Saito, Masaru Senoo","doi":"10.1109/ISPSD57135.2023.10147707","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147707","url":null,"abstract":"Reverse conducting integrated gate bipolar transistor (RC-IGBT) features a monolithically integrated diode. In the case of diodes, a lifetime killer is generally introduced because of large switching losses caused by accumulated carriers during forward conduction. However, lifetime killer causes an increase in IGBT on-resistance. This study proposes Schottky and Multi-layered Anode (SMA) structures for low loss RC-IGBT to control diode performance while maintaining IGBT characteristics. Results show that the proposed structure reduces the reverse recovery charge by 41 % compared to a conventional structure. In contrast, in the IGBT characteristics, the threshold voltage, on-voltage, and turn-off characteristics remain practically unchanged.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147660
Michel Nagel, Ivana Kovacevic-Badstuebner, Race Salvatore, D. Popescu, B. Popescu, D. Romano, Giulio Antonini, U. Grossner
This paper presents a novel modeling approach for assessing the stability of SiC power MOSFETs connected in parallel considering the voltage-dependent MOSFET C-V and I-V characteristics, as well as the frequency-dependent PCB layout parasitics. It is shown that the switching circuit is time-variant and hence, has to be analyzed both in the time-and frequency-domain to have a complete understanding of the (un)stable oscillations. Such a two-domain analysis can be beneficial for designing optimized circuits with parallel SiC power MOSFETs.
{"title":"Stability Analysis of Parallel SiC power MOSFETs based on a Virtual Prototype","authors":"Michel Nagel, Ivana Kovacevic-Badstuebner, Race Salvatore, D. Popescu, B. Popescu, D. Romano, Giulio Antonini, U. Grossner","doi":"10.1109/ISPSD57135.2023.10147660","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147660","url":null,"abstract":"This paper presents a novel modeling approach for assessing the stability of SiC power MOSFETs connected in parallel considering the voltage-dependent MOSFET C-V and I-V characteristics, as well as the frequency-dependent PCB layout parasitics. It is shown that the switching circuit is time-variant and hence, has to be analyzed both in the time-and frequency-domain to have a complete understanding of the (un)stable oscillations. Such a two-domain analysis can be beneficial for designing optimized circuits with parallel SiC power MOSFETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127978238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147608
Junsong Jiang, Mohan Tian, Wen Ji, Zhihao Hu, Haoran Li, Yuzheng Guo, Zhaofu Zhang, Xi Tang, Cungang Hu, Wenping Cao
The threshold voltage ($V_{text{TH}}$) instability of silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) are investigated by pulsed bias characterizations. The $V_{text{TH}}$ instability is observed at a time range from nanoseconds (ns) to seconds. The bias induced $V_{text{TH}}$ shift caused by is observed within 40 ns. It is also found that a negative gate bias induces a negative $V_{text{TH}}$ shift while a positive gate bias induces a positive $V_{text{TH}}$ shift. The carrier trapping and de-trapping processes into the gate oxide cause the $V_{text{TH}}$ instabilities and they are explained by the energy band diagrams. The TCAD simulations are performed to demonstrate the exsistence of the electric fields to sweep carriers into the trapping region under both positive and negative gate bias conditions. The capacitance-voltage characterizations and first-principles calculations are further carried out to evaluate the defect distribution and explore the intrinsic source of high-density interface traps near the SiC-SiO2 interface.
{"title":"Mechanism of Threshold Voltage Instability in SiC MOSFETs and Impacts on Dynamic Switching","authors":"Junsong Jiang, Mohan Tian, Wen Ji, Zhihao Hu, Haoran Li, Yuzheng Guo, Zhaofu Zhang, Xi Tang, Cungang Hu, Wenping Cao","doi":"10.1109/ISPSD57135.2023.10147608","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147608","url":null,"abstract":"The threshold voltage ($V_{text{TH}}$) instability of silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) are investigated by pulsed bias characterizations. The $V_{text{TH}}$ instability is observed at a time range from nanoseconds (ns) to seconds. The bias induced $V_{text{TH}}$ shift caused by is observed within 40 ns. It is also found that a negative gate bias induces a negative $V_{text{TH}}$ shift while a positive gate bias induces a positive $V_{text{TH}}$ shift. The carrier trapping and de-trapping processes into the gate oxide cause the $V_{text{TH}}$ instabilities and they are explained by the energy band diagrams. The TCAD simulations are performed to demonstrate the exsistence of the electric fields to sweep carriers into the trapping region under both positive and negative gate bias conditions. The capacitance-voltage characterizations and first-principles calculations are further carried out to evaluate the defect distribution and explore the intrinsic source of high-density interface traps near the SiC-SiO2 interface.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115928591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147414
Zuquan Zheng, M. Qiao, Wenliang Liu, Xingrui Long, Penglong Xu, Chunxia Ma, Feng Lin, Bo Zhang
This paper researches the hot carrier injection (HCI) degradation of 200V STI-based triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS). The degradation phenomenon of specific on-resistance ($R_{text{on},text{sp}}$) increasing, then decreasing and finally increasing at low gate voltage ($V_{text{gs}}$) was discovered in HCI test. First electron injection, then hole injection, and finally interface state generation, three mechanisms were put forward to account for this degradation phenomenon. With the assistance of TCAD tools, it can be concluded that the degradation of $R_{text{on},text{sp}}$ caused by both electron traps and hole traps is much greater at STI corner than elsewhere for the same amount. Furthermore, an improved model based on above three mechanisms is proposed. This model introduces a parameter $alpha(V_{text{gs}})$ to characterize the influence of impact ionization peak locations on degradation.
{"title":"Mechanism Analysis and Improved Model for HCI in 200V STI-based Triple RESURF LDMOS With n-p-n Layer","authors":"Zuquan Zheng, M. Qiao, Wenliang Liu, Xingrui Long, Penglong Xu, Chunxia Ma, Feng Lin, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147414","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147414","url":null,"abstract":"This paper researches the hot carrier injection (HCI) degradation of 200V STI-based triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS). The degradation phenomenon of specific on-resistance ($R_{text{on},text{sp}}$) increasing, then decreasing and finally increasing at low gate voltage ($V_{text{gs}}$) was discovered in HCI test. First electron injection, then hole injection, and finally interface state generation, three mechanisms were put forward to account for this degradation phenomenon. With the assistance of TCAD tools, it can be concluded that the degradation of $R_{text{on},text{sp}}$ caused by both electron traps and hole traps is much greater at STI corner than elsewhere for the same amount. Furthermore, an improved model based on above three mechanisms is proposed. This model introduces a parameter $alpha(V_{text{gs}})$ to characterize the influence of impact ionization peak locations on degradation.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper proposes a single-event burnout (SEB) hardened trench-gate DMOS with HfO2 gate dielectric and a decelerating electric field layer in the parasitic NPN. The proposed device presents remarkable potential to tolerate SEB. High-$k$ gate dielectric (HfO2) is adopted to obtain a higher channel doping concentration while maintaining the normal $V_{text{TH}}$, thereby suppressing the secondary breakdown of parasitic NPN. The decelerating electric field layer will reduce the $beta$ of parasitic NPN. For the hardened trench gate DMOS with breakdown voltage of 572V under irradiation linear energy transfer value of 1pC/µm (96MeV/mg/cm2), numerical results (without considering the self-heating effect) show that the SEB threshold voltage is 554V, while the conventional device's is 132V. The SEB threshold voltage is increased by 32%. When the LET value is smaller than 0.6pC/µm, the SEB threshold voltage is over 570V. The SEB threshold voltage of proposed device almost equals its original breakdown voltage. It is meaningful for SEB hardening design of power devices.
{"title":"A SEB Hardened Trench Gate DMOS with HfO2 Gate Dielectric and Decelerating Electric Field Layer in Parasitic NPN Base","authors":"Jian Fang, Yibo Lei, Zhou Fang, Lijuan Shi, Lingli Tang, Xihe Yang, Ling Yan, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147721","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147721","url":null,"abstract":"The paper proposes a single-event burnout (SEB) hardened trench-gate DMOS with HfO2 gate dielectric and a decelerating electric field layer in the parasitic NPN. The proposed device presents remarkable potential to tolerate SEB. High-$k$ gate dielectric (HfO2) is adopted to obtain a higher channel doping concentration while maintaining the normal $V_{text{TH}}$, thereby suppressing the secondary breakdown of parasitic NPN. The decelerating electric field layer will reduce the $beta$ of parasitic NPN. For the hardened trench gate DMOS with breakdown voltage of 572V under irradiation linear energy transfer value of 1pC/µm (96MeV/mg/cm2), numerical results (without considering the self-heating effect) show that the SEB threshold voltage is 554V, while the conventional device's is 132V. The SEB threshold voltage is increased by 32%. When the LET value is smaller than 0.6pC/µm, the SEB threshold voltage is over 570V. The SEB threshold voltage of proposed device almost equals its original breakdown voltage. It is meaningful for SEB hardening design of power devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126895453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147539
Dong-Hoon Park, Min-Woo Kim, Jun-Ki Min, Kwang-Young Ko, Sang-Gi Lee
In this paper, improvement of gate oxide breakdown and BVdss walk-in after HCI stress of 100V PLDMOS devices was studied. The poly field plate extension applied at 60V or lower in the previous study could improve gate oxide breakdown by HCI of 100V PLDMOS. However, BVdss walk-in occurred after on-stress due to a change in the electric field distribution by changing the poly field plate. Changes in electrical potential and impact ionization were confirmed through TCAD simulation and improvements in HCI and HTRB of 100V PLDMOS devices were achieved by changing the metal field plates and N-type sinker design, in addition to poly field plates. Based on these results, we propose a novel structure for 100V class PLDMOS.
{"title":"Improvement of HCI and HTRB Reliability on 100V pLDMOS for 48V Battery Applications","authors":"Dong-Hoon Park, Min-Woo Kim, Jun-Ki Min, Kwang-Young Ko, Sang-Gi Lee","doi":"10.1109/ISPSD57135.2023.10147539","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147539","url":null,"abstract":"In this paper, improvement of gate oxide breakdown and BVdss walk-in after HCI stress of 100V PLDMOS devices was studied. The poly field plate extension applied at 60V or lower in the previous study could improve gate oxide breakdown by HCI of 100V PLDMOS. However, BVdss walk-in occurred after on-stress due to a change in the electric field distribution by changing the poly field plate. Changes in electrical potential and impact ionization were confirmed through TCAD simulation and improvements in HCI and HTRB of 100V PLDMOS devices were achieved by changing the metal field plates and N-type sinker design, in addition to poly field plates. Based on these results, we propose a novel structure for 100V class PLDMOS.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147400
Zhengpeng Wang, H. Gong, Xinxin Yu, F. Ren, S. Gu, Youdou Zheng, Rong Zhang, Jiandong Ye
Industrial power devices are required to conduct at least several amperes current in the on-state while blocking at least hundreds of volts in the off-state. In this work, high-temperature operational $text{NiO}/beta-text{Ga}_{2}mathrm{O}_{3}$ vertical p-n heterojunction diodes (HJDs) with ampere-level forward current and kV -level reverse breakdown voltage $(V_{b})$ have been demonstrated. The temperature-dependent current-voltage characteristics reveal that trap-assisted tunneling (TAT) current dominates the forward conduction mechanism of HJDs, while the leakage current is dominated by variable range hopping (VRH) mechanism under the high reverse bias. The resultant large-area (1×1 mm2) HJD rectifiers exhibit a superior forward on-state current of 5 A, a nearly-unity ideality factor and a large $V_{b}$ of 1.17 kV operated at a high temperature up to 548 K. The low deterioration rate of forward on-state current (1.24 mA/K at 4 V) and $V_{b}$ (0.95 V/K) with temperature implies high reliability of HJD, evidencing the promising potential of Ga2O3-based power diodes in harsh-environment power systems.
{"title":"5 A/1.17 kV NiO/$beta$-Ga2O3 heterojunction power rectifier with high-temperature operation capability up to 548 K","authors":"Zhengpeng Wang, H. Gong, Xinxin Yu, F. Ren, S. Gu, Youdou Zheng, Rong Zhang, Jiandong Ye","doi":"10.1109/ISPSD57135.2023.10147400","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147400","url":null,"abstract":"Industrial power devices are required to conduct at least several amperes current in the on-state while blocking at least hundreds of volts in the off-state. In this work, high-temperature operational $text{NiO}/beta-text{Ga}_{2}mathrm{O}_{3}$ vertical p-n heterojunction diodes (HJDs) with ampere-level forward current and kV -level reverse breakdown voltage $(V_{b})$ have been demonstrated. The temperature-dependent current-voltage characteristics reveal that trap-assisted tunneling (TAT) current dominates the forward conduction mechanism of HJDs, while the leakage current is dominated by variable range hopping (VRH) mechanism under the high reverse bias. The resultant large-area (1×1 mm2) HJD rectifiers exhibit a superior forward on-state current of 5 A, a nearly-unity ideality factor and a large $V_{b}$ of 1.17 kV operated at a high temperature up to 548 K. The low deterioration rate of forward on-state current (1.24 mA/K at 4 V) and $V_{b}$ (0.95 V/K) with temperature implies high reliability of HJD, evidencing the promising potential of Ga2O3-based power diodes in harsh-environment power systems.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127179534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147701
Yuxi Wei, Jie Wei, Pengcheng Zhu, Kemeng Yang, Kaiwei Dai, Jie Li, Junnan Wang, Bo Zhang, X. Luo
A low loss lateral insulated gate bipolar transistor (LIGBT) features an anode PNP structure and an integrated freewheeling diode (iFWD), named as PD LIGBT, is proposed and investigated by simulation. For the anode PNP structure, its P+ Collector shorts to the potential extracting contact above the P-top layer of iFWD, and its emitter is the anode of the LIGBT. During turning off period with the increasing $V_{text{AK}}$, the PNP is activated and hole current is allowed to flow through the PNP to iFWD. It suppresses the hole injection of the anode into the N-drift region, and thus the current density decreases quickly. Therefore, the PD LIGBT achieves a fast turning-off speed and reduces the $E_{text{off}}$ significantly. In the on-state with low anode voltage $V_{text{AK}}$, the PNP is not activated, hence the PD LIGBT gets into bipolar conduction without snapback effect. Moreover, the iFWD can realize reverse conduction and obtain a low reverse recovery charge ($Q_{text{rr}}$). Compared with the SSA and STA LIGBTs, the proposed LIGBT reduces the $E_{text{off}}$ by 81% and 70% at the same on-state voltage drop ($V_{text{on}}$), respectively. The reverse recovery charge of the proposed device is reduced by 49.5% compared with that of SSA LIGBT.
{"title":"Low Loss Lateral Insulated Gate Bipolar Transistor with an Anode PNP Structure and Integrated Freewheeling Diode","authors":"Yuxi Wei, Jie Wei, Pengcheng Zhu, Kemeng Yang, Kaiwei Dai, Jie Li, Junnan Wang, Bo Zhang, X. Luo","doi":"10.1109/ISPSD57135.2023.10147701","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147701","url":null,"abstract":"A low loss lateral insulated gate bipolar transistor (LIGBT) features an anode PNP structure and an integrated freewheeling diode (iFWD), named as PD LIGBT, is proposed and investigated by simulation. For the anode PNP structure, its P+ Collector shorts to the potential extracting contact above the P-top layer of iFWD, and its emitter is the anode of the LIGBT. During turning off period with the increasing $V_{text{AK}}$, the PNP is activated and hole current is allowed to flow through the PNP to iFWD. It suppresses the hole injection of the anode into the N-drift region, and thus the current density decreases quickly. Therefore, the PD LIGBT achieves a fast turning-off speed and reduces the $E_{text{off}}$ significantly. In the on-state with low anode voltage $V_{text{AK}}$, the PNP is not activated, hence the PD LIGBT gets into bipolar conduction without snapback effect. Moreover, the iFWD can realize reverse conduction and obtain a low reverse recovery charge ($Q_{text{rr}}$). Compared with the SSA and STA LIGBTs, the proposed LIGBT reduces the $E_{text{off}}$ by 81% and 70% at the same on-state voltage drop ($V_{text{on}}$), respectively. The reverse recovery charge of the proposed device is reduced by 49.5% compared with that of SSA LIGBT.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：