Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147550
Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi
We propose a 200 V-class dual-field-plate (DFP) trench MOSFET (DFP MOSFET), which has multiple field-plate of different length inside the deep trench. This structure can be formed by simple DFP process. To clarify optimum design of DFP structure and reveal its potential, we verify the significant device parameters by TCAD simulation. We obtained a specific on-resistance of $147.7 mathrm{m}Omegacdot text{mm}^{2}$ at a breakdown voltage of 237 V, which is the best result in comparable voltage rating MOSFETs.
{"title":"High Performance Dual Field Plate Trench MOSFETs for Middle-voltage Applications","authors":"Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi","doi":"10.1109/ISPSD57135.2023.10147550","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147550","url":null,"abstract":"We propose a 200 V-class dual-field-plate (DFP) trench MOSFET (DFP MOSFET), which has multiple field-plate of different length inside the deep trench. This structure can be formed by simple DFP process. To clarify optimum design of DFP structure and reveal its potential, we verify the significant device parameters by TCAD simulation. We obtained a specific on-resistance of $147.7 mathrm{m}Omegacdot text{mm}^{2}$ at a breakdown voltage of 237 V, which is the best result in comparable voltage rating MOSFETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147411
W. Saito, S. Nishizawa
Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.
{"title":"Failure Process of GaN-HEMTs by Repetitive Overvoltage Stress","authors":"W. Saito, S. Nishizawa","doi":"10.1109/ISPSD57135.2023.10147411","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147411","url":null,"abstract":"Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One major roadblock toward the maturation of Ga2O3 technology is device overheating. For Ga2O3 trench devices, although with the higher thermal conductivity (kT[010]) of [100] trench sidewall compared to [010] trench sidewall, the Ga2O3 trench devices with [100] trench are rarely adopted, due to the worst sidewall interface quality induced by sidewall-orientation-dependent etch damage, even after the wet etch repair using acids. For the first time, the proposed electro-thermal co-designed Ga2O3 [100] trench diode based on optimized trench sidewall interface quality, featuring ferroelectric dielectric, exhibits better performance compared with Ga2O3 [010] trench diode. Under the identical power consumption, the Ga2O3 [100] trench diode shows the lowest center junction temperature, which is 9 degree lower than that of Ga2O3 [010] trench diode. The new interface-quality optimization strategy can significantly provide potential for electro-thermal optimization of Ga2O3 trench devices.
{"title":"An Electro-Thermal Co-Designed Ga2O3[100] Trench Power Diode Featuring Ferroelectric Dielectric","authors":"Yuan Li, Yitong Yang, Xiaoli Lu, Yunlong He, Xiao-hua Ma, Yue Hao","doi":"10.1109/ISPSD57135.2023.10147506","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147506","url":null,"abstract":"One major roadblock toward the maturation of Ga<inf>2</inf>O<inf>3</inf> technology is device overheating. For Ga<inf>2</inf>O<inf>3</inf> trench devices, although with the higher thermal conductivity (k<inf>T[010]</inf>) of [100] trench sidewall compared to [010] trench sidewall, the Ga<inf>2</inf>O<inf>3</inf> trench devices with [100] trench are rarely adopted, due to the worst sidewall interface quality induced by sidewall-orientation-dependent etch damage, even after the wet etch repair using acids. For the first time, the proposed electro-thermal co-designed Ga<inf>2</inf>O<inf>3</inf> [100] trench diode based on optimized trench sidewall interface quality, featuring ferroelectric dielectric, exhibits better performance compared with Ga<inf>2</inf>O<inf>3</inf> [010] trench diode. Under the identical power consumption, the Ga<inf>2</inf>O<inf>3</inf> [100] trench diode shows the lowest center junction temperature, which is 9 degree lower than that of Ga<inf>2</inf>O<inf>3</inf> [010] trench diode. The new interface-quality optimization strategy can significantly provide potential for electro-thermal optimization of Ga<inf>2</inf>O<inf>3</inf> trench devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147740
Li Lu, Shulang Ma, Jinyu Xiao, Feng Lin, Shuxian Chen, Hong Shao, Sen Zhang, Kui Xiao, Yixin Dai, Zhihan Zhu, Jia Ma, Jiaxing Wei, Long Zhang, Siyang Liu, Weifeng Sun
In this work, a new 200V 0.18µm SOI-BCD platform has been developed comprehensively including the wide-SOA n&pLDMOS, low-Ron nLDMOS and LIGBT. It is noted that a ultra-thin N-drift has been skillfully applied below the shallow-trench-isolation (STI) structure for the low-Ron nLDMOS to realize an ultra-low specific on-state resistance (Ron, sp) with 20% decrease than the best reported study and the off-state breakdown voltage (BVoff) is also unsacrificed. Moreover, a linear buffer near the drain side has been arranged in the wide-SOA n&pLDMOS for high on-state breakdown voltage (BVon). Finally, the reliability concerns have been also investigated fully including the negative bias temperature instability (NBTI) for the wide-SOA pLDMOS and hot carrier injection (HCI) for nLDMOS.
{"title":"0.18µm 200V SOI-BCD Technology with Ultra-Low Specific On-Resistance LDMOS for Automotive Application","authors":"Li Lu, Shulang Ma, Jinyu Xiao, Feng Lin, Shuxian Chen, Hong Shao, Sen Zhang, Kui Xiao, Yixin Dai, Zhihan Zhu, Jia Ma, Jiaxing Wei, Long Zhang, Siyang Liu, Weifeng Sun","doi":"10.1109/ISPSD57135.2023.10147740","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147740","url":null,"abstract":"In this work, a new 200V 0.18µm SOI-BCD platform has been developed comprehensively including the wide-SOA n&pLDMOS, low-Ron nLDMOS and LIGBT. It is noted that a ultra-thin N-drift has been skillfully applied below the shallow-trench-isolation (STI) structure for the low-Ron nLDMOS to realize an ultra-low specific on-state resistance (Ron, sp) with 20% decrease than the best reported study and the off-state breakdown voltage (BVoff) is also unsacrificed. Moreover, a linear buffer near the drain side has been arranged in the wide-SOA n&pLDMOS for high on-state breakdown voltage (BVon). Finally, the reliability concerns have been also investigated fully including the negative bias temperature instability (NBTI) for the wide-SOA pLDMOS and hot carrier injection (HCI) for nLDMOS.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147501
Zhao Wang, Xin Zhou, Zhanghua Wu, Chen Chen, Qi Zhou, M. Qiao, Zhaoji Li, Bo Zhang
TID radiation induced damage in metal/p-GaN/AlGaN/GaN gate stack of p-GaN gate HEMTs is studied and the damage mechanisms highly correlated with electric field are revealed. For on-state bias, irradiation damages related to donor-like traps are located at the reverse-biased metal/p-GaN Schottky junction with high electric field. The depletion region in the Schottky junction would extend, and the trap-assisted tunneling mechanism could be introduced to increase the forward gate current. For off-state bias, irradiation damages are located at the reverse-biased p-GaN/AlGaN/GaN (p-i-n) junction in relation to holes trapped in the AlGaN barrier and the GaN channel. The energy barrier of the AlGaN barrier and the GaN channel would be lowered for electron injection, leading to reverse gate current and off-state drain leakage current increasing. Irradiation induced damage at the Schottky junction may be permanent, while the p-i-n junction damage is recoverable with time.
{"title":"Total-Ionizing-Dose Radiation Induced Gate Damage in High Voltage P-GaN Gate HEMTs","authors":"Zhao Wang, Xin Zhou, Zhanghua Wu, Chen Chen, Qi Zhou, M. Qiao, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147501","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147501","url":null,"abstract":"TID radiation induced damage in metal/p-GaN/AlGaN/GaN gate stack of p-GaN gate HEMTs is studied and the damage mechanisms highly correlated with electric field are revealed. For on-state bias, irradiation damages related to donor-like traps are located at the reverse-biased metal/p-GaN Schottky junction with high electric field. The depletion region in the Schottky junction would extend, and the trap-assisted tunneling mechanism could be introduced to increase the forward gate current. For off-state bias, irradiation damages are located at the reverse-biased p-GaN/AlGaN/GaN (p-i-n) junction in relation to holes trapped in the AlGaN barrier and the GaN channel. The energy barrier of the AlGaN barrier and the GaN channel would be lowered for electron injection, leading to reverse gate current and off-state drain leakage current increasing. Irradiation induced damage at the Schottky junction may be permanent, while the p-i-n junction damage is recoverable with time.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147533
F. Hoffmann, S. Schmitt, N. Kaminski
The goal of this work is to assess the power cycling performance of silicon carbide MOSFETs at low temperature swings and investigate the previously reported discrepancy between common lifetime model and power cycling test results. Additionally, the impact of the minimum temperature on the power cycling performance was examined. For this purpose, power cycling tests with temperature swings between 40 K to 100 K and at minimum temperatures of 20°C and 40°C are performed. The results confirm, that the lifetime of SiC MOSFETs is significantly underestimated at low temperature swings by state-of-the-art lifetime models, when the model is fitted to power cycling test results at high temperature swings, which is in agreement with previous reports. Furthermore, the test results suggest that the discrepancy increases even further towards lower temperature swings, which can be modeled by a change of the Coffin-Manson exponent at a threshold temperature swing. This could be a possible indication of the transition from plastic to elastic deformation as the prevalent fatigue mechanism. Moreover, the tests at different minimum temperatures show a significantly higher impact of the baseline temperature on the lifetime at low temperature swings compared to high temperature swings. This may indicate that the threshold temperature swing for the transition from plastic to elastic deformation is impacted by the minimum temperature.
{"title":"Lifetime Modeling of SiC MOSFET Power Modules During Power Cycling Tests at Low Temperature Swings","authors":"F. Hoffmann, S. Schmitt, N. Kaminski","doi":"10.1109/ISPSD57135.2023.10147533","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147533","url":null,"abstract":"The goal of this work is to assess the power cycling performance of silicon carbide MOSFETs at low temperature swings and investigate the previously reported discrepancy between common lifetime model and power cycling test results. Additionally, the impact of the minimum temperature on the power cycling performance was examined. For this purpose, power cycling tests with temperature swings between 40 K to 100 K and at minimum temperatures of 20°C and 40°C are performed. The results confirm, that the lifetime of SiC MOSFETs is significantly underestimated at low temperature swings by state-of-the-art lifetime models, when the model is fitted to power cycling test results at high temperature swings, which is in agreement with previous reports. Furthermore, the test results suggest that the discrepancy increases even further towards lower temperature swings, which can be modeled by a change of the Coffin-Manson exponent at a threshold temperature swing. This could be a possible indication of the transition from plastic to elastic deformation as the prevalent fatigue mechanism. Moreover, the tests at different minimum temperatures show a significantly higher impact of the baseline temperature on the lifetime at low temperature swings compared to high temperature swings. This may indicate that the threshold temperature swing for the transition from plastic to elastic deformation is impacted by the minimum temperature.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147700
Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato
In this study, the first 3D direct integration of a SiC power MOSFET and its SiC CMOS gate driver is achieved using flip chip bonding, enabling a wire bondless connection. Switching operation of the resulting “SiC 3D power IC” is achieved experimentally at 600 V and 20 A for the first time at speeds of 102 and 67.0 V/ns for turn-on and turn-off operations, respectively. Further experiments demonstrated that the switching speed of the first version of the SiC 3D power IC is improved by over 14% compared to previous devices using wire bonding (wire bonding devices). Numerical predictions indicate that the SiC 3D power IC has the potential to more than double the switching speed of wire bonding devices and realizes switching speeds of 300 V/ns or more if the gate resistance is decreased.
{"title":"A SiC 3D Power IC Directly Integrating a Power MOSFET With Its CMOS Gate Driver Using Flip Chip Bonding","authors":"Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato","doi":"10.1109/ISPSD57135.2023.10147700","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147700","url":null,"abstract":"In this study, the first 3D direct integration of a SiC power MOSFET and its SiC CMOS gate driver is achieved using flip chip bonding, enabling a wire bondless connection. Switching operation of the resulting “SiC 3D power IC” is achieved experimentally at 600 V and 20 A for the first time at speeds of 102 and 67.0 V/ns for turn-on and turn-off operations, respectively. Further experiments demonstrated that the switching speed of the first version of the SiC 3D power IC is improved by over 14% compared to previous devices using wire bonding (wire bonding devices). Numerical predictions indicate that the SiC 3D power IC has the potential to more than double the switching speed of wire bonding devices and realizes switching speeds of 300 V/ns or more if the gate resistance is decreased.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"116 35","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131912992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147399
Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang
In this work, we propose a 700V super-junction vertical double-diffused MOSFET (SJ VDMOS) with P-type lateral connection (LC) layer in the termination region. By changing the doping concentration of the LC layer, we can effectively adjust the reverse recovery characteristics. More internal holes remain near the depletion boundary for the termination structure with lower P-type LC layer doping concentration during the recovery period, leading to slower recovery current drop. However, the doping concentration of P-type LC layer does not affect the reverse period. Using this optimization method, we conduct experiments based on a multi-epitaxy/multi-implant platform. The experimental device realizes specific on-resistance of 12.09 m Ω.cm2 and breakdown voltage of 719 V. The experimental results are in good consistence with the simulated results. Both simulated and experimental results validate the effectiveness and feasibility of the proposed method.
在这项工作中，我们提出了一个在终端区具有p型横向连接(LC)层的700V超结垂直双扩散MOSFET (SJ VDMOS)。通过改变LC层的掺杂浓度，可以有效地调节反向回收特性。p型LC层掺杂浓度越低，在恢复期间终止结构的耗尽边界附近保留更多的内部空穴，导致恢复电流下降越慢。而p型LC层的掺杂浓度对反向周期没有影响。利用这种优化方法，我们在多外延/多植入平台上进行了实验。实验装置实现比导通电阻12.09 m Ω。cm2，击穿电压719v。实验结果与仿真结果吻合较好。仿真和实验结果验证了该方法的有效性和可行性。
{"title":"Optimization of Reverse Recovery Characteristics Based on Termination Structure for 700V Super-Junction VDMOS","authors":"Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147399","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147399","url":null,"abstract":"In this work, we propose a 700V super-junction vertical double-diffused MOSFET (SJ VDMOS) with P-type lateral connection (LC) layer in the termination region. By changing the doping concentration of the LC layer, we can effectively adjust the reverse recovery characteristics. More internal holes remain near the depletion boundary for the termination structure with lower P-type LC layer doping concentration during the recovery period, leading to slower recovery current drop. However, the doping concentration of P-type LC layer does not affect the reverse period. Using this optimization method, we conduct experiments based on a multi-epitaxy/multi-implant platform. The experimental device realizes specific on-resistance of 12.09 m Ω.cm2 and breakdown voltage of 719 V. The experimental results are in good consistence with the simulated results. Both simulated and experimental results validate the effectiveness and feasibility of the proposed method.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147403
Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang
Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current $(I_{text{PP}})$ of 5 A under the line-line capacitance $(C_{mathrm{L}-mathrm{L}})$ of 0.25 pF, 5 V power clamp gets the $I_{text{PP}}$ of 10 A with the dynamic resistance $(R_{text{dyn}})$ of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes $I_{text{PP}}$ of 320 A by increasing finger amount without non-uniformity triggering.
{"title":"Novel Multifunctional Transient Voltage Suppressor Technology for Modular EOS/ESD Protection Circuit Designs","authors":"Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147403","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147403","url":null,"abstract":"Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current $(I_{text{PP}})$ of 5 A under the line-line capacitance $(C_{mathrm{L}-mathrm{L}})$ of 0.25 pF, 5 V power clamp gets the $I_{text{PP}}$ of 10 A with the dynamic resistance $(R_{text{dyn}})$ of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes $I_{text{PP}}$ of 320 A by increasing finger amount without non-uniformity triggering.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147719
Xing Liu, Xupeng Li, C. Herrmann, T. Basler
The impact of the dead-time on the body diode reverse recovery behavior for 1.2 kV silicon carbide MOSFETs has been studied in this paper. The plasma formation behavior of the body diode at different temperatures and load currents is investigated firstly. The time for the plasma stabilization can be estimated. Afterwards, the influence of the load current amplitude, the operating temperature, and the switching speed have been investigated with standard double-pulse tests. Different MOSFET cell designs of various manufacturers were compared. It has been found that selecting a suitable dead-time and switching speed is essential for the optimization of the overall losses, especially at higher operation temperatures.
{"title":"The Impact of the Dead-Time on the Reverse Recovery Behavior of SiC-MOSFET Body Diodes","authors":"Xing Liu, Xupeng Li, C. Herrmann, T. Basler","doi":"10.1109/ISPSD57135.2023.10147719","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147719","url":null,"abstract":"The impact of the dead-time on the body diode reverse recovery behavior for 1.2 kV silicon carbide MOSFETs has been studied in this paper. The plasma formation behavior of the body diode at different temperatures and load currents is investigated firstly. The time for the plasma stabilization can be estimated. Afterwards, the influence of the load current amplitude, the operating temperature, and the switching speed have been investigated with standard double-pulse tests. Different MOSFET cell designs of various manufacturers were compared. It has been found that selecting a suitable dead-time and switching speed is essential for the optimization of the overall losses, especially at higher operation temperatures.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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