Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147630
R. Reiner, S. Moench, P. Waltereit, M. Basler, S. Müller, M. Mikulla, R. Quay
This work presents the design, fabrication, and measurements of a GaN-HEMT with a back-gated segment and pull-down pin in a GaN-on-Si technology. The device is designed for the use in high voltage cascodes. The static and dynamic characteristics of the device is demonstrated in a three-stage hybrid cascode assembly. The cascode was measured with a blocking voltage up to 1250 V.
{"title":"GaN-HEMT with a Back-Gated Segment for High Voltage Cascodes","authors":"R. Reiner, S. Moench, P. Waltereit, M. Basler, S. Müller, M. Mikulla, R. Quay","doi":"10.1109/ISPSD57135.2023.10147630","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147630","url":null,"abstract":"This work presents the design, fabrication, and measurements of a GaN-HEMT with a back-gated segment and pull-down pin in a GaN-on-Si technology. The device is designed for the use in high voltage cascodes. The static and dynamic characteristics of the device is demonstrated in a three-stage hybrid cascode assembly. The cascode was measured with a blocking voltage up to 1250 V.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147411
W. Saito, S. Nishizawa
Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.
{"title":"Failure Process of GaN-HEMTs by Repetitive Overvoltage Stress","authors":"W. Saito, S. Nishizawa","doi":"10.1109/ISPSD57135.2023.10147411","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147411","url":null,"abstract":"Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147405
T. Tamaki, Kohei Ebihara, Kazuya Konishi, Koki Kishimoto, S. Soneda, Tetsuo Takahashi, Tetsuya Nitta, Tatsuro Watahiki, Keunsam Lee
The impact of carrier injection into mold epoxy resin on the device leakage current of power modules is investigated by our proposed model of the resin and its application to a simplified power module. Charge redistribution or polarization of the resin alters the surface potential of the edge termination region, leading to electric failure during reliability tests such as High- Temperature Reverse Bias test. While attempts to simulate such behavior have been reported, the modeling of the epoxy resin and its interaction with the device termination and bonding wires are not fully understood. This paper shed light on this issue by presenting a physically reasonable assumption that can help resolve it.
{"title":"TCAD Simulation Modeling of Mold Epoxy Resin Applied for Encapsulation of Power Devices","authors":"T. Tamaki, Kohei Ebihara, Kazuya Konishi, Koki Kishimoto, S. Soneda, Tetsuo Takahashi, Tetsuya Nitta, Tatsuro Watahiki, Keunsam Lee","doi":"10.1109/ISPSD57135.2023.10147405","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147405","url":null,"abstract":"The impact of carrier injection into mold epoxy resin on the device leakage current of power modules is investigated by our proposed model of the resin and its application to a simplified power module. Charge redistribution or polarization of the resin alters the surface potential of the edge termination region, leading to electric failure during reliability tests such as High- Temperature Reverse Bias test. While attempts to simulate such behavior have been reported, the modeling of the epoxy resin and its interaction with the device termination and bonding wires are not fully understood. This paper shed light on this issue by presenting a physically reasonable assumption that can help resolve it.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"543-547 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128972318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147526
A. Edwards, V. Padilla, C. Drowley, S. Pidaparthi, J. Michael, Prashant Saxena, Joseph S. Tandingan, W. Meier, Andrew Walker
The fast-switching performance results of a 1200 V rated normally-off vertical GaN Fin-JFET are presented in this paper. A compact SPICE model which predicts its DC and dynamic behavior is presented and the anticipated switching performance is verified by measurement using a custom double pulse clamped inductive switching (CIS) circuit. As far as we know, this is the first report of a device switching 1400 V allowing for 10 MHz operation.
{"title":"Switching of a Bus Voltage of 1400 V at 10 MHz Using Vertical GaN Fin-JFETs","authors":"A. Edwards, V. Padilla, C. Drowley, S. Pidaparthi, J. Michael, Prashant Saxena, Joseph S. Tandingan, W. Meier, Andrew Walker","doi":"10.1109/ISPSD57135.2023.10147526","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147526","url":null,"abstract":"The fast-switching performance results of a 1200 V rated normally-off vertical GaN Fin-JFET are presented in this paper. A compact SPICE model which predicts its DC and dynamic behavior is presented and the anticipated switching performance is verified by measurement using a custom double pulse clamped inductive switching (CIS) circuit. As far as we know, this is the first report of a device switching 1400 V allowing for 10 MHz operation.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147646
Masahiro Tanaka, N. Abe, A. Nakagawa
In this paper, we propose shallow trench IGBT (ST -IGBT) and its fabrication process. It is designed for 15V of gate operation, as is the same as conventional IGBTs. The cell is consist of shallow trench gate MOS structure and shallow doping layers, formed by ion implantation and RTA (Rapid Thermal Anneal). The edge termination structure is composed by many shallow FLRs. The optimized cell design reduces V ce(sat) by 0.2V, compared with conventional IGBTs.
{"title":"A 15V operated Shallow Trench IGBT(ST-IGBT) fabricated by low temperature process and optimized for 12inch wafers","authors":"Masahiro Tanaka, N. Abe, A. Nakagawa","doi":"10.1109/ISPSD57135.2023.10147646","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147646","url":null,"abstract":"In this paper, we propose shallow trench IGBT (ST -IGBT) and its fabrication process. It is designed for 15V of gate operation, as is the same as conventional IGBTs. The cell is consist of shallow trench gate MOS structure and shallow doping layers, formed by ion implantation and RTA (Rapid Thermal Anneal). The edge termination structure is composed by many shallow FLRs. The optimized cell design reduces V ce(sat) by 0.2V, compared with conventional IGBTs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123380131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147550
Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi
We propose a 200 V-class dual-field-plate (DFP) trench MOSFET (DFP MOSFET), which has multiple field-plate of different length inside the deep trench. This structure can be formed by simple DFP process. To clarify optimum design of DFP structure and reveal its potential, we verify the significant device parameters by TCAD simulation. We obtained a specific on-resistance of $147.7 mathrm{m}Omegacdot text{mm}^{2}$ at a breakdown voltage of 237 V, which is the best result in comparable voltage rating MOSFETs.
{"title":"High Performance Dual Field Plate Trench MOSFETs for Middle-voltage Applications","authors":"Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi","doi":"10.1109/ISPSD57135.2023.10147550","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147550","url":null,"abstract":"We propose a 200 V-class dual-field-plate (DFP) trench MOSFET (DFP MOSFET), which has multiple field-plate of different length inside the deep trench. This structure can be formed by simple DFP process. To clarify optimum design of DFP structure and reveal its potential, we verify the significant device parameters by TCAD simulation. We obtained a specific on-resistance of $147.7 mathrm{m}Omegacdot text{mm}^{2}$ at a breakdown voltage of 237 V, which is the best result in comparable voltage rating MOSFETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147399
Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang
In this work, we propose a 700V super-junction vertical double-diffused MOSFET (SJ VDMOS) with P-type lateral connection (LC) layer in the termination region. By changing the doping concentration of the LC layer, we can effectively adjust the reverse recovery characteristics. More internal holes remain near the depletion boundary for the termination structure with lower P-type LC layer doping concentration during the recovery period, leading to slower recovery current drop. However, the doping concentration of P-type LC layer does not affect the reverse period. Using this optimization method, we conduct experiments based on a multi-epitaxy/multi-implant platform. The experimental device realizes specific on-resistance of 12.09 m Ω.cm2 and breakdown voltage of 719 V. The experimental results are in good consistence with the simulated results. Both simulated and experimental results validate the effectiveness and feasibility of the proposed method.
在这项工作中，我们提出了一个在终端区具有p型横向连接(LC)层的700V超结垂直双扩散MOSFET (SJ VDMOS)。通过改变LC层的掺杂浓度，可以有效地调节反向回收特性。p型LC层掺杂浓度越低，在恢复期间终止结构的耗尽边界附近保留更多的内部空穴，导致恢复电流下降越慢。而p型LC层的掺杂浓度对反向周期没有影响。利用这种优化方法，我们在多外延/多植入平台上进行了实验。实验装置实现比导通电阻12.09 m Ω。cm2，击穿电压719v。实验结果与仿真结果吻合较好。仿真和实验结果验证了该方法的有效性和可行性。
{"title":"Optimization of Reverse Recovery Characteristics Based on Termination Structure for 700V Super-Junction VDMOS","authors":"Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147399","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147399","url":null,"abstract":"In this work, we propose a 700V super-junction vertical double-diffused MOSFET (SJ VDMOS) with P-type lateral connection (LC) layer in the termination region. By changing the doping concentration of the LC layer, we can effectively adjust the reverse recovery characteristics. More internal holes remain near the depletion boundary for the termination structure with lower P-type LC layer doping concentration during the recovery period, leading to slower recovery current drop. However, the doping concentration of P-type LC layer does not affect the reverse period. Using this optimization method, we conduct experiments based on a multi-epitaxy/multi-implant platform. The experimental device realizes specific on-resistance of 12.09 m Ω.cm2 and breakdown voltage of 719 V. The experimental results are in good consistence with the simulated results. Both simulated and experimental results validate the effectiveness and feasibility of the proposed method.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147700
Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato
In this study, the first 3D direct integration of a SiC power MOSFET and its SiC CMOS gate driver is achieved using flip chip bonding, enabling a wire bondless connection. Switching operation of the resulting “SiC 3D power IC” is achieved experimentally at 600 V and 20 A for the first time at speeds of 102 and 67.0 V/ns for turn-on and turn-off operations, respectively. Further experiments demonstrated that the switching speed of the first version of the SiC 3D power IC is improved by over 14% compared to previous devices using wire bonding (wire bonding devices). Numerical predictions indicate that the SiC 3D power IC has the potential to more than double the switching speed of wire bonding devices and realizes switching speeds of 300 V/ns or more if the gate resistance is decreased.
{"title":"A SiC 3D Power IC Directly Integrating a Power MOSFET With Its CMOS Gate Driver Using Flip Chip Bonding","authors":"Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato","doi":"10.1109/ISPSD57135.2023.10147700","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147700","url":null,"abstract":"In this study, the first 3D direct integration of a SiC power MOSFET and its SiC CMOS gate driver is achieved using flip chip bonding, enabling a wire bondless connection. Switching operation of the resulting “SiC 3D power IC” is achieved experimentally at 600 V and 20 A for the first time at speeds of 102 and 67.0 V/ns for turn-on and turn-off operations, respectively. Further experiments demonstrated that the switching speed of the first version of the SiC 3D power IC is improved by over 14% compared to previous devices using wire bonding (wire bonding devices). Numerical predictions indicate that the SiC 3D power IC has the potential to more than double the switching speed of wire bonding devices and realizes switching speeds of 300 V/ns or more if the gate resistance is decreased.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"116 35","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131912992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147505
Dongyoung Kim, Skylar DeBoer, S. Jang, Adam J. Morgan, Woongje Sung
This paper presents the development and evaluation of a 1.2 kV 4H-SiC Split-Gate (SG) MOSFET with a deep P-well structure that effectively reduces the maximum electric field in the gate oxide (Eox), increases the short-circuit withstand time (SCWT), and reduces the switching energy loss. Channeling implantation was implemented to achieve a deep junction with low implantation energy in the proposed SG-MOSFET. The conventional MOSFET, conventional SG-MOSFET, and proposed SG-MOSFET were successfully fabricated and evaluated. The measured static, dynamic, and short-circuit characteristics were compared. In addition, 2D simulations were conducted to support the experimental results and extract the electric field in the gate oxide. The proposed SG-MOSFET outperforms the conventional SG-MOSFET with a 1.06× increase in BV and a 1.78× decrease in Eox. Additionally, the proposed SG-MOSFET shows a 1.52× improvement in SCWT compared to the conventional SG-MOSFET. Further, the proposed SG-MOSFET enhances [Ron × Crss] by 2.66× in comparison to the conventional SG-MOSFET, leading to the reduction of Eoff and Etotal by 1.5× and 1.05×, respectively.
{"title":"Improved Blocking and Switching Characteristics of Split-Gate 1.2kV 4H-SiC MOSFET with a Deep P-well","authors":"Dongyoung Kim, Skylar DeBoer, S. Jang, Adam J. Morgan, Woongje Sung","doi":"10.1109/ISPSD57135.2023.10147505","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147505","url":null,"abstract":"This paper presents the development and evaluation of a 1.2 kV 4H-SiC Split-Gate (SG) MOSFET with a deep P-well structure that effectively reduces the maximum electric field in the gate oxide (Eox), increases the short-circuit withstand time (SCWT), and reduces the switching energy loss. Channeling implantation was implemented to achieve a deep junction with low implantation energy in the proposed SG-MOSFET. The conventional MOSFET, conventional SG-MOSFET, and proposed SG-MOSFET were successfully fabricated and evaluated. The measured static, dynamic, and short-circuit characteristics were compared. In addition, 2D simulations were conducted to support the experimental results and extract the electric field in the gate oxide. The proposed SG-MOSFET outperforms the conventional SG-MOSFET with a 1.06× increase in BV and a 1.78× decrease in Eox. Additionally, the proposed SG-MOSFET shows a 1.52× improvement in SCWT compared to the conventional SG-MOSFET. Further, the proposed SG-MOSFET enhances [Ron × Crss] by 2.66× in comparison to the conventional SG-MOSFET, leading to the reduction of Eoff and Etotal by 1.5× and 1.05×, respectively.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"166 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120898579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147403
Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang
Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current $(I_{text{PP}})$ of 5 A under the line-line capacitance $(C_{mathrm{L}-mathrm{L}})$ of 0.25 pF, 5 V power clamp gets the $I_{text{PP}}$ of 10 A with the dynamic resistance $(R_{text{dyn}})$ of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes $I_{text{PP}}$ of 320 A by increasing finger amount without non-uniformity triggering.
{"title":"Novel Multifunctional Transient Voltage Suppressor Technology for Modular EOS/ESD Protection Circuit Designs","authors":"Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147403","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147403","url":null,"abstract":"Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current $(I_{text{PP}})$ of 5 A under the line-line capacitance $(C_{mathrm{L}-mathrm{L}})$ of 0.25 pF, 5 V power clamp gets the $I_{text{PP}}$ of 10 A with the dynamic resistance $(R_{text{dyn}})$ of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes $I_{text{PP}}$ of 320 A by increasing finger amount without non-uniformity triggering.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：