Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147694
Xuan Li, Qian Lou, Hanqing Zhao, Xiaochuan Deng, Bo Zhang
A novel self-clamped P-shield design in SiC trench-gate IGBT is proposed. An enhancement-mode (E-mode) PMOS and open-base PNP transistor are embedded at the emitter side by introducing an N-well into the P-shield region. In OFF -state, the P-shield is clamped at a low potential via the conduction of E-mode PMOS, maintaining a strong electric field shielding effect for trench gate oxide. In ON-state, the P-shield is floating electrically via the deep hole barrier formed by the N-well, enhancing the injection-enhancement (IE) effect. Under high collector-emitter voltage conditions, the P-shield is clamped via the punch-through of the open-base PNP transistor, effectively reducing saturation current. Furthermore, the self-clamped P-shield reduces the Miller capacitance and suppresses the negative gate capacitance during the switching transient, achieving low switching losses and high switching speed. As a result, the self-clamped P-shield SiC IGBT provides a new design solution to improving ON-, OFF -, and switching performance simultaneously.
提出了一种新的SiC沟槽栅IGBT自箝位p屏蔽设计方法。通过在p屏蔽区引入n阱，在发射极侧嵌入增强模式(e模式)PMOS和开基极PNP晶体管。在关断状态下，p -屏蔽层通过e模PMOS的导通被箝位在低电位，对沟槽栅氧化物保持强电场屏蔽作用。在on状态下，P-shield通过n井形成的深孔屏障带电漂浮，增强了注入增强(IE)效果。在高集电极-发射极电压条件下，p -屏蔽通过开基极PNP晶体管的穿孔箝位，有效降低饱和电流。此外，自箝位p屏蔽降低了米勒电容，抑制了开关瞬态时的负栅电容，实现了低开关损耗和高开关速度。因此，自箝位p屏蔽SiC IGBT提供了一种新的设计解决方案，可以同时提高ON-， OFF -和开关性能。
{"title":"Self-Clamped P-shield SiC Trench IGBT for Low On-State Voltage and Switching Loss","authors":"Xuan Li, Qian Lou, Hanqing Zhao, Xiaochuan Deng, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147694","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147694","url":null,"abstract":"A novel self-clamped P-shield design in SiC trench-gate IGBT is proposed. An enhancement-mode (E-mode) PMOS and open-base PNP transistor are embedded at the emitter side by introducing an N-well into the P-shield region. In OFF -state, the P-shield is clamped at a low potential via the conduction of E-mode PMOS, maintaining a strong electric field shielding effect for trench gate oxide. In ON-state, the P-shield is floating electrically via the deep hole barrier formed by the N-well, enhancing the injection-enhancement (IE) effect. Under high collector-emitter voltage conditions, the P-shield is clamped via the punch-through of the open-base PNP transistor, effectively reducing saturation current. Furthermore, the self-clamped P-shield reduces the Miller capacitance and suppresses the negative gate capacitance during the switching transient, achieving low switching losses and high switching speed. As a result, the self-clamped P-shield SiC IGBT provides a new design solution to improving ON-, OFF -, and switching performance simultaneously.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125637616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147625
Elizabeth Buitrago, M. Antoniou, Nick Schneider, E. Bianda, Luca De-Michielis, C. Corvasce, F. Udrea
The point injection trench IGBT is a promising concept based on the narrowing of the mesa between active gate trenches. In this paper, multiple design variations of the point injection trench IGBT with a voltage rating of 1200 V are fabricated and experimentally investigated. It is shown that sub micron mesa widths are successfully processed and a broad design space of IGBT devices with competitive performance is spanned.
{"title":"Experimental Demonstration of Point-Injection Trench IGBT Concept","authors":"Elizabeth Buitrago, M. Antoniou, Nick Schneider, E. Bianda, Luca De-Michielis, C. Corvasce, F. Udrea","doi":"10.1109/ISPSD57135.2023.10147625","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147625","url":null,"abstract":"The point injection trench IGBT is a promising concept based on the narrowing of the mesa between active gate trenches. In this paper, multiple design variations of the point injection trench IGBT with a voltage rating of 1200 V are fabricated and experimentally investigated. It is shown that sub micron mesa widths are successfully processed and a broad design space of IGBT devices with competitive performance is spanned.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147483
Y. Kobayashi, M. Fukui, T. Matsudai, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Ryohei Gejo, Tatsunori Sakano, T. Kato, T. Inokuchi, K. Takao, T. Hiramoto
Reducing turn-off loss ($E_{text{off}_text{total}}$) in insulated-gate bipolar transistors (IGBTs) improves the power consumption of high-power converter systems. Multi-gate IGBTs can reduce $E_{text{off}_text{total}}$ because stored carriers are reduced by adding independently controllable gates that switch just before the turn-off period. The proposed single-back and double-front gate-controlled IGBT (SDG-IGBT) successfully reduces $E_{text{off}_text{total}}$ when both the control gate (CG) on the emitter side and the back gate (BG) on the collector side are operated simultaneously. When the drift layer is thick in high-voltage IGBTs (e.g., the 3-kV-class), the control design of SDG-IGBTs is simple because the CG and BG carrier reduction regions do not interfere with each other. The optimum switching timings of CG and BG can be decided by evaluating $E_{text{off}_text{total}}$ in mode-2 (CG only operation) and mode-3 (BG only operation). SDG-IGBTs have the potential to greatly reduce $E_{text{off}_text{total}}$ while maximally utilizing the capabilities of both CG and BG because $E_{text{off}_text{total}}$ reduction rate is represented by the sum of the values for mode-2 and mode-3.
{"title":"Single-Back and Double-Front Gate-Controlled IGBT for Achieving Low Turn-Off Loss","authors":"Y. Kobayashi, M. Fukui, T. Matsudai, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Ryohei Gejo, Tatsunori Sakano, T. Kato, T. Inokuchi, K. Takao, T. Hiramoto","doi":"10.1109/ISPSD57135.2023.10147483","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147483","url":null,"abstract":"Reducing turn-off loss ($E_{text{off}_text{total}}$) in insulated-gate bipolar transistors (IGBTs) improves the power consumption of high-power converter systems. Multi-gate IGBTs can reduce $E_{text{off}_text{total}}$ because stored carriers are reduced by adding independently controllable gates that switch just before the turn-off period. The proposed single-back and double-front gate-controlled IGBT (SDG-IGBT) successfully reduces $E_{text{off}_text{total}}$ when both the control gate (CG) on the emitter side and the back gate (BG) on the collector side are operated simultaneously. When the drift layer is thick in high-voltage IGBTs (e.g., the 3-kV-class), the control design of SDG-IGBTs is simple because the CG and BG carrier reduction regions do not interfere with each other. The optimum switching timings of CG and BG can be decided by evaluating $E_{text{off}_text{total}}$ in mode-2 (CG only operation) and mode-3 (BG only operation). SDG-IGBTs have the potential to greatly reduce $E_{text{off}_text{total}}$ while maximally utilizing the capabilities of both CG and BG because $E_{text{off}_text{total}}$ reduction rate is represented by the sum of the values for mode-2 and mode-3.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114997235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147561
H. Shimizu, Takeru Suto, H. Miki, Y. Mori, D. Hisamoto, A. Shima, K. Kinoshita, T. Murata, T. Oda
We propose a new SiC trench MOSFET suitable for achieving both low loss and high reliability. This structure, called a VC Fin-SiC, is characterized by a fin-shaped trench, and by adopting a wide channel formed on the sidewall of the fin and a narrow JFET with high dopant concentration, it achieves both low on-resistance and high reliability. In this work, these design concepts are verified through simulation and actual device fabrication. Because the VC Fin-SiC has channels directly above the JFET structure, the performance can be easily improved by scaling the fin-pitch and channel length, and it will be one of the most promising structures in the future.
{"title":"Proposal of Vertical-channel Fin-SiC MOSFET toward Future Device Scaling","authors":"H. Shimizu, Takeru Suto, H. Miki, Y. Mori, D. Hisamoto, A. Shima, K. Kinoshita, T. Murata, T. Oda","doi":"10.1109/ISPSD57135.2023.10147561","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147561","url":null,"abstract":"We propose a new SiC trench MOSFET suitable for achieving both low loss and high reliability. This structure, called a VC Fin-SiC, is characterized by a fin-shaped trench, and by adopting a wide channel formed on the sidewall of the fin and a narrow JFET with high dopant concentration, it achieves both low on-resistance and high reliability. In this work, these design concepts are verified through simulation and actual device fabrication. Because the VC Fin-SiC has channels directly above the JFET structure, the performance can be easily improved by scaling the fin-pitch and channel length, and it will be one of the most promising structures in the future.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115428339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147621
R. Baburske, F. Pfirsch, Jana Hänsel, Katja Waschneck
For a trade-off between turn-off and on-state of power switches in medium and high power applications, it is crucial to consider the switching speed restrictions due to turn-off peak voltage. By varying the p-emitter efficiency and the front side plasma level of an IGBT, an $E_{text{off}}-V_{text{ce},text{sat}}$ trade-off curve for a fixed turn-off peak voltage can be obtained. It is shown that a turn-off behavior similar to that of a SiC MOSFET can be achieved with an IGBT with low carrier confinement, but with the drawback of a higher on-state voltage drop. At low current operations, the losses dissipated by the SiC MOSET are lower, not only in the on-state, but also during turn-off. The charge carrier plasma in the IGBT reduces both $mathrm{d}v/mathrm{d}t$ and $mathrm{d}i/mathrm{d}t$ for lower current densities. Switching curves at the rim of the RBSOA and beyond show that there is no dynamic avalanche in the SiC MOSFET. However, a quasi-static clamping mode can be observed for both types of devices.
{"title":"Si IGBT and SiC MOSFET – Potentials and Limitations of Plasma Shaping versus Unipolar Switching in Medium Power Applications","authors":"R. Baburske, F. Pfirsch, Jana Hänsel, Katja Waschneck","doi":"10.1109/ISPSD57135.2023.10147621","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147621","url":null,"abstract":"For a trade-off between turn-off and on-state of power switches in medium and high power applications, it is crucial to consider the switching speed restrictions due to turn-off peak voltage. By varying the p-emitter efficiency and the front side plasma level of an IGBT, an $E_{text{off}}-V_{text{ce},text{sat}}$ trade-off curve for a fixed turn-off peak voltage can be obtained. It is shown that a turn-off behavior similar to that of a SiC MOSFET can be achieved with an IGBT with low carrier confinement, but with the drawback of a higher on-state voltage drop. At low current operations, the losses dissipated by the SiC MOSET are lower, not only in the on-state, but also during turn-off. The charge carrier plasma in the IGBT reduces both $mathrm{d}v/mathrm{d}t$ and $mathrm{d}i/mathrm{d}t$ for lower current densities. Switching curves at the rim of the RBSOA and beyond show that there is no dynamic avalanche in the SiC MOSFET. However, a quasi-static clamping mode can be observed for both types of devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128649258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147632
Ji Shu, Jiahui Sun, Zheyang Zheng, K. J. Chen
The pn-junction body diode of Si super-junction MOSFET (SJ-MOSFET), when turned ON for reverse conduction, will result in a reverse-recovery process that exacerbates the switching loss. In this work, a cascode GaN/Si-SJ structure based on a high-voltage Si SJ-MOSFET and a low-voltage GaN HEMT is first proposed to suppress SJ-MOSFET's reverse-recovery process. Experiment results verified that the reverse-recovery charge ($Q_{text{rr}}$) of a Si SJ-MOSFET can be suppressed by 98% with the cascode structure, reducing the overall switching loss by 50% at high current levels.
{"title":"Suppressing the Reverse Recovery of Si Super-Junction MOSFET with a Low-Voltage GaN HEMT in a Cascode Configuration","authors":"Ji Shu, Jiahui Sun, Zheyang Zheng, K. J. Chen","doi":"10.1109/ISPSD57135.2023.10147632","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147632","url":null,"abstract":"The pn-junction body diode of Si super-junction MOSFET (SJ-MOSFET), when turned ON for reverse conduction, will result in a reverse-recovery process that exacerbates the switching loss. In this work, a cascode GaN/Si-SJ structure based on a high-voltage Si SJ-MOSFET and a low-voltage GaN HEMT is first proposed to suppress SJ-MOSFET's reverse-recovery process. Experiment results verified that the reverse-recovery charge ($Q_{text{rr}}$) of a Si SJ-MOSFET can be suppressed by 98% with the cascode structure, reducing the overall switching loss by 50% at high current levels.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"3574 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127522102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147560
Yifei Zheng, Qing Yuan, Deyuan Song, Yutao Ying, Jing Zhu, Weifeng Sun, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou, Sen Zhang, Nailong He
Monolithic integration has been demonstrated to be an ideal solution to minimize the parasitics in GaN power IC. Nonetheless, the current commercially GaN process for power IC is far less mature and only n-type HEMTs are available. Therefore, it is difficult for high voltage level shifters to achieve high speed. This work implements a level shifter for GaN IC to achieve both small response time and high $mathrm{d}V_{mathrm{S}}/text{dt}$ noise immunity without complicated signal processing circuits, thus delay and conduction loss will be minimized. The proposed circuit was fabricated in a $1mumathrm{m}$ GaN-on-Silicon process and measured results were performed to verify the characteristics.
{"title":"A High-Speed Level Shifter with dVs/dt Noise Immunity Enhancement Structure for 200V Monolithic GaN Power IC","authors":"Yifei Zheng, Qing Yuan, Deyuan Song, Yutao Ying, Jing Zhu, Weifeng Sun, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou, Sen Zhang, Nailong He","doi":"10.1109/ISPSD57135.2023.10147560","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147560","url":null,"abstract":"Monolithic integration has been demonstrated to be an ideal solution to minimize the parasitics in GaN power IC. Nonetheless, the current commercially GaN process for power IC is far less mature and only n-type HEMTs are available. Therefore, it is difficult for high voltage level shifters to achieve high speed. This work implements a level shifter for GaN IC to achieve both small response time and high $mathrm{d}V_{mathrm{S}}/text{dt}$ noise immunity without complicated signal processing circuits, thus delay and conduction loss will be minimized. The proposed circuit was fabricated in a $1mumathrm{m}$ GaN-on-Silicon process and measured results were performed to verify the characteristics.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117165635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147615
Yonghwa Lee, A. Castellazzi, S. Avilès, C. Duchesne, P. Lasserre
This paper presents the design and proof of concept validation of an integrated SiC MOSFET bidirectional switch, aiming to deliver high electro-thermal and electro-magnetic performance, while remaining commercially viable for large-volume applications. The focus is on enabling a high degree of system-level modularity by an integration effort targeted specifically at a single Bi-Directional Switch. Unlike conventional power modules, this work employs Insulated Metal Substrate technology, using copper and aluminum for interconnection without specific die finishes and without the need for ceramic substrates. The design is validated using specialist computer-aided design methodologies and tools for both electro-magnetic and electro-thermal performance. A prototype is manufactured, characterized and tested.
{"title":"SiC MOSFET bi-directional switch IMS module design","authors":"Yonghwa Lee, A. Castellazzi, S. Avilès, C. Duchesne, P. Lasserre","doi":"10.1109/ISPSD57135.2023.10147615","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147615","url":null,"abstract":"This paper presents the design and proof of concept validation of an integrated SiC MOSFET bidirectional switch, aiming to deliver high electro-thermal and electro-magnetic performance, while remaining commercially viable for large-volume applications. The focus is on enabling a high degree of system-level modularity by an integration effort targeted specifically at a single Bi-Directional Switch. Unlike conventional power modules, this work employs Insulated Metal Substrate technology, using copper and aluminum for interconnection without specific die finishes and without the need for ceramic substrates. The design is validated using specialist computer-aided design methodologies and tools for both electro-magnetic and electro-thermal performance. A prototype is manufactured, characterized and tested.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122034736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147598
A. P. Catalano, C. Scognamillo, V. d’Alessandro, L. Codecasa
This paper validates an innovative thermal impedance (ZTH) extraction technique against a state-of-the-art GaN-based power HEMT embedded in a PCB-based power circuit. Differently from traditional approaches based on direct or indirect temperature measurements, the technique provides the junction-to-ambient ZTHj-a - that is, the in-situ ZTH without any need for (i) thermocouples/infrared cameras or (ii) specific equipment like thermochuck and cold-plates. The accuracy of the technique is assessed by adopting the 'simulated experiments' strategy: the technique is applied to calibrated electrothermal simulations emulating the experiments, and the extracted junction-to-ambient ZTH is successfully compared to a reference one preliminarily determined with numerical simulations.
{"title":"In-Situ Extraction of the Thermal Impedance of GaN Power HEMTs Embedded in PCB-based Power Circuits","authors":"A. P. Catalano, C. Scognamillo, V. d’Alessandro, L. Codecasa","doi":"10.1109/ISPSD57135.2023.10147598","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147598","url":null,"abstract":"This paper validates an innovative thermal impedance (ZTH) extraction technique against a state-of-the-art GaN-based power HEMT embedded in a PCB-based power circuit. Differently from traditional approaches based on direct or indirect temperature measurements, the technique provides the junction-to-ambient ZTHj-a - that is, the in-situ ZTH without any need for (i) thermocouples/infrared cameras or (ii) specific equipment like thermochuck and cold-plates. The accuracy of the technique is assessed by adopting the 'simulated experiments' strategy: the technique is applied to calibrated electrothermal simulations emulating the experiments, and the extracted junction-to-ambient ZTH is successfully compared to a reference one preliminarily determined with numerical simulations.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a new high voltage MOS (HVMOS) structure and its gate control circuit for integrating a bootstrap diode (BSD) function into a 600V high voltage IC (HVIC). The new HVMOS structure is free from a parasitic PNP, and its drain drift resistance is lowered without sacrificing breakdown voltage. The new gate control circuit maintain the gate voltage of HVMOS high regardless of the frequency. The new 600V HVIC realizes a sufficient charging capacity even at a low frequency operation and a high tolerance of a VS negative surge.
{"title":"A 600V HVIC with integrated bootstrap diode function by a new emulating HVMOS","authors":"Yuji Kawasaki, Toshihiro Imasaka, Yuto Shibuta, Shohei Sano, Yoshio Habu, Nobuo Hashimoto, Mitsutaka Hano, M. Yoshino","doi":"10.1109/ISPSD57135.2023.10147683","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147683","url":null,"abstract":"We propose a new high voltage MOS (HVMOS) structure and its gate control circuit for integrating a bootstrap diode (BSD) function into a 600V high voltage IC (HVIC). The new HVMOS structure is free from a parasitic PNP, and its drain drift resistance is lowered without sacrificing breakdown voltage. The new gate control circuit maintain the gate voltage of HVMOS high regardless of the frequency. The new 600V HVIC realizes a sufficient charging capacity even at a low frequency operation and a high tolerance of a VS negative surge.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126723140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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