Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147641
Tianqi Liu, R. Martins, Yan Lu
This paper proposes a 600- V half-bridge GaN active gate driver with built-in dV/dt self-adaptive control utilizing a common-mode (CM) noise sensing and amplifying unit. The two 600- V LDMOS FETs existing in the conventional level shifter are used to sense the CM noises. When the dV/ dt rate is large enough, the sensed CM noises will be amplified and then rapidly provide a pull-down gate current for reducing the turn-on speed. As the dV/dt rate becomes smaller, the pull-down gate current will decrease adaptively, which achieving double peaks in the waveform of driving current. Compared to adding an extra high-voltage capacitor or LDMOS as a dV/dt sensor, this method has no additional area overhead and negligible control delay. At the same slew rate, we compare the low-side gate noises induced by Miller coupling at condition of either only $R_{ON}$ or the proposed self-adaptive adjustments. It shows that the noise peak in $V_{GL}$ for self-adaptive control decreases 46% at $V_{JN}=300mathrm{V}$ and also the noise envelope becomes smaller due to the dV/dt adjustment, dramatically reducing the probability of shoot-through current in the half bridge.
本文提出了一种600 V半桥GaN有源栅极驱动器，内置dV/dt自适应控制，利用共模(CM)噪声传感和放大单元。利用传统移电平器中存在的两个600 V LDMOS场效应管来检测CM噪声。当dV/ dt速率足够大时，检测到的CM噪声将被放大，然后迅速提供一个下拉栅极电流，以降低导通速度。随着dV/dt速率的减小，下拉栅极电流自适应减小，驱动电流波形出现双峰。与增加额外的高压电容器或LDMOS作为dV/dt传感器相比，该方法没有额外的面积开销和可忽略不计的控制延迟。在相同的转换率下，我们比较了仅R_{ON}$和提出的自适应调整条件下米勒耦合引起的低侧栅极噪声。结果表明，自适应控制的V_{GL}$的噪声峰值在V_{JN}=300 maththrm {V}$时降低了46%，并且由于dV/dt的调整，噪声包络线变小，显著降低了半电桥中穿透电流的概率。
{"title":"A 600-V GaN Active Gate Driver with Level Shifter Common-Mode Noise Sensing for Built-in dV/dt Self-Adaptive Control","authors":"Tianqi Liu, R. Martins, Yan Lu","doi":"10.1109/ISPSD57135.2023.10147641","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147641","url":null,"abstract":"This paper proposes a 600- V half-bridge GaN active gate driver with built-in dV/dt self-adaptive control utilizing a common-mode (CM) noise sensing and amplifying unit. The two 600- V LDMOS FETs existing in the conventional level shifter are used to sense the CM noises. When the dV/ dt rate is large enough, the sensed CM noises will be amplified and then rapidly provide a pull-down gate current for reducing the turn-on speed. As the dV/dt rate becomes smaller, the pull-down gate current will decrease adaptively, which achieving double peaks in the waveform of driving current. Compared to adding an extra high-voltage capacitor or LDMOS as a dV/dt sensor, this method has no additional area overhead and negligible control delay. At the same slew rate, we compare the low-side gate noises induced by Miller coupling at condition of either only $R_{ON}$ or the proposed self-adaptive adjustments. It shows that the noise peak in $V_{GL}$ for self-adaptive control decreases 46% at $V_{JN}=300mathrm{V}$ and also the noise envelope becomes smaller due to the dV/dt adjustment, dramatically reducing the probability of shoot-through current in the half bridge.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121624023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147546
S. Jang, S. Isukapati, Dongyoung Kim, Woongje Sung
This paper presents the first successful demonstration of cell-to-cell integrated 600 V 4H-SiC Lateral Bi-Directional MOSFET (LBiDMOS). The unit cell of the LBiDMOS is constructed by connecting two SiC MOSFET unit cells back-to-back with a common-drain configuration. By sharing the n-drift region in the middle and omitting the drain terminal, a novel and efficient structure was created. The peripheral design of the LBiDMOS was optimized in addition to the cell design to ensure blocking capabilities in both forward and reverse directions. The fabricated LBiDMOS exhibits symmetric bi-directional transfer, output, and blocking characteristics under the control of two gates. Over 600 V of breakdown voltage was achieved in both directions.
本文首次成功演示了电池间集成的600 V 4H-SiC横向双向MOSFET (LBiDMOS)。LBiDMOS的单元单元是通过用共漏配置将两个SiC MOSFET单元单元背对背连接而成的。通过共享中间的n漂移区和省略漏极，创造了一种新颖高效的结构。除了电池设计外，LBiDMOS的外围设计也进行了优化，以确保正向和反向的阻塞能力。制备的LBiDMOS在两个栅极控制下具有对称的双向转移、输出和阻塞特性。双向击穿电压均超过600 V。
{"title":"First Demonstration of 600 V 4H-SiC Lateral Bi-Directional Metal-Oxide-Semiconductor Field-Effect Transistor (LBiDMOS)","authors":"S. Jang, S. Isukapati, Dongyoung Kim, Woongje Sung","doi":"10.1109/ISPSD57135.2023.10147546","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147546","url":null,"abstract":"This paper presents the first successful demonstration of cell-to-cell integrated 600 V 4H-SiC Lateral Bi-Directional MOSFET (LBiDMOS). The unit cell of the LBiDMOS is constructed by connecting two SiC MOSFET unit cells back-to-back with a common-drain configuration. By sharing the n-drift region in the middle and omitting the drain terminal, a novel and efficient structure was created. The peripheral design of the LBiDMOS was optimized in addition to the cell design to ensure blocking capabilities in both forward and reverse directions. The fabricated LBiDMOS exhibits symmetric bi-directional transfer, output, and blocking characteristics under the control of two gates. Over 600 V of breakdown voltage was achieved in both directions.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122000709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147538
Stefan Karner, O. Blank, J. Keckes, M. Rösch, Seung Hwan Lee, S. Léomant
The ongoing trend towards electrification and digitalization requires the continuous improvement of high frequency, high power density switching solutions such as split-gate Si trench power MOSFETs. However, their pure figure of merit (FOM) related performance improvement through conventional scaling has reached a physical limit. Similar to the approaches for planar MOSFETs, the device performance can also be improved by strain engineering, leading to a modified charge carrier mobility in the electrically active monocrystalline Si. Therefore, a novel strain engineering approach is proposed for Si trench power MOSFETs, adding a strain functionality to the trenches on top of their charge compensation purpose. It is shown that the device performance is increased by up to 16.8%, which is achieved by not only altering the mobility in the channel but also influencing the drift region of the device. Since the correlation of electrical and mechanical device characteristics is key to effectively implement strain engineering concepts in Si trench power MOSFETs, high-precision nanoscale stress and strain characterization techniques as well as finite element mechanical simulations are established and presented.
{"title":"Strain Engineering in Modern Si Trench Power MOSFETs — A Performance Booster for Future Generations","authors":"Stefan Karner, O. Blank, J. Keckes, M. Rösch, Seung Hwan Lee, S. Léomant","doi":"10.1109/ISPSD57135.2023.10147538","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147538","url":null,"abstract":"The ongoing trend towards electrification and digitalization requires the continuous improvement of high frequency, high power density switching solutions such as split-gate Si trench power MOSFETs. However, their pure figure of merit (FOM) related performance improvement through conventional scaling has reached a physical limit. Similar to the approaches for planar MOSFETs, the device performance can also be improved by strain engineering, leading to a modified charge carrier mobility in the electrically active monocrystalline Si. Therefore, a novel strain engineering approach is proposed for Si trench power MOSFETs, adding a strain functionality to the trenches on top of their charge compensation purpose. It is shown that the device performance is increased by up to 16.8%, which is achieved by not only altering the mobility in the channel but also influencing the drift region of the device. Since the correlation of electrical and mechanical device characteristics is key to effectively implement strain engineering concepts in Si trench power MOSFETs, high-precision nanoscale stress and strain characterization techniques as well as finite element mechanical simulations are established and presented.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147471
Ivana Kovacevic-Badstuebner, E. Mengotti, P. Natzke, S. Race, E. Bianda, J. Jormanainen, U. Grossner
This paper shows a comparison of power cycling (PC) lifetime between SiC power MOSFET baseplate-less modules with Si3N4 and Al2O3 DBC substrates at heating on/off-times of 2 s. As the modules were designed with soft Si-gel encapsulation and silver sinter die attach, the dominant failure mechanism was bond wire lift-off. Electro-thermal-mechanical (ETM) simulations are performed to support the lifetime analysis on a small set of statistical data. The results point out that the PC capability of the Al wires is not significantly affected by changing the semiconductor material from Si to SiC. Furthermore, the developed ETM simulations show that Si3N4 substrates will cause a faster temperature rise time, but will not lead to a significantly higher thermo-mechanical stress of the bond wire foot.
{"title":"Power Cycling of Sintered SiC Power MOSFET Baseplate-less Modules with Aluminum Oxide and Silicon Nitride Substrates","authors":"Ivana Kovacevic-Badstuebner, E. Mengotti, P. Natzke, S. Race, E. Bianda, J. Jormanainen, U. Grossner","doi":"10.1109/ISPSD57135.2023.10147471","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147471","url":null,"abstract":"This paper shows a comparison of power cycling (PC) lifetime between SiC power MOSFET baseplate-less modules with Si3N4 and Al2O3 DBC substrates at heating on/off-times of 2 s. As the modules were designed with soft Si-gel encapsulation and silver sinter die attach, the dominant failure mechanism was bond wire lift-off. Electro-thermal-mechanical (ETM) simulations are performed to support the lifetime analysis on a small set of statistical data. The results point out that the PC capability of the Al wires is not significantly affected by changing the semiconductor material from Si to SiC. Furthermore, the developed ETM simulations show that Si3N4 substrates will cause a faster temperature rise time, but will not lead to a significantly higher thermo-mechanical stress of the bond wire foot.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115032500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147513
Mengqi Wang, Jiupeng Zhang, W. Ng, H. Nishio, Motomitsu Iwamoto, H. Sumida
In this paper we present an integrated smart gate driver (SGD) capable of in-operation detection of SiC power MOSFET aging. The SGD IC monitors the discrete time differentiated (DTD) gate voltage slope, $Delta V_{GS}$, to identify the time to start of the Miller plateau, $t_{1}$, during turn-on. Under known operating conditions, the value of $t_{1}$ can be used as an aging indicator to detect changes in the Miller plateau due to threshold voltage shifts. A synthesized digital central control unit (CCU) within the SGD can adjust the gate drive profile and gate drive bus voltage ($V_{DR}$) based on the aging-induced changes in $t_{1}$. We demonstrate that following 200 hours of high-temperature gate bias (HTGB) at 200 °C, $V_{DR, stress}=30 mathrm{V}$, aging-induced gate degradation of a 1.2 kV 75A SiC MOSFET results in a decrease in drain current ($I_{D}$) by 1.5%. An increase in $V_{text{MP}}$ by 0.5 V can restore $I_{D}$ by 1.7% to pre-aged levels. This is achieved by adjusting the digital pulse width modulation (PWM) duty cycle of the on-chip DC-DC boost converter.
{"title":"Application of a Smart Gate Driver to Detect Aging in SiC Power MOSFETs","authors":"Mengqi Wang, Jiupeng Zhang, W. Ng, H. Nishio, Motomitsu Iwamoto, H. Sumida","doi":"10.1109/ISPSD57135.2023.10147513","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147513","url":null,"abstract":"In this paper we present an integrated smart gate driver (SGD) capable of in-operation detection of SiC power MOSFET aging. The SGD IC monitors the discrete time differentiated (DTD) gate voltage slope, $Delta V_{GS}$, to identify the time to start of the Miller plateau, $t_{1}$, during turn-on. Under known operating conditions, the value of $t_{1}$ can be used as an aging indicator to detect changes in the Miller plateau due to threshold voltage shifts. A synthesized digital central control unit (CCU) within the SGD can adjust the gate drive profile and gate drive bus voltage ($V_{DR}$) based on the aging-induced changes in $t_{1}$. We demonstrate that following 200 hours of high-temperature gate bias (HTGB) at 200 °C, $V_{DR, stress}=30 mathrm{V}$, aging-induced gate degradation of a 1.2 kV 75A SiC MOSFET results in a decrease in drain current ($I_{D}$) by 1.5%. An increase in $V_{text{MP}}$ by 0.5 V can restore $I_{D}$ by 1.7% to pre-aged levels. This is achieved by adjusting the digital pulse width modulation (PWM) duty cycle of the on-chip DC-DC boost converter.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129596613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147418
Li Liu, Jue Wang, Zishi Wang, Miaoguang Bai, Junze Li, Zhengyun Zhu, Hongyi Xu, Na Ren, Qing Guo, Kuang Sheng
This paper demonstrates a SiC lateral MOSFET (LMOS) with DOUBLE RESURFs (reduce surface field) technology to improve the device's breakdown voltage. The electrical characteristics and analysis of the fabricated SiC LMOS are carried out in terms of output, transfer and blocking characteristics, as well as the leakage current mechanisms. In particular, the effect of the length of the P-top RESURFs on device performance is studied. The experimental results indicate that the SiC LMOS with P-top RESURFs of length $7 mumathrm{m}$ exhibits best comprehensively with the highest breakdown voltage of 970 V, the highest Baliga's figure of merit BFOM of 83.6MW/cm2, and low (gate) leakage current. Which is recommended in this work and also encourages its further application in the power integrated circuits (Power ICs).
{"title":"Electrical Characterization and Analysis of 4H-SiC Lateral MOSFET (LMOS) for High-Voltage Power Integrated Circuits","authors":"Li Liu, Jue Wang, Zishi Wang, Miaoguang Bai, Junze Li, Zhengyun Zhu, Hongyi Xu, Na Ren, Qing Guo, Kuang Sheng","doi":"10.1109/ISPSD57135.2023.10147418","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147418","url":null,"abstract":"This paper demonstrates a SiC lateral MOSFET (LMOS) with DOUBLE RESURFs (reduce surface field) technology to improve the device's breakdown voltage. The electrical characteristics and analysis of the fabricated SiC LMOS are carried out in terms of output, transfer and blocking characteristics, as well as the leakage current mechanisms. In particular, the effect of the length of the P-top RESURFs on device performance is studied. The experimental results indicate that the SiC LMOS with P-top RESURFs of length $7 mumathrm{m}$ exhibits best comprehensively with the highest breakdown voltage of 970 V, the highest Baliga's figure of merit BFOM of 83.6MW/cm2, and low (gate) leakage current. Which is recommended in this work and also encourages its further application in the power integrated circuits (Power ICs).","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147489
Marina Ruggeri, P. Calenzo, F. Morancho, L. Masoero, R. Germana, Alessandro Nodari, R. Monflier
In this paper, we investigated the drain to source breakdown voltage (BVdss) instability during avalanche current drain stress of Shielded Gate MOSFET (SG-MOSFET) structure and we propose a new methodology to correlate electrical results to TCAD simulations. The presence of positive charged states at the Field Plate (FP) oxide/Si interface was confirmed by Capacitance Deep Level Transient Spectroscopy (C-DLTS). Thus, it was implemented in TCAD simulations that predict the experimental behavior of two architectures. Thanks to these results, walk-in contributors were discriminated to suggest a pathway to increase device robustness with a slight Ron impact.
{"title":"Investigation of BVdss instability in trench power MOSFET through DLTS, electrical characterization and TCAD simulations","authors":"Marina Ruggeri, P. Calenzo, F. Morancho, L. Masoero, R. Germana, Alessandro Nodari, R. Monflier","doi":"10.1109/ISPSD57135.2023.10147489","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147489","url":null,"abstract":"In this paper, we investigated the drain to source breakdown voltage (BVdss) instability during avalanche current drain stress of Shielded Gate MOSFET (SG-MOSFET) structure and we propose a new methodology to correlate electrical results to TCAD simulations. The presence of positive charged states at the Field Plate (FP) oxide/Si interface was confirmed by Capacitance Deep Level Transient Spectroscopy (C-DLTS). Thus, it was implemented in TCAD simulations that predict the experimental behavior of two architectures. Thanks to these results, walk-in contributors were discriminated to suggest a pathway to increase device robustness with a slight Ron impact.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129715758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147649
Junjie Yang, Yanlin Wu, Muqin Nuo, Zheng-wei Chen, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei
In this study, we investigate the role of hole injection and spreading in a p-GaN gate HEMT for addressing buffer-related dynamic $R_{text{ON}}$ degradations. The proposed structure includes a buried AlGaN layer that acts as a hole barrier and provides a hole spreading channel (BHSC) under the 2DEG channel. During the on-state, holes are injected from the gate and spread along the BHSC. We observe that the hole injection is enhanced with increasing temperatures. The lateral spreading of holes is critical for suppressing buffer trapping outside of the gate region. As the suppression of buffer trapping is enhanced with an increase in $V_{text{GS}}$, the dynamic $R_{text{ON}}$ is dramatically reduced. We then adopt the widely used back-gating test to evaluate the dynamic $R_{text{ON}}$ when buffer trapping is intentionally introduced. Finally, we demonstrate that the proposed device with BHSC exhibits nearly zero buffer-related dynamic $R_{text{ON}}$ degradation from room temperature to 125°C.
{"title":"Exploitation of Hole Injection and Spreading for Dynamic Enhancement in p-GaN Gate HEMT under Room/High Temperatures","authors":"Junjie Yang, Yanlin Wu, Muqin Nuo, Zheng-wei Chen, Xuelin Yang, B. Shen, Maojun Wang, Jin Wei","doi":"10.1109/ISPSD57135.2023.10147649","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147649","url":null,"abstract":"In this study, we investigate the role of hole injection and spreading in a p-GaN gate HEMT for addressing buffer-related dynamic $R_{text{ON}}$ degradations. The proposed structure includes a buried AlGaN layer that acts as a hole barrier and provides a hole spreading channel (BHSC) under the 2DEG channel. During the on-state, holes are injected from the gate and spread along the BHSC. We observe that the hole injection is enhanced with increasing temperatures. The lateral spreading of holes is critical for suppressing buffer trapping outside of the gate region. As the suppression of buffer trapping is enhanced with an increase in $V_{text{GS}}$, the dynamic $R_{text{ON}}$ is dramatically reduced. We then adopt the widely used back-gating test to evaluate the dynamic $R_{text{ON}}$ when buffer trapping is intentionally introduced. Finally, we demonstrate that the proposed device with BHSC exhibits nearly zero buffer-related dynamic $R_{text{ON}}$ degradation from room temperature to 125°C.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"42 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147582
Hiroto Sakai, Yuta Okawauchi, Shinji Yato, Hideo Araki, Takayuki Atago, K. Nakahara
This study suggests a method to derive an approximate but sufficient formula of an open-loop transfer function for examining the oscillation seen for power devices connected in parallel. The stability of parallel-connected power devices is evaluated by an equivalent circuit and its open-loop characteristics are analyzed using simulation. The simulated Bode diagram is classified into bands by the estimated poles and zeros, and accordingly, the open-loop transfer function is successfully expressed as a simplified analytical form. This calculation makes it clear that while gate-to-drain capacitance prevents self-turn-on and enhances high-speed switching, it also causes parallel oscillation. This insight achieved by simulations was experimentally confirmed.
{"title":"Simplified Open-Loop Transfer Functions to Analyze Influential Parasitic Parameters for Oscillation Caused by Parallel Connected Transistors","authors":"Hiroto Sakai, Yuta Okawauchi, Shinji Yato, Hideo Araki, Takayuki Atago, K. Nakahara","doi":"10.1109/ISPSD57135.2023.10147582","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147582","url":null,"abstract":"This study suggests a method to derive an approximate but sufficient formula of an open-loop transfer function for examining the oscillation seen for power devices connected in parallel. The stability of parallel-connected power devices is evaluated by an equivalent circuit and its open-loop characteristics are analyzed using simulation. The simulated Bode diagram is classified into bands by the estimated poles and zeros, and accordingly, the open-loop transfer function is successfully expressed as a simplified analytical form. This calculation makes it clear that while gate-to-drain capacitance prevents self-turn-on and enhances high-speed switching, it also causes parallel oscillation. This insight achieved by simulations was experimentally confirmed.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116323990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147635
Satoshi Yoshida, T. Yasuzumi, Tsuguhiro Tanaka, Yasuyuki Fujiwara
A semi-bridgeless power factor correction (PFC) converter offers an excellent trade-off between efficiency, conducted electro-magnetic interference (EMI) performance, and cost. However, reduction of radiated EMI remains as an issue. This paper proposes a multichip package design for realizing low radiated EMI semi-bridgeless PFC converters. The proposed package design was applied to a 1.0 kW semi-bridgeless PFC converter and reduction of the radiated EMI was successfully demonstrated.
{"title":"Package Design Consideration for Suppressing Radiated EMI Noise in Semi-Bridgeless PFC Converters","authors":"Satoshi Yoshida, T. Yasuzumi, Tsuguhiro Tanaka, Yasuyuki Fujiwara","doi":"10.1109/ISPSD57135.2023.10147635","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147635","url":null,"abstract":"A semi-bridgeless power factor correction (PFC) converter offers an excellent trade-off between efficiency, conducted electro-magnetic interference (EMI) performance, and cost. However, reduction of radiated EMI remains as an issue. This paper proposes a multichip package design for realizing low radiated EMI semi-bridgeless PFC converters. The proposed package design was applied to a 1.0 kW semi-bridgeless PFC converter and reduction of the radiated EMI was successfully demonstrated.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126873661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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