Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145679
K. Jain, D. Dunn, P. Dutta, J. M. Himelick
An optical method for rapid assessment of SOI structures is developed. This method is based upon angle lapping and etching to observe crystal defects in SOI structures. Traditional beveling methods introduce defects due to mechanical damage resulting from unintentional scratches caused by the material breaking loose from the sides of the sample. The proposed approach covers the sidewalls and the surface of the sample during lapping with a waxy material which provides a thick soft matrix to embed loose particles and eliminate the scratches. The method has been used to investigate both SIMOX and ISE structures. The proposed method has a greater sensitivity of defect detection than the cross-sectional transmission electron microscopy commonly used in defect studies and it is also well suited for evaluating process induced defects in bulk silicon devices.<>
{"title":"A new optical method for identifying crystal defects in silicon-on-insulator materials","authors":"K. Jain, D. Dunn, P. Dutta, J. M. Himelick","doi":"10.1109/SOSSOI.1990.145679","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145679","url":null,"abstract":"An optical method for rapid assessment of SOI structures is developed. This method is based upon angle lapping and etching to observe crystal defects in SOI structures. Traditional beveling methods introduce defects due to mechanical damage resulting from unintentional scratches caused by the material breaking loose from the sides of the sample. The proposed approach covers the sidewalls and the surface of the sample during lapping with a waxy material which provides a thick soft matrix to embed loose particles and eliminate the scratches. The method has been used to investigate both SIMOX and ISE structures. The proposed method has a greater sensitivity of defect detection than the cross-sectional transmission electron microscopy commonly used in defect studies and it is also well suited for evaluating process induced defects in bulk silicon devices.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121265346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145728
Q. Tong, X.-L. Xu, H.-Z. Zhang
A new SOI fully depleted buried channel MOSFET (FD BCMOS) has been developed which is different from conventional surface buried channel MOS devices in which a pn junction exists at the channel surface. Moreover, the pn junction is totally eliminated in the device structure. Numerical simulation and practical fabrication have demonstrated that no kink effect is seen and the device has excellent performance for VLSI applications due to the absence of the pn junction and superior material quality prepared by silicon wafer direct bonding technology.<>
{"title":"Elimination of kink effect in fully depleted buried channel SOI MOSFET based on silicon direct bonding technology","authors":"Q. Tong, X.-L. Xu, H.-Z. Zhang","doi":"10.1109/SOSSOI.1990.145728","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145728","url":null,"abstract":"A new SOI fully depleted buried channel MOSFET (FD BCMOS) has been developed which is different from conventional surface buried channel MOS devices in which a pn junction exists at the channel surface. Moreover, the pn junction is totally eliminated in the device structure. Numerical simulation and practical fabrication have demonstrated that no kink effect is seen and the device has excellent performance for VLSI applications due to the absence of the pn junction and superior material quality prepared by silicon wafer direct bonding technology.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145706
P. Zavracky, L. Allen, D. Vu, M. Batty
A program is briefly reported aimed at the development of SOI material using a seeded zone melting recrystallization (ZMR) technique which is known as isolated silicon epitaxy (ISE). The ISE process has the flexibility required to meet the demands of a variety of different applications. Specifically, thin films of epitaxial Si (0.10 mu m) on thin SiO/sub 2/ (0.4 mu m) layers are being produced for fully depleted CMOS applications. At the same time, low-defect thick-film Si (>2 mu m) on thick oxide (1-2 mu m) are being fabricated for bipolar applications.<>
{"title":"Advances in recrystallization technology","authors":"P. Zavracky, L. Allen, D. Vu, M. Batty","doi":"10.1109/SOSSOI.1990.145706","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145706","url":null,"abstract":"A program is briefly reported aimed at the development of SOI material using a seeded zone melting recrystallization (ZMR) technique which is known as isolated silicon epitaxy (ISE). The ISE process has the flexibility required to meet the demands of a variety of different applications. Specifically, thin films of epitaxial Si (0.10 mu m) on thin SiO/sub 2/ (0.4 mu m) layers are being produced for fully depleted CMOS applications. At the same time, low-defect thick-film Si (>2 mu m) on thick oxide (1-2 mu m) are being fabricated for bipolar applications.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145755
A. Auberton-Herve
The advantages of SOI technologies in CMOS for rad-hard applications and for high performances are considered. The author discusses the need for rad-hard circuits beyond the military or space requirements.<>
{"title":"SOI technologies applications: trends in VLSI","authors":"A. Auberton-Herve","doi":"10.1109/SOSSOI.1990.145755","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145755","url":null,"abstract":"The advantages of SOI technologies in CMOS for rad-hard applications and for high performances are considered. The author discusses the need for rad-hard circuits beyond the military or space requirements.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130565216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145686
J.S.T. Huang, J. Kueng
The snapback effect in N channel SOI devices in which the drain to source breakdown voltage is less than the drain to body breakdown voltage is addressed. The purpose is to present an approach to snapback modeling based on nonlinear feedback mechanisms between impact ionization current, the body to source forward bias, the threshold voltage, and the drain current supplying carriers to enhance impact ionization. NMOS SOI devices with the body either tied to the source of floating are analyzed. As the gate voltage first increases and then decreases, the device first operates in the subthreshold region, then jumps abruptly to the strong inversion regime and finally jumps back to the subthreshold region of operation. The model results in transcendental feedback expressions. It is possible to obtain closed-form expressions for the device currents and voltages at the jump points.<>
{"title":"An approach to analytical modeling of snapback in SOI devices","authors":"J.S.T. Huang, J. Kueng","doi":"10.1109/SOSSOI.1990.145686","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145686","url":null,"abstract":"The snapback effect in N channel SOI devices in which the drain to source breakdown voltage is less than the drain to body breakdown voltage is addressed. The purpose is to present an approach to snapback modeling based on nonlinear feedback mechanisms between impact ionization current, the body to source forward bias, the threshold voltage, and the drain current supplying carriers to enhance impact ionization. NMOS SOI devices with the body either tied to the source of floating are analyzed. As the gate voltage first increases and then decreases, the device first operates in the subthreshold region, then jumps abruptly to the strong inversion regime and finally jumps back to the subthreshold region of operation. The model results in transcendental feedback expressions. It is possible to obtain closed-form expressions for the device currents and voltages at the jump points.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133266891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145696
T. Her, P.S. Liu, G. Li, C. Chi, J. Brandewie, J. White
In an n-channel silicon-on-insulator (SOI) MOSFET the accumulation of holes in the floating substrate can lead to the rise of the substrate potential and thus turn on the parastic source-substrate-drain bipolar transistor. To minimize the floating-substrate effect, it is essential to reduce the parasitic bipolar transistor current gain ( beta ). The authors examine the effects of beta on the subthreshold slope and drain breakdown voltage (BV/sub DSS/). The BV/sub DSS/ is improved by reducing beta , and the punch-through currents are well correlated with the results of beta and drain-substrate junction leakage currents. The proposed process to improve BV/sub DSS/ is implemented solely by beta reduction without using any exhausted source/drain engineering process to reduce the multiplication factor. The device with lower beta gives higher substrate-source (base) currents which can effectively reduce the substrate potential.<>
{"title":"Parasitic BJT design consideration in SOI MOSFETs","authors":"T. Her, P.S. Liu, G. Li, C. Chi, J. Brandewie, J. White","doi":"10.1109/SOSSOI.1990.145696","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145696","url":null,"abstract":"In an n-channel silicon-on-insulator (SOI) MOSFET the accumulation of holes in the floating substrate can lead to the rise of the substrate potential and thus turn on the parastic source-substrate-drain bipolar transistor. To minimize the floating-substrate effect, it is essential to reduce the parasitic bipolar transistor current gain ( beta ). The authors examine the effects of beta on the subthreshold slope and drain breakdown voltage (BV/sub DSS/). The BV/sub DSS/ is improved by reducing beta , and the punch-through currents are well correlated with the results of beta and drain-substrate junction leakage currents. The proposed process to improve BV/sub DSS/ is implemented solely by beta reduction without using any exhausted source/drain engineering process to reduce the multiplication factor. The device with lower beta gives higher substrate-source (base) currents which can effectively reduce the substrate potential.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130826355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145705
U. Bussmann, A. K. Robinson, P. Hemment, G. Campisi
A method of forming islands that utilizes masking layers during implantation was used. Windows in the mask define the silicon island positions. In these regions the layer structure corresponds to the conventional SIMOX structure. However, in the mask region, where the oxygen ions loose part of their kinetic energy before reaching the silicon, the buried oxide is shifted towards the surface. The aim is to achieve total dielectric isolation by implantation and annealing only, thus avoiding a subsequent LOCOS or mesa etching step. New experimental parameters, which include masking material, mask thickness and the geometry of the bevel edge, determine the structural properties of the non-planar oxide as well as the surface topology. Polycrystalline silicon masks have been successfully used to form continuous non-planar buried oxide layers. Experimental results are briefly discussed.<>
{"title":"SOI device islands formed by oxygen implantation through patterned masking layers","authors":"U. Bussmann, A. K. Robinson, P. Hemment, G. Campisi","doi":"10.1109/SOSSOI.1990.145705","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145705","url":null,"abstract":"A method of forming islands that utilizes masking layers during implantation was used. Windows in the mask define the silicon island positions. In these regions the layer structure corresponds to the conventional SIMOX structure. However, in the mask region, where the oxygen ions loose part of their kinetic energy before reaching the silicon, the buried oxide is shifted towards the surface. The aim is to achieve total dielectric isolation by implantation and annealing only, thus avoiding a subsequent LOCOS or mesa etching step. New experimental parameters, which include masking material, mask thickness and the geometry of the bevel edge, determine the structural properties of the non-planar oxide as well as the surface topology. Polycrystalline silicon masks have been successfully used to form continuous non-planar buried oxide layers. Experimental results are briefly discussed.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124112101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145767
X. Xiao, J. Sturm, P. Schwartz, K. Goel
Reported is a new optical intensity modulator at 1.3 mu m which utilizes a Fabry-Perot resonant cavity implemented by silicon-on-insulator technology to achieve a high modulation depth. A p-i-n diode modulator is placed outside the cavity. The 1.3 mu m light comes in from the top, bounces back-and-forth inside the Fabry-Perot cavity, and is partially reflected back and partially transmitted through. At resonance, the reflectance is minimized. Forward biasing the p-i-n diode modulates the phase of the laser light inside the cavity and shifts the resonance of the cavity to convert the phase modulation to intensity modulation. Device fabrication and testing are outlined.<>
{"title":"Vertical 1.3 mu m optical modulator in silicon-on-insulator","authors":"X. Xiao, J. Sturm, P. Schwartz, K. Goel","doi":"10.1109/SOSSOI.1990.145767","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145767","url":null,"abstract":"Reported is a new optical intensity modulator at 1.3 mu m which utilizes a Fabry-Perot resonant cavity implemented by silicon-on-insulator technology to achieve a high modulation depth. A p-i-n diode modulator is placed outside the cavity. The 1.3 mu m light comes in from the top, bounces back-and-forth inside the Fabry-Perot cavity, and is partially reflected back and partially transmitted through. At resonance, the reflectance is minimized. Forward biasing the p-i-n diode modulates the phase of the laser light inside the cavity and shifts the resonance of the cavity to convert the phase modulation to intensity modulation. Device fabrication and testing are outlined.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122931882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145711
A. Pérez, J. Samitier, A. Cornet, J. Morante, P. Hemment, K. Homewood
An analysis was carried out of SOI/SIMOX structures obtained by sequential implantation and annealing (SIA). The analysis of these structures has been made in relation to those obtained by an equivalent standard single implant and anneal (SS structures), by means of infrared reflection spectroscopy. The use of a fast Fourier transform infrared (FTIR) system allows the combination of a low measuring time of the spectra (on the order of several minutes) with a high spectral resolution (up to 0.02 cm/sup -1/). Complementary optical measurements such as photoluminescence and Raman spectroscopy using different excitation powers and wavelengths reveal the higher quality of the surface region of the top silicon layer free of precipitates in the SIA material. These data, together with the FTIR results, show the potential of the SIA technique for obtaining high quality quasi-ideal SOI structures.<>
{"title":"Infrared reflection spectroscopy analysis of SIMOX material obtained by multiple implant","authors":"A. Pérez, J. Samitier, A. Cornet, J. Morante, P. Hemment, K. Homewood","doi":"10.1109/SOSSOI.1990.145711","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145711","url":null,"abstract":"An analysis was carried out of SOI/SIMOX structures obtained by sequential implantation and annealing (SIA). The analysis of these structures has been made in relation to those obtained by an equivalent standard single implant and anneal (SS structures), by means of infrared reflection spectroscopy. The use of a fast Fourier transform infrared (FTIR) system allows the combination of a low measuring time of the spectra (on the order of several minutes) with a high spectral resolution (up to 0.02 cm/sup -1/). Complementary optical measurements such as photoluminescence and Raman spectroscopy using different excitation powers and wavelengths reveal the higher quality of the surface region of the top silicon layer free of precipitates in the SIA material. These data, together with the FTIR results, show the potential of the SIA technique for obtaining high quality quasi-ideal SOI structures.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145724
J. Wang, N. Kistler, J. Woo, C. Viswanathan
The threshold voltage instability at low temperatures due to the floating Si film in partially depleted SIMOX was examined at low temperatures under normal operating conditions. Floating-film SOI MOS transistors suffer an accumulation of holes generated by impact ionization near the drain, at the lower Si film interface. As the potential at this interface increases due to hole accumulation, the source junction becomes forward biased, limiting the amount of charge which can accumulate. This causes the saturation kink effect. The increase in potential at the lower interface acts analogously to a positive bias in bulk devices and effectively decreases the threshold voltage of the device. The use of the channel contact alleviates the hole accumulation effect by providing a conducting path for the generated holes. Hence, the grounded film exhibits a higher threshold voltage than the floating film.<>
{"title":"Threshold voltage instability at low temperatures in partially depleted thin film SOI MOSFETs","authors":"J. Wang, N. Kistler, J. Woo, C. Viswanathan","doi":"10.1109/SOSSOI.1990.145724","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145724","url":null,"abstract":"The threshold voltage instability at low temperatures due to the floating Si film in partially depleted SIMOX was examined at low temperatures under normal operating conditions. Floating-film SOI MOS transistors suffer an accumulation of holes generated by impact ionization near the drain, at the lower Si film interface. As the potential at this interface increases due to hole accumulation, the source junction becomes forward biased, limiting the amount of charge which can accumulate. This causes the saturation kink effect. The increase in potential at the lower interface acts analogously to a positive bias in bulk devices and effectively decreases the threshold voltage of the device. The use of the channel contact alleviates the hole accumulation effect by providing a conducting path for the generated holes. Hence, the grounded film exhibits a higher threshold voltage than the floating film.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125890485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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