Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145721
J. Blanc, J. Bonaimé, E. Delevoye, J. Gautier, J. de Pontcharra, R. Truche, E. Dupont-Nivet, J.L. Martin, J. Montaron
Development of a fully CMOS and bipolar compatible JFET process on SIMOX is reported. The main characteristics obtained on a two-junction-type JFET realized in 1- mu m silicon epitaxy on SOI material are presented. A mesa-structure has been chosen for lateral isolation. A deep junction is arsenic implanted before epitaxy at 1000 degrees C; the channel and drain/source doping levels are controlled by ion implantation; the upper junction is diffused from polysilicon. Radiation dose, neutron fluence, and photocurrent effects are described.<>
{"title":"P-JFET on SIMOX for rad-hard analog devices","authors":"J. Blanc, J. Bonaimé, E. Delevoye, J. Gautier, J. de Pontcharra, R. Truche, E. Dupont-Nivet, J.L. Martin, J. Montaron","doi":"10.1109/SOSSOI.1990.145721","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145721","url":null,"abstract":"Development of a fully CMOS and bipolar compatible JFET process on SIMOX is reported. The main characteristics obtained on a two-junction-type JFET realized in 1- mu m silicon epitaxy on SOI material are presented. A mesa-structure has been chosen for lateral isolation. A deep junction is arsenic implanted before epitaxy at 1000 degrees C; the channel and drain/source doping levels are controlled by ion implantation; the upper junction is diffused from polysilicon. Radiation dose, neutron fluence, and photocurrent effects are described.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127405640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145685
M. Gao, J. Colinge, L. Lauwers, S. Wu, C. Claeys
The dual-MOSFET structure proposed consists of two SOI nMOSFETs, T/sub 1/ and T/sub 2/, in series, but measured as a single device (T/sub 1/ to the source and T/sub 2/ to the drain) with a common gate electrode. The N/sup +/ region in between T/sub 1/ and T/sub 2/ is kept floating. This structure can confine the kink effect to the upper transistor T/sub 2/ and thus successfully keeps the lower transistor T/sub 1/ from undergoing pinch-off, impact ionization, and the kink effect. If the channel length of T/sub 1/ is longer than that of T/sub 2/, then T/sub 1/ will dominate the overall output characteristics of the device. As a result, the kink effect is eliminated from the overall output characteristics. This structure can also confine the parasitic bipolar effect only to the upper transistor T/sub 2/. Since the base hole current of T/sub 2/ will recombine in the common N/sup +/ region, it cannot reach the base region of the lower transistor T/sub 1/. Results of measurements and simulation are given.<>
{"title":"Dual-MOSFET structure for suppression of kink in SOI MOSFETs at room and liquid helium temperatures","authors":"M. Gao, J. Colinge, L. Lauwers, S. Wu, C. Claeys","doi":"10.1109/SOSSOI.1990.145685","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145685","url":null,"abstract":"The dual-MOSFET structure proposed consists of two SOI nMOSFETs, T/sub 1/ and T/sub 2/, in series, but measured as a single device (T/sub 1/ to the source and T/sub 2/ to the drain) with a common gate electrode. The N/sup +/ region in between T/sub 1/ and T/sub 2/ is kept floating. This structure can confine the kink effect to the upper transistor T/sub 2/ and thus successfully keeps the lower transistor T/sub 1/ from undergoing pinch-off, impact ionization, and the kink effect. If the channel length of T/sub 1/ is longer than that of T/sub 2/, then T/sub 1/ will dominate the overall output characteristics of the device. As a result, the kink effect is eliminated from the overall output characteristics. This structure can also confine the parasitic bipolar effect only to the upper transistor T/sub 2/. Since the base hole current of T/sub 2/ will recombine in the common N/sup +/ region, it cannot reach the base region of the lower transistor T/sub 1/. Results of measurements and simulation are given.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129691662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145687
G. A. Armstrong, W. French, J. Alderman
Model validation for submicron SIMOX (separation by implantation of oxygen) transistors by careful comparison of the simulated and measured snapback voltages as a function of gate length is reported. The transistors were fabricated in SIMOX material with an estimated film thickness of 0.2 mu m, a buried insulator thickness of 0.4 mu m, and a gate oxide thickness of 20 nm. The measured threshold voltage of the 1 mu m n-channel transistor was 1.08 V and the subthreshold slope 86 mV/decade. The snapback voltage was defined as the maximum drain voltage at which the transistor turns off, when swept in the direction of decreasing gate voltage. Excellent agreement has been achieved over a range of transistor gate lengths down to 0.5 mu m. Two-dimensional device simulation can be used to determine the optimum transistor structure by considering the factors associated with engineering both the source and drain regions with a view to maximizing the breakdown voltage.<>
{"title":"Modelling of breakdown voltage in sub-micron SOI transistors","authors":"G. A. Armstrong, W. French, J. Alderman","doi":"10.1109/SOSSOI.1990.145687","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145687","url":null,"abstract":"Model validation for submicron SIMOX (separation by implantation of oxygen) transistors by careful comparison of the simulated and measured snapback voltages as a function of gate length is reported. The transistors were fabricated in SIMOX material with an estimated film thickness of 0.2 mu m, a buried insulator thickness of 0.4 mu m, and a gate oxide thickness of 20 nm. The measured threshold voltage of the 1 mu m n-channel transistor was 1.08 V and the subthreshold slope 86 mV/decade. The snapback voltage was defined as the maximum drain voltage at which the transistor turns off, when swept in the direction of decreasing gate voltage. Excellent agreement has been achieved over a range of transistor gate lengths down to 0.5 mu m. Two-dimensional device simulation can be used to determine the optimum transistor structure by considering the factors associated with engineering both the source and drain regions with a view to maximizing the breakdown voltage.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129856431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145688
L. Mcdaid, S. Hall, J. Marsland, W. Eccleston, J. Alderman, K. R. Cook, R. Bunyan, M. Uren
A simple model is presented using one-dimensional bipolar theory to predict the holding voltage for silicon-on-insulator MOSFETs operating in the latch state. The holding voltage is a function of channel length as predicted by the model, and good agreement with experimental data is obtained for a recombination lifetime of 0.7 ns and k=0.015. The model also predicts that if the lifetime is reduced to 0.4 ns the holding voltage is only slightly increased for short-channel devices suggesting that decreasing the lifetime in the body by external means (e.g., gold doping) has little effect for small gate lengths. In addition the model can also predict the temperature dependence of the holding voltage.<>
{"title":"A simple model to predict the holding voltage for SOI MOSFETs operating in the latch state","authors":"L. Mcdaid, S. Hall, J. Marsland, W. Eccleston, J. Alderman, K. R. Cook, R. Bunyan, M. Uren","doi":"10.1109/SOSSOI.1990.145688","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145688","url":null,"abstract":"A simple model is presented using one-dimensional bipolar theory to predict the holding voltage for silicon-on-insulator MOSFETs operating in the latch state. The holding voltage is a function of channel length as predicted by the model, and good agreement with experimental data is obtained for a recombination lifetime of 0.7 ns and k=0.015. The model also predicts that if the lifetime is reduced to 0.4 ns the holding voltage is only slightly increased for short-channel devices suggesting that decreasing the lifetime in the body by external means (e.g., gold doping) has little effect for small gate lengths. In addition the model can also predict the temperature dependence of the holding voltage.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124545172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145760
F. Brady, J. Chu, S.S. Li, W. Krull
Electrically active defects of the buried oxide in SIMOX (separation by implantation of oxygen) material have received relatively little attention. In an effort to gain further understanding of these defects, the authors investigated the effect of constant bias stressing on SIMOX buried oxides. The results show that damage from electron injection can be significant for electric fields of only 2 MV/cm. For low implant dose material, enhanced electron injection from the film/buried oxide interface is seen. For this material, there is also a net negative trapped charge and generation of interface traps at both buried oxide interfaces. For standard dose material, the net trapped charge is positive, and is only seen at the substrate/buried oxide interface.<>
{"title":"Low-field charge injection in SIMOX buried oxides","authors":"F. Brady, J. Chu, S.S. Li, W. Krull","doi":"10.1109/SOSSOI.1990.145760","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145760","url":null,"abstract":"Electrically active defects of the buried oxide in SIMOX (separation by implantation of oxygen) material have received relatively little attention. In an effort to gain further understanding of these defects, the authors investigated the effect of constant bias stressing on SIMOX buried oxides. The results show that damage from electron injection can be significant for electric fields of only 2 MV/cm. For low implant dose material, enhanced electron injection from the film/buried oxide interface is seen. For this material, there is also a net negative trapped charge and generation of interface traps at both buried oxide interfaces. For standard dose material, the net trapped charge is positive, and is only seen at the substrate/buried oxide interface.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114741133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145763
J. F. Conley, P. Lenahan, P. Roitman
Experimental evidence is presented that indicates that E' centers or E'-like centers play an important role in hole trapping in SIMOX (separation by implantation of oxygen) oxides. The E' center is a silicon atom back-bonded to three oxygen atoms; in thermally grown SiO/sub 2/ films on silicon it is the dominant deep hole trap and is almost certainly a hole trapped in an oxygen vacancy. The SIMOX samples used had buried oxides approximately 4000 AA thick. The trapping was explored using a combination of electron paramagnetic resonance (EPR) and vacuum ultraviolet (hc/ lambda =10.2 eV) and ultraviolet (hc/ lambda =5 eV) irradiation sequences.<>
{"title":"Direct experimental evidence for a dominant hole trapping center in SIMOX oxides","authors":"J. F. Conley, P. Lenahan, P. Roitman","doi":"10.1109/SOSSOI.1990.145763","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145763","url":null,"abstract":"Experimental evidence is presented that indicates that E' centers or E'-like centers play an important role in hole trapping in SIMOX (separation by implantation of oxygen) oxides. The E' center is a silicon atom back-bonded to three oxygen atoms; in thermally grown SiO/sub 2/ films on silicon it is the dominant deep hole trap and is almost certainly a hole trapped in an oxygen vacancy. The SIMOX samples used had buried oxides approximately 4000 AA thick. The trapping was explored using a combination of electron paramagnetic resonance (EPR) and vacuum ultraviolet (hc/ lambda =10.2 eV) and ultraviolet (hc/ lambda =5 eV) irradiation sequences.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145733
L. Lauwers, K. De Meyer
An accurate circuit-simulation-level mobility model for fully depleted SOI MOS devices is presented. It forms a solid basis for further optimization of specific thin-film properties. It is based on a local semiempirical carrier mobility model. The model can include all possible scattering mechanisms. It can also be used for low temperature ranges, where Coulomb scattering is dominant. A satisfactory and well-proved polynomial approximation allows an implementation of the local character of the carrier mobility model in a circuit simulation model. With a hyperbolical tangent dependence of the threshold voltage on the back gate voltage, the basis is formed for an accurate model for thin-film SOI devices.<>
{"title":"Incorporation of an engineering mobility model in an accurate analytical I-V description for SOI devices","authors":"L. Lauwers, K. De Meyer","doi":"10.1109/SOSSOI.1990.145733","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145733","url":null,"abstract":"An accurate circuit-simulation-level mobility model for fully depleted SOI MOS devices is presented. It forms a solid basis for further optimization of specific thin-film properties. It is based on a local semiempirical carrier mobility model. The model can include all possible scattering mechanisms. It can also be used for low temperature ranges, where Coulomb scattering is dominant. A satisfactory and well-proved polynomial approximation allows an implementation of the local character of the carrier mobility model in a circuit simulation model. With a hyperbolical tangent dependence of the threshold voltage on the back gate voltage, the basis is formed for an accurate model for thin-film SOI devices.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"315 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116601993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145737
M. Haond
Silicon-on-insulator (SOI) technology has been the subject of intensive work, mainly because of the advantages related to its intrinsic isolation properties. This avoids such drastic problems as latchup, encountered in bulk submicron CMOS processes. A lateral isolation is however necessary for the separation of the different transistors. Two main approaches can be considered: field oxidation (LOCOS) or field silicon etching (mesa). The author presents a review of the advantages and problems related to these techniques for an application to a VLSI CMOS process.<>
{"title":"Lateral isolation in SOI CMOS technology","authors":"M. Haond","doi":"10.1109/SOSSOI.1990.145737","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145737","url":null,"abstract":"Silicon-on-insulator (SOI) technology has been the subject of intensive work, mainly because of the advantages related to its intrinsic isolation properties. This avoids such drastic problems as latchup, encountered in bulk submicron CMOS processes. A lateral isolation is however necessary for the separation of the different transistors. Two main approaches can be considered: field oxidation (LOCOS) or field silicon etching (mesa). The author presents a review of the advantages and problems related to these techniques for an application to a VLSI CMOS process.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117019052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145719
L. L. Augenstein
Linewidth control of printed patterns on thin film on silicon-on-insulator wafers is addressed. Investigations were conducted to understand how variations in the buried oxide layer and the ultrathin Si layer affect linewidth control during printing and measurement operations. The photolithography characteristics were studied, including both printed lines and printed spaces, at a number of process steps. SIMOX wafers and bulk Si wafers exposed with focus/exposure matrices, exposure matrices (fixed focus), and fixed focus/exposure were studied using Hg G line (436-nm) exposure wavelength. Linewidths ranged from 1 to 2.5 mu m. Linewidths were measured using a scanning electron microscope and a confocal scanning laser microscope.<>
{"title":"Photolithographic linewidth control considerations on ultrathin fully depleted SOI devices","authors":"L. L. Augenstein","doi":"10.1109/SOSSOI.1990.145719","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145719","url":null,"abstract":"Linewidth control of printed patterns on thin film on silicon-on-insulator wafers is addressed. Investigations were conducted to understand how variations in the buried oxide layer and the ultrathin Si layer affect linewidth control during printing and measurement operations. The photolithography characteristics were studied, including both printed lines and printed spaces, at a number of process steps. SIMOX wafers and bulk Si wafers exposed with focus/exposure matrices, exposure matrices (fixed focus), and fixed focus/exposure were studied using Hg G line (436-nm) exposure wavelength. Linewidths ranged from 1 to 2.5 mu m. Linewidths were measured using a scanning electron microscope and a confocal scanning laser microscope.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145717
S. Bengtsson, O. Engstrom
It is found that Si/Si and Si/SiO/sub 2/ interfaces exhibit different interface charge properties when bonded at comparable temperatures and surface treatments. Thermally grown oxides were bonded to bare silicon surfaces and the bonded Si/SiO/sub 2/ interface was investigated on MOS-structures by the C-V technique. Interfaces prepared at temperatures in the range 900-1100 degrees c exhibited U-shaped interface state densities. Si/Si samples were prepared using a hydrophilizing surface treatment before wafer bonding. At the same annealing temperatures, the interface state densities of the bonded Si/Si interfaces were in the range 10/sup 11/-10/sup 13/ cm/sup -2/ eV/sup -1/. Si/Si interfaces are found to be very sensitive to prebond chemical treatment, while Si/SiO/sub 2/ interfaces are not. Native oxides at bonded silicon interfaces have a more pronounced influence on Si/Si interfaces than on Si/SiO/sub 2/ interfaces.<>
{"title":"Charge densities at silicon interfaces prepared by wafer bonding","authors":"S. Bengtsson, O. Engstrom","doi":"10.1109/SOSSOI.1990.145717","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145717","url":null,"abstract":"It is found that Si/Si and Si/SiO/sub 2/ interfaces exhibit different interface charge properties when bonded at comparable temperatures and surface treatments. Thermally grown oxides were bonded to bare silicon surfaces and the bonded Si/SiO/sub 2/ interface was investigated on MOS-structures by the C-V technique. Interfaces prepared at temperatures in the range 900-1100 degrees c exhibited U-shaped interface state densities. Si/Si samples were prepared using a hydrophilizing surface treatment before wafer bonding. At the same annealing temperatures, the interface state densities of the bonded Si/Si interfaces were in the range 10/sup 11/-10/sup 13/ cm/sup -2/ eV/sup -1/. Si/Si interfaces are found to be very sensitive to prebond chemical treatment, while Si/SiO/sub 2/ interfaces are not. Native oxides at bonded silicon interfaces have a more pronounced influence on Si/Si interfaces than on Si/SiO/sub 2/ interfaces.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129992071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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