Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145739
P. Pronko, A. McCormick, W. Maszara
The use of keV ion implantation of boron for the bond and etch-back SOI (BESOI) technique is addressed. Ion implantation of boron at 2.5 MeV was used in order to place the boron peak and residual tail of the boron distribution deep enough, so that a region of the original silicon material with acceptably low boron concentration persists near the active-layer-SiO/sub 2/ interface. The objective was to determine whether improvements in final uniformity were possible using the MeV implants compared to the more conventional epi-layer technique. Results show that a final thickness of 0.3 mu m of single crystal silicon on insulator can be produced with thickness nonuniformity of 28 to 30 nm averaged over 9 points on a 2"*2" area. The final oxidation-stripping steps contributed to most of this nonuniformity. Additional difficulties arose as a result of the extensive oxidation stripping used in the terminal processing steps. Etch pit analysis of the final material revealed substantial oxidation induced stacking faults in the finished material ( approximately 300 cm/sup -2/, average length approximately 50 mu m).<>
{"title":"Epi-less bond etch SOI using MeV ion implantation","authors":"P. Pronko, A. McCormick, W. Maszara","doi":"10.1109/SOSSOI.1990.145739","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145739","url":null,"abstract":"The use of keV ion implantation of boron for the bond and etch-back SOI (BESOI) technique is addressed. Ion implantation of boron at 2.5 MeV was used in order to place the boron peak and residual tail of the boron distribution deep enough, so that a region of the original silicon material with acceptably low boron concentration persists near the active-layer-SiO/sub 2/ interface. The objective was to determine whether improvements in final uniformity were possible using the MeV implants compared to the more conventional epi-layer technique. Results show that a final thickness of 0.3 mu m of single crystal silicon on insulator can be produced with thickness nonuniformity of 28 to 30 nm averaged over 9 points on a 2\"*2\" area. The final oxidation-stripping steps contributed to most of this nonuniformity. Additional difficulties arose as a result of the extensive oxidation stripping used in the terminal processing steps. Etch pit analysis of the final material revealed substantial oxidation induced stacking faults in the finished material ( approximately 300 cm/sup -2/, average length approximately 50 mu m).<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145745
K. Yallup, B. Lane, S. Edwwards
The implementaton is discussed of a bulk BIMOS process which incorporates vertical bipolar devices on a thick (5 mu m) film silicon-on-insulator (SOI) substrate. When trench isolation is incorporated in such a process, fully dielectrically isolated devices can be fabricated. By appropriate application of the trench technology, no change in the electrical device parameters will be produced by such processing. It has been demonstrated that epitaxially thickened ZMR (zone-melting recrystallization) and SIMOX (separation by implantation of oxygen) substrates can support a wide range of devices such as those found in the BIMOS process. However, for device structures in which electrical parameters are sensitive to the diffusion of dopants in silicon it may be necessary to adjust the process to allow for small changes in diffusivity in SOI material. This has been demonstrated in the case of oxidation enhanced diffusion.<>
{"title":"Novel diffusion effects in a dielectrically isolated BIMOS process using SOI substrates","authors":"K. Yallup, B. Lane, S. Edwwards","doi":"10.1109/SOSSOI.1990.145745","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145745","url":null,"abstract":"The implementaton is discussed of a bulk BIMOS process which incorporates vertical bipolar devices on a thick (5 mu m) film silicon-on-insulator (SOI) substrate. When trench isolation is incorporated in such a process, fully dielectrically isolated devices can be fabricated. By appropriate application of the trench technology, no change in the electrical device parameters will be produced by such processing. It has been demonstrated that epitaxially thickened ZMR (zone-melting recrystallization) and SIMOX (separation by implantation of oxygen) substrates can support a wide range of devices such as those found in the BIMOS process. However, for device structures in which electrical parameters are sensitive to the diffusion of dopants in silicon it may be necessary to adjust the process to allow for small changes in diffusivity in SOI material. This has been demonstrated in the case of oxidation enhanced diffusion.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145769
L. Koczela
Development of an advanced processor, the RI 1750AB, that utilizes the benefits of the 3 mu m CMOS/SOS technology and is intended for strategic-level radiation-hard guidance computers is reported. The RI 1750AB contains many special features enhancing its use in a real-time-control/radiation-tolerant system. These include trap and patch registers which allow changes in ROM memory in the field without having to replace the ROM chips. For most applications the CPU will operate through, in the true sense, without radiation upset. However, where extremely high transient levels may be encountered, the CPU supports both software and hardware circumvention. The CPU has an optional snapshot mode of operation which allows hardware-controlled, instead of software-controlled, program restart after radiation upset. To support circumvention, the CPU has several control lines that enable it to distinguish between a power turn-on and a radiation restart.<>
先进处理器RI 1750AB的开发利用了3 μ m CMOS/SOS技术的优势，旨在用于战略级辐射硬制导计算机。RI 1750AB包含许多特殊功能，增强了其在实时控制/耐辐射系统中的使用。这些寄存器包括陷阱寄存器和补丁寄存器，它们允许在不更换ROM芯片的情况下在现场更改ROM存储器。对于大多数应用程序，CPU将运行，在真正意义上，没有辐射干扰。然而，在可能遇到极高的瞬态电平时，CPU支持软件和硬件规避。CPU有一个可选的快照操作模式，允许硬件控制，而不是软件控制，程序重启后，辐射破坏。为了支持规避，CPU有几条控制线，使其能够区分电源打开和辐射重启
{"title":"Advanced CMOS/SOS LSI rad hard 1750 A/B processor","authors":"L. Koczela","doi":"10.1109/SOSSOI.1990.145769","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145769","url":null,"abstract":"Development of an advanced processor, the RI 1750AB, that utilizes the benefits of the 3 mu m CMOS/SOS technology and is intended for strategic-level radiation-hard guidance computers is reported. The RI 1750AB contains many special features enhancing its use in a real-time-control/radiation-tolerant system. These include trap and patch registers which allow changes in ROM memory in the field without having to replace the ROM chips. For most applications the CPU will operate through, in the true sense, without radiation upset. However, where extremely high transient levels may be encountered, the CPU supports both software and hardware circumvention. The CPU has an optional snapshot mode of operation which allows hardware-controlled, instead of software-controlled, program restart after radiation upset. To support circumvention, the CPU has several control lines that enable it to distinguish between a power turn-on and a radiation restart.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145716
G. Campisi, D. Ma, S. B. Quadri, M. Peckerar
An examination of the surface silicon layer of SOI substrates was made using X-ray double crystal rocking curve (XDCRC) and reflection topographic analysis (XRT). The original intent was to examine dislocations in SOI substrates-SIMOX, and BESOI (bond and etchback silicon-on-insulator). The properties of the superficial or surface silicon layer were characterized with reflection topography for the three SOI technologies, and these results were correlated with crystal quality measured by XDCRC. Reflection topography did not reveal surface imperfection, defects, or dislocations in SIMOX or BESOI, but XRT revealed the transmission of substrate strain or warpage into the surface silicon layer for all SOI samples. Rocking curves confirmed the high quality of the surface silicon layer.<>
{"title":"X-ray characterization of silicon on insulator substrates","authors":"G. Campisi, D. Ma, S. B. Quadri, M. Peckerar","doi":"10.1109/SOSSOI.1990.145716","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145716","url":null,"abstract":"An examination of the surface silicon layer of SOI substrates was made using X-ray double crystal rocking curve (XDCRC) and reflection topographic analysis (XRT). The original intent was to examine dislocations in SOI substrates-SIMOX, and BESOI (bond and etchback silicon-on-insulator). The properties of the superficial or surface silicon layer were characterized with reflection topography for the three SOI technologies, and these results were correlated with crystal quality measured by XDCRC. Reflection topography did not reveal surface imperfection, defects, or dislocations in SIMOX or BESOI, but XRT revealed the transmission of substrate strain or warpage into the surface silicon layer for all SOI samples. Rocking curves confirmed the high quality of the surface silicon layer.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145752
R. Hillard, J. Heddleson, P. Rai-Choudhury, P. Karulkar
The buried oxide in SOI structures influences the electrical parameters, reliability, and the radiation hardness of devices fabricated in the superficial silicon film. Hence, along with advances in SOI (silicon-on-insulator) wafer fabrication, characterization of the buried oxide is an important aspect of SOI technology development. The authors' earlier work demonstrated the superior static and time dependent breakdown properties of multiple implant SIMOX (separation by implantation of oxygen) buried oxide as compared to single implant buried oxide. The previous work used novel kinematic pressure contacts placed directly on the oxide. Experiments to further characterize the charge trapping behavior of SIMOX buried oxides using C-V and I-V measurements are reported. Deposited metal contacts were used for the C-V measurements, and pressure contacts were used for the I-V measurements.<>
{"title":"Charge trapping in single and multiple implant SIMOX buried oxides","authors":"R. Hillard, J. Heddleson, P. Rai-Choudhury, P. Karulkar","doi":"10.1109/SOSSOI.1990.145752","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145752","url":null,"abstract":"The buried oxide in SOI structures influences the electrical parameters, reliability, and the radiation hardness of devices fabricated in the superficial silicon film. Hence, along with advances in SOI (silicon-on-insulator) wafer fabrication, characterization of the buried oxide is an important aspect of SOI technology development. The authors' earlier work demonstrated the superior static and time dependent breakdown properties of multiple implant SIMOX (separation by implantation of oxygen) buried oxide as compared to single implant buried oxide. The previous work used novel kinematic pressure contacts placed directly on the oxide. Experiments to further characterize the charge trapping behavior of SIMOX buried oxides using C-V and I-V measurements are reported. Deposited metal contacts were used for the C-V measurements, and pressure contacts were used for the I-V measurements.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128755836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145709
N. Annamalai, J. Chapski
Two novel dielectrics for SOI structures are proposed. They are diamond and silicon carbide, replacing the silicon dioxide dielectric currently used in SOI structures. The authors report on some preliminary results of fabrication of buried diamond silicon-on-insulator structures by the zone melting recrystallization technique. Diamond grown by CVD (chemical vapor deposition) on silicon is chosen as the substrate. The CVD diamond film was grown on a 3" silicon wafer. A Raman spectrum peak was seen at 1334-35 cm/sup -1/, indicating that the film is diamond. Crystal size and growth characteristics were studied using high frequency capacitance and leakage current through the diamond film.<>
{"title":"Novel dielectrics for SOI structures","authors":"N. Annamalai, J. Chapski","doi":"10.1109/SOSSOI.1990.145709","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145709","url":null,"abstract":"Two novel dielectrics for SOI structures are proposed. They are diamond and silicon carbide, replacing the silicon dioxide dielectric currently used in SOI structures. The authors report on some preliminary results of fabrication of buried diamond silicon-on-insulator structures by the zone melting recrystallization technique. Diamond grown by CVD (chemical vapor deposition) on silicon is chosen as the substrate. The CVD diamond film was grown on a 3\" silicon wafer. A Raman spectrum peak was seen at 1334-35 cm/sup -1/, indicating that the film is diamond. Crystal size and growth characteristics were studied using high frequency capacitance and leakage current through the diamond film.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129042942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145708
D. L. Leung, J. Knudsen, D. Swanson, B. Hill, D. Mayer
The effect of process parameters on the quality of recrystallized material using rapid thermal processing (RTP) was evaluated. Both X-ray rocking curve and Read camera analysis were used to verify the crystalline quality of the regrown material. It is shown that RTP is a viable method for agglomerating the interfacial oxide at a silicon/polysilicon boundary before epitaxial growth. The material quality was observed to improve with increasing RTP time and temperature cycles. The optimum thermal anneal cycle was 600 degrees C for 18 h and 800 degrees C for 3 h. The improvement in the number of defects over the previously used ion implantation process is about two orders of magnitude.<>
{"title":"Native silicon oxide agglomeration prior to solid-phase epitaxy using rapid thermal processing","authors":"D. L. Leung, J. Knudsen, D. Swanson, B. Hill, D. Mayer","doi":"10.1109/SOSSOI.1990.145708","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145708","url":null,"abstract":"The effect of process parameters on the quality of recrystallized material using rapid thermal processing (RTP) was evaluated. Both X-ray rocking curve and Read camera analysis were used to verify the crystalline quality of the regrown material. It is shown that RTP is a viable method for agglomerating the interfacial oxide at a silicon/polysilicon boundary before epitaxial growth. The material quality was observed to improve with increasing RTP time and temperature cycles. The optimum thermal anneal cycle was 600 degrees C for 18 h and 800 degrees C for 3 h. The improvement in the number of defects over the previously used ion implantation process is about two orders of magnitude.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132509272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145702
J. Lamure, B. Biasse, C. Jaussaud, A. Papon, J. Michaud, F. Gusella, C. Pudda, A. Cartier, A. Soubie, J. Margail
A 150 m/sup 2/ class 100 clean room, specially dedicated for separation by implantation of oxygen (SIMOX) wafer production on a semi-industrial basis, has been set up at LETI. This facility includes a very high current oxygen ion implantation machine (Eaton NV-200), a high temperature annealing furnace (temperature up to 1350 degrees C, six inches capability), and nondestructive characterization tools. The characterization techniques include IR absorption, nuclear reaction analysis, and spectral reflectivity analysis that allows automatic measurement of silicon thickness down to 100 nm. Contamination levels are routinely checked by SIMS (secondary ion mass spectrometry) and the structure and crystalline quality are monitored using TEM and XTEM analysis. Different methods for producing thin silicon film SIMOX wafers-sacrificial oxidation, implantation through oxide, and reduction of the implantation energy-are briefly outlined.<>
LETI已经建立了一个150m /sup / 2/ class 100的洁净室，专门用于半工业基础上的氧注入分离(SIMOX)晶圆生产。该设施包括一个非常高电流的氧离子注入机(Eaton NV-200)，一个高温退火炉(温度高达1350摄氏度，6英寸容量)，和非破坏性表征工具。表征技术包括红外吸收，核反应分析和光谱反射率分析，可自动测量硅厚度至100 nm。通过SIMS(二次离子质谱法)常规检查污染水平，并使用TEM和XTEM分析监测结构和晶体质量。简述了硅薄膜SIMOX晶圆的不同制备方法:牺牲氧化法、氧化注入法和降低注入能量法。
{"title":"SIMOX material: from research to production","authors":"J. Lamure, B. Biasse, C. Jaussaud, A. Papon, J. Michaud, F. Gusella, C. Pudda, A. Cartier, A. Soubie, J. Margail","doi":"10.1109/SOSSOI.1990.145702","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145702","url":null,"abstract":"A 150 m/sup 2/ class 100 clean room, specially dedicated for separation by implantation of oxygen (SIMOX) wafer production on a semi-industrial basis, has been set up at LETI. This facility includes a very high current oxygen ion implantation machine (Eaton NV-200), a high temperature annealing furnace (temperature up to 1350 degrees C, six inches capability), and nondestructive characterization tools. The characterization techniques include IR absorption, nuclear reaction analysis, and spectral reflectivity analysis that allows automatic measurement of silicon thickness down to 100 nm. Contamination levels are routinely checked by SIMS (secondary ion mass spectrometry) and the structure and crystalline quality are monitored using TEM and XTEM analysis. Different methods for producing thin silicon film SIMOX wafers-sacrificial oxidation, implantation through oxide, and reduction of the implantation energy-are briefly outlined.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115924031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145751
L. Mcdaid, S. Hall, W. Eccleston, P. Watkinson, J. Alderman
It is demonstrated that a significant improvement in the breakdown voltage of an SOI (silicon-on-insulator) MOSFET can be achieved by stress-induced damage to the source/body junction. The damage serves to degrade the injection efficiency of this junction and thus suppresses the parasitic lateral bipolar associated with source/body/drain. The experiment indicates the usefulness of source engineering to the latch problem.<>
{"title":"The influence of emitter efficiency on single transistor latch in silicon-on-insulator MOSFETs","authors":"L. Mcdaid, S. Hall, W. Eccleston, P. Watkinson, J. Alderman","doi":"10.1109/SOSSOI.1990.145751","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145751","url":null,"abstract":"It is demonstrated that a significant improvement in the breakdown voltage of an SOI (silicon-on-insulator) MOSFET can be achieved by stress-induced damage to the source/body junction. The damage serves to degrade the injection efficiency of this junction and thus suppresses the parasitic lateral bipolar associated with source/body/drain. The experiment indicates the usefulness of source engineering to the latch problem.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114664148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145735
A. Ipri, G. Dolny, S. Policastro, R. Stewart, D. Peters
The authors discuss the electrical characteristics of thin film polycrystalline silicon transistors and their various uses. The first major application of polysilicon transistors was in the fabrication of active matrix liquid crystal displays. Over 40000 devices are fabricated on a four inch glass wafer and are used to make write only dynamic memory type full wafer arrays. The second major application of polysilicon transistors is as a replacement for the polysilicon load resistor in static memories. Future applications include circuits where both bulk silicon transistors and low performance silicon-on-insulator polysilicon transistors are used in the same integrated circuit. Typical of these applications are arrays where different substrate biases are needed and where junction isolation is insufficient for the application.<>
{"title":"Polycrystalline silicon thin-film CMOS technology: the poor man's SOI","authors":"A. Ipri, G. Dolny, S. Policastro, R. Stewart, D. Peters","doi":"10.1109/SOSSOI.1990.145735","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145735","url":null,"abstract":"The authors discuss the electrical characteristics of thin film polycrystalline silicon transistors and their various uses. The first major application of polysilicon transistors was in the fabrication of active matrix liquid crystal displays. Over 40000 devices are fabricated on a four inch glass wafer and are used to make write only dynamic memory type full wafer arrays. The second major application of polysilicon transistors is as a replacement for the polysilicon load resistor in static memories. Future applications include circuits where both bulk silicon transistors and low performance silicon-on-insulator polysilicon transistors are used in the same integrated circuit. Typical of these applications are arrays where different substrate biases are needed and where junction isolation is insufficient for the application.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124928565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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