Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145749
J. Colinge, M. Gao, A. Romano, H. Maes, C. Claeys
The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described.<>
{"title":"Silicon-on-insulator 'gate-all-around' MOS device","authors":"J. Colinge, M. Gao, A. Romano, H. Maes, C. Claeys","doi":"10.1109/SOSSOI.1990.145749","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145749","url":null,"abstract":"The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131490074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145734
J. B. Mckitterick
It is universally assumed that impact ionization has no noticeable effects in FETs at low drain voltages, e.g. 0.1 volts. It is pointed out that in SOI FETs without a body contact the effects of impact ionization, though somewhat subtle, are significant. Proper inclusion of impact ionization effects in modeling does not appear to affect the gross characteristics of the device, yet it has a profound impact on the correct interpretation of such derived quantities as lifetime.<>
{"title":"Impact ionization at low drain voltages in SOI FETs","authors":"J. B. Mckitterick","doi":"10.1109/SOSSOI.1990.145734","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145734","url":null,"abstract":"It is universally assumed that impact ionization has no noticeable effects in FETs at low drain voltages, e.g. 0.1 volts. It is pointed out that in SOI FETs without a body contact the effects of impact ionization, though somewhat subtle, are significant. Proper inclusion of impact ionization effects in modeling does not appear to affect the gross characteristics of the device, yet it has a profound impact on the correct interpretation of such derived quantities as lifetime.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145758
P. Roitman, M. Edelstein, S. Krause, S. Visitserngtrukul
Some techniques are discussed for monitoring dislocations and stacking faults in SIMOX (separation by implantation of oxygen) films. Also, a different type of defect, a silicon pipe running through the buried oxide, has been observed. The origin of these defects and a technique for detecting them are described.<>
{"title":"Residual defects in SIMOX: threading dislocations and pipes","authors":"P. Roitman, M. Edelstein, S. Krause, S. Visitserngtrukul","doi":"10.1109/SOSSOI.1990.145758","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145758","url":null,"abstract":"Some techniques are discussed for monitoring dislocations and stacking faults in SIMOX (separation by implantation of oxygen) films. Also, a different type of defect, a silicon pipe running through the buried oxide, has been observed. The origin of these defects and a technique for detecting them are described.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125018185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145766
S. Valeri, A. L. Robinson
A circuit is described that uses low-voltage transistors to form a high-voltage composite device. The circuit is a series string of SOI (silicon-on-insulator) MOSFETs and associated biasing elements fabricated using a modified nMOS process on a SIMOX (separation by implantation of oxygen) substrate. The circuit voltages higher than the breakdown voltage of a single transistor by dividing the applied voltage among the transistors in the string. MOSFET-like characteristics with breakdown voltage up to 60 V are demonstrated using a string of 25 SOI MOSFETs, each with a breakdown voltage of 6-7 V.<>
{"title":"A composite high-voltage device using low-voltage SOI MOSFETs","authors":"S. Valeri, A. L. Robinson","doi":"10.1109/SOSSOI.1990.145766","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145766","url":null,"abstract":"A circuit is described that uses low-voltage transistors to form a high-voltage composite device. The circuit is a series string of SOI (silicon-on-insulator) MOSFETs and associated biasing elements fabricated using a modified nMOS process on a SIMOX (separation by implantation of oxygen) substrate. The circuit voltages higher than the breakdown voltage of a single transistor by dividing the applied voltage among the transistors in the string. MOSFET-like characteristics with breakdown voltage up to 60 V are demonstrated using a string of 25 SOI MOSFETs, each with a breakdown voltage of 6-7 V.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128874186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145768
C. Yue, J. Kueng, P. Fechner, T. Randazzo
Direct correlation is reported between single-transistor back channel leakage and the anomalous increase in 16 K-SRAM standby current after total dose irradiation. 16 K-SRAMs fabricated on SIMOX (separation by implantation of oxygen) substrates were total-dose tested up to 10 Mrad (SiO/sub 2/) using an ARACOR X-ray source with zero substrate bias. Different bias conditions were examined to determine the worst case condition for the buried oxide. The worst bias condition for back channel buried oxide threshold voltage shift is when irradiated with zero substrate bias. The standby current hump of the 16 K-SRAM after total dose irradiation can be directly correlated with the NMOS transistor back channel leakage current. Reduction of standby current with increased total dose can be explained by the buildup of interface charge which reduces the back channel leakage.<>
{"title":"Bias dependence of buried oxide hardness during total dose irradiation","authors":"C. Yue, J. Kueng, P. Fechner, T. Randazzo","doi":"10.1109/SOSSOI.1990.145768","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145768","url":null,"abstract":"Direct correlation is reported between single-transistor back channel leakage and the anomalous increase in 16 K-SRAM standby current after total dose irradiation. 16 K-SRAMs fabricated on SIMOX (separation by implantation of oxygen) substrates were total-dose tested up to 10 Mrad (SiO/sub 2/) using an ARACOR X-ray source with zero substrate bias. Different bias conditions were examined to determine the worst case condition for the buried oxide. The worst bias condition for back channel buried oxide threshold voltage shift is when irradiated with zero substrate bias. The standby current hump of the 16 K-SRAM after total dose irradiation can be directly correlated with the NMOS transistor back channel leakage current. Reduction of standby current with increased total dose can be explained by the buildup of interface charge which reduces the back channel leakage.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127390668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145693
R. Rios, R. Smeltzer, R. Amantea, A. Rothwarf
The role of the edge parasitic transistor in the MOS-SOS (silicon-on-sapphire) device behavior is analyzed with a new 3-D device simulator. Radiation effects on the n-MOS device leakage are simulated by adding positive charge distributions at the back interface. It is shown that the radiation-induced leakage is very sensitive to the back interface charge density, which explains the large variations observed in practice. The 3-D simulations also demonstrate that the bottom corner of the edge transistor is the region where most of the radiation-induced leakage current flows.<>
{"title":"Analysis of radiation-induced leakage in MOS-SOS edge parasitic transistors using a 3-D device simulator","authors":"R. Rios, R. Smeltzer, R. Amantea, A. Rothwarf","doi":"10.1109/SOSSOI.1990.145693","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145693","url":null,"abstract":"The role of the edge parasitic transistor in the MOS-SOS (silicon-on-sapphire) device behavior is analyzed with a new 3-D device simulator. Radiation effects on the n-MOS device leakage are simulated by adding positive charge distributions at the back interface. It is shown that the radiation-induced leakage is very sensitive to the back interface charge density, which explains the large variations observed in practice. The 3-D simulations also demonstrate that the bottom corner of the edge transistor is the region where most of the radiation-induced leakage current flows.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145757
B. Biasse, J. Stehle
A nondestructive optical technique, spectroscopic ellipsometry (SE), used to control top SiO/sub 2/, silicon, and buried SiO/sub 2/ layer thicknesses, as well as interfaces of these layers during SIMOX (separation by implantation of oxygen) wafer fabrication, is addressed. New improvements on SE give the capability to measure a complete spectrum within 1 s without losing useful information. Using this technique, it is also possible to characterize the evolution of layer thicknesses when the dose of implantation is increased at a given energy. The microspot option reduces the beam size from 3*9 mm/sup 2/ down to 150*150 mu m/sup 2/.<>
{"title":"SIMOX layers and interfaces studies with a new fast multichannel spectroscopic ellipsometer","authors":"B. Biasse, J. Stehle","doi":"10.1109/SOSSOI.1990.145757","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145757","url":null,"abstract":"A nondestructive optical technique, spectroscopic ellipsometry (SE), used to control top SiO/sub 2/, silicon, and buried SiO/sub 2/ layer thicknesses, as well as interfaces of these layers during SIMOX (separation by implantation of oxygen) wafer fabrication, is addressed. New improvements on SE give the capability to measure a complete spectrum within 1 s without losing useful information. Using this technique, it is also possible to characterize the evolution of layer thicknesses when the dose of implantation is increased at a given energy. The microspot option reduces the beam size from 3*9 mm/sup 2/ down to 150*150 mu m/sup 2/.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129651339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145765
J. O'connor, V. Luciani, A. Caviglia
A 90 V, 1.3 A double-diffused MOS (DMOS) power FET fabricated on a 400 nm thick SOI (silicon-on-insulator) film is reported. By utilizing thin SOI materials, these devices can be easily integrated with analog and digital devices to form smart power monolithic circuits. The power devices can be isolated from each other and from the control circuitry by either etching or oxidizing (local oxidation of silicon) through the thin SOI layer, and both high and low side drivers can be combined on a single chip. The thin SOI layer virtually eliminates step coverage problems with interconnects and avoids complicated planarization schemes often needed for dielectrically isolated power devices.<>
{"title":"High voltage DMOS power FETs on thin SOI substrates","authors":"J. O'connor, V. Luciani, A. Caviglia","doi":"10.1109/SOSSOI.1990.145765","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145765","url":null,"abstract":"A 90 V, 1.3 A double-diffused MOS (DMOS) power FET fabricated on a 400 nm thick SOI (silicon-on-insulator) film is reported. By utilizing thin SOI materials, these devices can be easily integrated with analog and digital devices to form smart power monolithic circuits. The power devices can be isolated from each other and from the control circuitry by either etching or oxidizing (local oxidation of silicon) through the thin SOI layer, and both high and low side drivers can be combined on a single chip. The thin SOI layer virtually eliminates step coverage problems with interconnects and avoids complicated planarization schemes often needed for dielectrically isolated power devices.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOSSOI.1990.145746
M. Haond, O. Le Néel
Different isolation features have been proposed for silicon on insulator (SOI): LOCOS, mesa, and reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. The rounded edge mesa (REM) presented allows accurate control of the gate dimensions without shorts. A 0.8 mu m DLM CMOS process was run on ZMR (zone-melting recrystallization) SOI films thinned down to 150 nm. After the REM formation, the pad oxide is stripped and a 15 nm gate oxide is grown followed by a 380 nm N+-polysilicon film deposition. A classical gate etch is then applied. The absence of residues as studied by measuring the resistance of 22 mm long 0.8 mu m spaced 0.8 mu m wide interdigitated polysilicon fingers running on mesas. The absence of subthreshold leakage or bumps in the subthreshold slope confirms that this technique prevents the formation of sidewall parasitic channels.<>
{"title":"Rounded edge mesa for submicron SOI CMOS process","authors":"M. Haond, O. Le Néel","doi":"10.1109/SOSSOI.1990.145746","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145746","url":null,"abstract":"Different isolation features have been proposed for silicon on insulator (SOI): LOCOS, mesa, and reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. The rounded edge mesa (REM) presented allows accurate control of the gate dimensions without shorts. A 0.8 mu m DLM CMOS process was run on ZMR (zone-melting recrystallization) SOI films thinned down to 150 nm. After the REM formation, the pad oxide is stripped and a 15 nm gate oxide is grown followed by a 380 nm N+-polysilicon film deposition. A classical gate etch is then applied. The absence of residues as studied by measuring the resistance of 22 mm long 0.8 mu m spaced 0.8 mu m wide interdigitated polysilicon fingers running on mesas. The absence of subthreshold leakage or bumps in the subthreshold slope confirms that this technique prevents the formation of sidewall parasitic channels.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121343073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOSSOI.1990.145741
E. Cortesi, F. Namavar, N. Kalkhoran, J. Manke, B. Buchanan
Improvement of the crystalline quality of epitaxial silicon grown on separation by implantation of oxygen (SIMOX) material was investigated by confining the threading dislocations in the silicon top layer with a GeSi strained layer. The standard SIMOX used was produced by implantation of 1.6*10/sup 18/ O+/cm/sup 2/ at 160 keV, followed by annealing for 6 h at 1300 degrees C in N/sub 2/. Thin Si/GeSi/Si epitaxial structures were grown on the SIMOX and on Si substrates by chemical vapor deposition (CVD). The material was evaluated using a variety of methods, including cross-sectional transmission electron microscopy (XTEM), plane view TEM, and Rutherford backscattering spectroscopy (RBS)/channeling. The GeSi strained layer grown by CVD appears to be high quality, and no misfit dislocations were observed for Si/GeSi/Si structures grown at the same time on bulk silicon. CVD may also be a simple and economical method for growing Si/GeSi/Si structures for device applications such as heterojunction bipolar transistors.<>
{"title":"Epitaxial GeSi strained layer on SIMOX for confinement of threading dislocations","authors":"E. Cortesi, F. Namavar, N. Kalkhoran, J. Manke, B. Buchanan","doi":"10.1109/SOSSOI.1990.145741","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145741","url":null,"abstract":"Improvement of the crystalline quality of epitaxial silicon grown on separation by implantation of oxygen (SIMOX) material was investigated by confining the threading dislocations in the silicon top layer with a GeSi strained layer. The standard SIMOX used was produced by implantation of 1.6*10/sup 18/ O+/cm/sup 2/ at 160 keV, followed by annealing for 6 h at 1300 degrees C in N/sub 2/. Thin Si/GeSi/Si epitaxial structures were grown on the SIMOX and on Si substrates by chemical vapor deposition (CVD). The material was evaluated using a variety of methods, including cross-sectional transmission electron microscopy (XTEM), plane view TEM, and Rutherford backscattering spectroscopy (RBS)/channeling. The GeSi strained layer grown by CVD appears to be high quality, and no misfit dislocations were observed for Si/GeSi/Si structures grown at the same time on bulk silicon. CVD may also be a simple and economical method for growing Si/GeSi/Si structures for device applications such as heterojunction bipolar transistors.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130978178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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