Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145761
P. Hurley, S. Hall, W. Eccleston, J. Alderman
In thin-film SOI (silicon-on-insulator) devices, where the body is fully depleted in normal device operation, the buried insulator has a pronounced effect on the transistor characteristics. In particular, the presence of fixed oxide charge and interface states at the body/insulator and the substrate/insulator interfaces influences the electrostatics in the body region. Consequently, it is necessary to have a simple method for determining the density of fixed charge at the interfaces. Moreover, from the viewpoint of long term device stability it is necessary to assess how the magnitude of the fixed charge varies under the influence of electric field stress. Previous work has demonstrated how the high-frequency capacitance/voltage plot can be used to determine the thickness of the body and buried oxide regions of SOI capacitors. The authors extend the technique to allow the determination of the fixed charge densities at both silicon/oxide interfaces, and they outline how the effects of high field stress can be interpreted.<>
{"title":"The effect of high field stress on the capacitance/voltage characteristics of buried insulators formed by oxygen implantation","authors":"P. Hurley, S. Hall, W. Eccleston, J. Alderman","doi":"10.1109/SOSSOI.1990.145761","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145761","url":null,"abstract":"In thin-film SOI (silicon-on-insulator) devices, where the body is fully depleted in normal device operation, the buried insulator has a pronounced effect on the transistor characteristics. In particular, the presence of fixed oxide charge and interface states at the body/insulator and the substrate/insulator interfaces influences the electrostatics in the body region. Consequently, it is necessary to have a simple method for determining the density of fixed charge at the interfaces. Moreover, from the viewpoint of long term device stability it is necessary to assess how the magnitude of the fixed charge varies under the influence of electric field stress. Previous work has demonstrated how the high-frequency capacitance/voltage plot can be used to determine the thickness of the body and buried oxide regions of SOI capacitors. The authors extend the technique to allow the determination of the fixed charge densities at both silicon/oxide interfaces, and they outline how the effects of high field stress can be interpreted.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114792135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145743
M. Landstrass
Total dose radiation hardness measurements were performed on SOI (silicon-on-insulator) test structures where the insulator was chemical vapor deposited (CVD) diamond in order to look at the fundamental radiation response of low-pressure CVD synthetic diamond materials for SOI applications. Silicon/diamond metal insulator semiconductor (MIS) capacitors were subjected to both cobalt-60 and 10 keV X-ray irradiation up to doses of 1*10/sup 7/ rad(SiO/sub 2/) while under positive, negative, and zero bias conditions. One-MHz capacitance-voltage (C-V) measurements were performed to monitor the device threshold and flatband voltage shifts. In order to evaluate any time-dependent bias-temperature instabilities, all devices, after irradiation, were baked at 150 degrees C with +5 V applied bias for five weeks. The measured results for flatband voltage shift versus time for 10 keV X-ray irradiation are presented. The diamond insulators used were free from extensive hole or electron trapping. This behavior is consistent with the high electron and hole mobility of the polycrystalline diamond insulator.<>
{"title":"Diamond based silicon-on-insulator structures","authors":"M. Landstrass","doi":"10.1109/SOSSOI.1990.145743","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145743","url":null,"abstract":"Total dose radiation hardness measurements were performed on SOI (silicon-on-insulator) test structures where the insulator was chemical vapor deposited (CVD) diamond in order to look at the fundamental radiation response of low-pressure CVD synthetic diamond materials for SOI applications. Silicon/diamond metal insulator semiconductor (MIS) capacitors were subjected to both cobalt-60 and 10 keV X-ray irradiation up to doses of 1*10/sup 7/ rad(SiO/sub 2/) while under positive, negative, and zero bias conditions. One-MHz capacitance-voltage (C-V) measurements were performed to monitor the device threshold and flatband voltage shifts. In order to evaluate any time-dependent bias-temperature instabilities, all devices, after irradiation, were baked at 150 degrees C with +5 V applied bias for five weeks. The measured results for flatband voltage shift versus time for 10 keV X-ray irradiation are presented. The diamond insulators used were free from extensive hole or electron trapping. This behavior is consistent with the high electron and hole mobility of the polycrystalline diamond insulator.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145718
R. Gallegos, M. Sullivan
Self-aligned silicide (salicide) is necessary to reduce device resistances associated with an ultra-thin film fully-depleted (UTF/FD) CMOS SOI technology. A salicide process for use with UTF/FD CMOS SOI devices is developed, and subsequent transistor characteristics are shown. Process optimization was achieved through experimental design techniques by minimizing salicide sheet resistance and improving salicide uniformity across the wafer. Replicates at the center points of the experimental designs determined the repeatability of the process and the ability of the models to predict responses. The salicide process developed for SOI is a four-step procedure: (1) Ti deposition (500 AA), (2) monosilicide formation (600-700 degrees C), (3) TiN/Ti removal (1:1 NH/sub 4/OH:H/sub 2/O/sub 2/), and (4) disilicide formation (700-800 degrees C).<>
{"title":"Salicide technology for fully-depleted SOI CMOS devices","authors":"R. Gallegos, M. Sullivan","doi":"10.1109/SOSSOI.1990.145718","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145718","url":null,"abstract":"Self-aligned silicide (salicide) is necessary to reduce device resistances associated with an ultra-thin film fully-depleted (UTF/FD) CMOS SOI technology. A salicide process for use with UTF/FD CMOS SOI devices is developed, and subsequent transistor characteristics are shown. Process optimization was achieved through experimental design techniques by minimizing salicide sheet resistance and improving salicide uniformity across the wafer. Replicates at the center points of the experimental designs determined the repeatability of the process and the ability of the models to predict responses. The salicide process developed for SOI is a four-step procedure: (1) Ti deposition (500 AA), (2) monosilicide formation (600-700 degrees C), (3) TiN/Ti removal (1:1 NH/sub 4/OH:H/sub 2/O/sub 2/), and (4) disilicide formation (700-800 degrees C).<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145725
L. Mcdaid, S. Hall, W. Eccleston, J. Alderman
Capacitance-voltage (C-V) and capacitance-time (C-T) measurements used to yield valuable material parameters in thin-film silicon-on-insulator MOS capacitors are considered. The authors previously demonstrated (1989) that a two-terminal C-V can yield the thickness of the body (silicon overlayer) and the buried oxide. However, a more comprehensive assessment of SOI material necessitates the evaluation of the generation lifetime in the body region, as this quantity directly correlates with leakage current and is crucial in determining parasitic effects such as lateral bipolar action in SOI transistors. It is shown that the minority carrier generation lifetime can be obtained by monitoring the capacitance between the gate and substrate after the application of a step voltage.<>
{"title":"Determination of generation lifetime in silicon-on-insulator (SOI) substrates using a three-terminal capacitance-time response","authors":"L. Mcdaid, S. Hall, W. Eccleston, J. Alderman","doi":"10.1109/SOSSOI.1990.145725","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145725","url":null,"abstract":"Capacitance-voltage (C-V) and capacitance-time (C-T) measurements used to yield valuable material parameters in thin-film silicon-on-insulator MOS capacitors are considered. The authors previously demonstrated (1989) that a two-terminal C-V can yield the thickness of the body (silicon overlayer) and the buried oxide. However, a more comprehensive assessment of SOI material necessitates the evaluation of the generation lifetime in the body region, as this quantity directly correlates with leakage current and is crucial in determining parasitic effects such as lateral bipolar action in SOI transistors. It is shown that the minority carrier generation lifetime can be obtained by monitoring the capacitance between the gate and substrate after the application of a step voltage.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132634201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145689
J. Choi, J. Fossum
The floating-body bipolar junction transistor (BJT) effects in fully depleted 0.5- mu m n-channel SOI (silicon on insulator) MOSFETs are analyzed, based on two-dimensional device simulations and on device measurements. PISCES simulations of the BJT-induced breakdown and latch phenomena are done, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC-breakdown and latch mechanisms in the fully depleted SOI MOSFET to the actual BJT-induced problems in an operating SOI CMOS circuit. A comprehensive understanding of floating-body effects is attained.<>
基于二维器件仿真和器件测量，分析了浮体双极结晶体管(BJT)在满耗尽0.5 μ m n沟道SOI(绝缘体上硅)mosfet中的效应。对bjt引起的击穿和锁存现象进行了双鱼座模拟，并检查了参数依赖性，以便为优化设计提供物理见解。分析进一步将完全耗尽SOI MOSFET中的直流击穿和锁存机制与工作SOI CMOS电路中实际的bjt引起的问题联系起来。获得了对浮体效应的全面理解。
{"title":"Analysis and control of BJT latch in fully depleted floating-body submicron SOI MOSFETs","authors":"J. Choi, J. Fossum","doi":"10.1109/SOSSOI.1990.145689","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145689","url":null,"abstract":"The floating-body bipolar junction transistor (BJT) effects in fully depleted 0.5- mu m n-channel SOI (silicon on insulator) MOSFETs are analyzed, based on two-dimensional device simulations and on device measurements. PISCES simulations of the BJT-induced breakdown and latch phenomena are done, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC-breakdown and latch mechanisms in the fully depleted SOI MOSFET to the actual BJT-induced problems in an operating SOI CMOS circuit. A comprehensive understanding of floating-body effects is attained.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145742
S. Peterstrom
Germanium-implanted double solid phase epitaxial (DSPE) material was produced in 0.3- mu m intrinsic silicon on sapphire. First, 4*10/sup 14/ germanium ions/cm/sup 2/ were implanted at 320 keV in a nonaligned direction. This implantation amorphized the inner part of the silicon. The wafers were annealed at 550, 600, 700, 800, 900 or 1000 degrees C. Next, 8*10/sup 14/ germanium ions/cm/sup 2/ were implanted at 100 keV. The implantation formed a 100-nm thick amorphous layer beneath the surface. This layer was epitaxially regrown from the inner part of the silicon crystal during the second annealing treatment, which was made at the same temperature as the first one for each wafer. Only a low number of implantation-induced carriers were formed in germanium-implanted intrinsic silicon on sapphire. Another advantage of using germanium for the amorphization is that the implantation dose can be reduced by more than 50% compared with silicon ions.<>
{"title":"Double solid phase epitaxy of germanium implanted silicon on sapphire","authors":"S. Peterstrom","doi":"10.1109/SOSSOI.1990.145742","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145742","url":null,"abstract":"Germanium-implanted double solid phase epitaxial (DSPE) material was produced in 0.3- mu m intrinsic silicon on sapphire. First, 4*10/sup 14/ germanium ions/cm/sup 2/ were implanted at 320 keV in a nonaligned direction. This implantation amorphized the inner part of the silicon. The wafers were annealed at 550, 600, 700, 800, 900 or 1000 degrees C. Next, 8*10/sup 14/ germanium ions/cm/sup 2/ were implanted at 100 keV. The implantation formed a 100-nm thick amorphous layer beneath the surface. This layer was epitaxially regrown from the inner part of the silicon crystal during the second annealing treatment, which was made at the same temperature as the first one for each wafer. Only a low number of implantation-induced carriers were formed in germanium-implanted intrinsic silicon on sapphire. Another advantage of using germanium for the amorphization is that the implantation dose can be reduced by more than 50% compared with silicon ions.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116366706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145759
Santos Mayo, J. Lowney, Peter Roitman, Donald B. Novotny
Photoinduced transient spectroscopy (PITS) was used to measure the persistent photoconductive (PPC) response in film resistors fabricated on two different commercial n-type SIMOX (separation by implantation of oxygen) wafers. A broadband, single-shot, flashlamp-pumped dye-laser pulse was used to photoexcite interband electrons in the film, and the decay of the induced excess carrier population was measured at temperatures in the 60-220 K range. The post-illumination conductivity transients observed show PPC signals exhibiting a nonexponential character. They were recorded for periods of time up to 30 s at constant temperature. Presented are the excess conductivity in SIMOX film annealed in nitrogen at 1300 degrees C for 6 h and the hole-trap volume density at the conductive-film-buried-silicon interface.<>
{"title":"Persistent photoconductivity in SIMOX films","authors":"Santos Mayo, J. Lowney, Peter Roitman, Donald B. Novotny","doi":"10.1109/SOSSOI.1990.145759","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145759","url":null,"abstract":"Photoinduced transient spectroscopy (PITS) was used to measure the persistent photoconductive (PPC) response in film resistors fabricated on two different commercial n-type SIMOX (separation by implantation of oxygen) wafers. A broadband, single-shot, flashlamp-pumped dye-laser pulse was used to photoexcite interband electrons in the film, and the decay of the induced excess carrier population was measured at temperatures in the 60-220 K range. The post-illumination conductivity transients observed show PPC signals exhibiting a nonexponential character. They were recorded for periods of time up to 30 s at constant temperature. Presented are the excess conductivity in SIMOX film annealed in nitrogen at 1300 degrees C for 6 h and the hole-trap volume density at the conductive-film-buried-silicon interface.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"10 27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115193310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145731
H. Abel
A model for a thin-film SOI MOSFET which is valid in all regions of inversion is presented. It takes into account all conditions at the back surface of the silicon film, including inversion. To achieve an analytical expression for the inversion layer charge as a function of the front and back surface potentials, the contribution of the accumulation layer to the total charge is neglected. Two-dimensional simulation results show that the variations of the front and back surface potentials along the channel are nearly equal. This simplifies the integration of the inversion layer charge along the channel, resulting in explicit formulas for the drift and diffusion terms of the drain current in both channels. The SOI-MOSFET model offers all features known from the charge sheet model. Due to the accurate computation of the surface potentials and the inclusion of the leakage current at the back interface the model gives an improved description of the substrate bias influence on transistor operation.<>
{"title":"A general model of the thin-film SOI-MOSFET","authors":"H. Abel","doi":"10.1109/SOSSOI.1990.145731","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145731","url":null,"abstract":"A model for a thin-film SOI MOSFET which is valid in all regions of inversion is presented. It takes into account all conditions at the back surface of the silicon film, including inversion. To achieve an analytical expression for the inversion layer charge as a function of the front and back surface potentials, the contribution of the accumulation layer to the total charge is neglected. Two-dimensional simulation results show that the variations of the front and back surface potentials along the channel are nearly equal. This simplifies the integration of the inversion layer charge along the channel, resulting in explicit formulas for the drift and diffusion terms of the drain current in both channels. The SOI-MOSFET model offers all features known from the charge sheet model. Due to the accurate computation of the surface potentials and the inclusion of the leakage current at the back interface the model gives an improved description of the substrate bias influence on transistor operation.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145726
D. Ioannou, B. Mazhari, X. Zhong, S. Cristoloveanu, A. Caviglia
The physics of ultrathin, fully depleted SOI MOSFETs are studied to obtain more accurate device equations and models and a better understanding of the carrier generation properties. It is found that the surface potential at threshold varies with the backgate potential, rather than being constant, as is usually assumed. The linear transconductance is also a strong function of the back gate voltage. The expressions presented can be used to determine the optimum back gate bias for maximum transconductance and mobility. The dual-gate Zerbst-like method is adapted for the study of carrier generation properties. Suitable biasing is used to set up a conductive channel in one interface and a transient variation of the surface potential in the other. The steady-state regime is gradually reached by charge generation in the film volume, the interfaces, and the sidewalls, giving rise to drain current transients. The corresponding generation rates are obtained by measuring and correctly modeling these transients.<>
{"title":"Surface potential at threshold, transconductance, and carrier generation in thin SOI MOSFETs","authors":"D. Ioannou, B. Mazhari, X. Zhong, S. Cristoloveanu, A. Caviglia","doi":"10.1109/SOSSOI.1990.145726","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145726","url":null,"abstract":"The physics of ultrathin, fully depleted SOI MOSFETs are studied to obtain more accurate device equations and models and a better understanding of the carrier generation properties. It is found that the surface potential at threshold varies with the backgate potential, rather than being constant, as is usually assumed. The linear transconductance is also a strong function of the back gate voltage. The expressions presented can be used to determine the optimum back gate bias for maximum transconductance and mobility. The dual-gate Zerbst-like method is adapted for the study of carrier generation properties. Suitable biasing is used to set up a conductive channel in one interface and a transient variation of the surface potential in the other. The steady-state regime is gradually reached by charge generation in the film volume, the interfaces, and the sidewalls, giving rise to drain current transients. The corresponding generation rates are obtained by measuring and correctly modeling these transients.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126128524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145720
D. Shain, R. Badilo
BESOI (bond and etchback silicon-on-insulator) substrates were used to create a trench isolated SOI process. The SOI substrates reduce the substrate capacitance and achieve better decoupling between digital and analog portions of the circuits. Changes were made to the process to incorporate the SOI substrates, but overall the process complexity was reduced using these substrates. The BESOI substrates, with approximately 3 mu m of thinned p-type silicon on 1 mu m of buried oxide, were processed through buried layer, epi, and N+ deep collector processes. The trench silicon etch was masked with a sandwich of LTO, nitride, and pad oxide. A 5- mu m-deep silicon trench etch was done before the etch stops on the buried oxide. After a thin sacrificial oxide was grown on the trench side walls, the thin pad oxide was stripped with a buffered HF dip. The electrical characteristics of the material were excellent.<>
{"title":"A trench isolated SOI bipolar process","authors":"D. Shain, R. Badilo","doi":"10.1109/SOSSOI.1990.145720","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145720","url":null,"abstract":"BESOI (bond and etchback silicon-on-insulator) substrates were used to create a trench isolated SOI process. The SOI substrates reduce the substrate capacitance and achieve better decoupling between digital and analog portions of the circuits. Changes were made to the process to incorporate the SOI substrates, but overall the process complexity was reduced using these substrates. The BESOI substrates, with approximately 3 mu m of thinned p-type silicon on 1 mu m of buried oxide, were processed through buried layer, epi, and N+ deep collector processes. The trench silicon etch was masked with a sandwich of LTO, nitride, and pad oxide. A 5- mu m-deep silicon trench etch was done before the etch stops on the buried oxide. After a thin sacrificial oxide was grown on the trench side walls, the thin pad oxide was stripped with a buffered HF dip. The electrical characteristics of the material were excellent.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125321053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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