Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145753
C. Hunt, G. Rouse, C. Harendt, M. Green
A limiting issue in the application of the BESOI (bond and etchback silicon-on-insulator) technique to whole wafers is the final film thickness nonuniformity, which typically totals approximately 40 nm using the etchback techniques presented to date. Such variation makes BESOI impractical for thin-film SOI (e.g. >
{"title":"Highly selective etch stop by stress compensation for thin-film BESOI","authors":"C. Hunt, G. Rouse, C. Harendt, M. Green","doi":"10.1109/SOSSOI.1990.145753","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145753","url":null,"abstract":"A limiting issue in the application of the BESOI (bond and etchback silicon-on-insulator) technique to whole wafers is the final film thickness nonuniformity, which typically totals approximately 40 nm using the etchback techniques presented to date. Such variation makes BESOI impractical for thin-film SOI (e.g. <or=300 nm) and applications to fully depleted MOS. The etchback process is a major contributor to the final film thickness nonuniformity. The authors demonstrate a highly selective etch stop of 2*10/sup 20/ cm/sup -3/ boron concentration, stress compensated by introducing GE (a high atomic number species). The Si/sub 1-x-y/ Ge/sub x/B/sub gamma / etch stop is selective through the reduction of the passivation potential in KOH to a point where negligible etching occurs. The stress compensation gives the wafer surface an exact Si lattice constant. Epitaxial layers are grown over this etch stop without misfit dislocations.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145723
J. Wang, N. Kistler, J. Woo, C. Viswanathan, P. Vasudev
The low-field effective mobility was studied for partially depleted and fully depleted silicon-on-insulator MOSFETs at temperatures from 300 K to 77 K. The transistors used in the study were fabricated on SIMOX wafers with a film thickness of 1800 AA and a buried oxide thickness of 3500 AA. The partially depleted device shows a greater improvement at low temperature. The mobility in both thin-film devices is essentially independent of inversion charge density, indicating a weak dependence on perpendicular electric field.<>
{"title":"Low temperature effective channel mobility in fully depleted and partially depleted SOI MOSFETs","authors":"J. Wang, N. Kistler, J. Woo, C. Viswanathan, P. Vasudev","doi":"10.1109/SOSSOI.1990.145723","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145723","url":null,"abstract":"The low-field effective mobility was studied for partially depleted and fully depleted silicon-on-insulator MOSFETs at temperatures from 300 K to 77 K. The transistors used in the study were fabricated on SIMOX wafers with a film thickness of 1800 AA and a buried oxide thickness of 3500 AA. The partially depleted device shows a greater improvement at low temperature. The mobility in both thin-film devices is essentially independent of inversion charge density, indicating a weak dependence on perpendicular electric field.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131803700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145703
S. Krause, S. Visisterngtrakul, B.F. Cordts, P. Roitman
Silicon-on-insulator (SOI) material fabrication by oxygen implantation (SIMOX) is addressed. Formation and growth of the buried oxide, formation and evolution of oxygen bubbles in the top silicon layer, and precipitate evolution and elimination during ramping and annealing are considered. Recent work is summarized on the effects of processing conditions on oxide evolution. Specifically, effects of implantation conditions on buried oxide formation, effects of ramping conditions on oxygen bubble evolution and defect formation, and effects of annealing conditions on the structure of the buried oxide and its interfaces are discussed.<>
{"title":"Microstructural evolution of oxides during processing of oxygen implanted SOI material","authors":"S. Krause, S. Visisterngtrakul, B.F. Cordts, P. Roitman","doi":"10.1109/SOSSOI.1990.145703","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145703","url":null,"abstract":"Silicon-on-insulator (SOI) material fabrication by oxygen implantation (SIMOX) is addressed. Formation and growth of the buried oxide, formation and evolution of oxygen bubbles in the top silicon layer, and precipitate evolution and elimination during ramping and annealing are considered. Recent work is summarized on the effects of processing conditions on oxide evolution. Specifically, effects of implantation conditions on buried oxide formation, effects of ramping conditions on oxygen bubble evolution and defect formation, and effects of annealing conditions on the structure of the buried oxide and its interfaces are discussed.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145707
P. Mertens, H. Maes
The authors report on lamp heated ZMR (zone melting recrystallization) of two silicon layers, stacked on top of each other and separated by an oxide layer in between. A 1.5- mu m thermal oxide was grown on
{"title":"Stacked SOI layers obtained by zone melting recrystallization","authors":"P. Mertens, H. Maes","doi":"10.1109/SOSSOI.1990.145707","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145707","url":null,"abstract":"The authors report on lamp heated ZMR (zone melting recrystallization) of two silicon layers, stacked on top of each other and separated by an oxide layer in between. A 1.5- mu m thermal oxide was grown on","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129886982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145712
D. Vu, W. Henderson, P. Zavracky, N. Cheong
The authors measured recombination lifetime in SOI by using a depletion-mode MOSFET. The drain-source current transient of depletion-mode MOSFETs when a reversed step bias is applied to the gate is studied at elevated temperatures. A theoretical analysis is performed by considering the different generation processes as functions of temperature. At high temperature, the minority carriers required for the inversion charge come mainly from the quasi-neutral region beneath the depletion region and from the nearby Si film-buried oxide interface through a generation-diffusion process; generation from the depletion region is neglected as well as the generation from the front gate interface. This analysis leads to a determination of a function containing the drain-source current varying linearly with time.<>
{"title":"Recombination lifetime measurements in SOI materials using a depletion-mode MOSFET","authors":"D. Vu, W. Henderson, P. Zavracky, N. Cheong","doi":"10.1109/SOSSOI.1990.145712","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145712","url":null,"abstract":"The authors measured recombination lifetime in SOI by using a depletion-mode MOSFET. The drain-source current transient of depletion-mode MOSFETs when a reversed step bias is applied to the gate is studied at elevated temperatures. A theoretical analysis is performed by considering the different generation processes as functions of temperature. At high temperature, the minority carriers required for the inversion charge come mainly from the quasi-neutral region beneath the depletion region and from the nearby Si film-buried oxide interface through a generation-diffusion process; generation from the depletion region is neglected as well as the generation from the front gate interface. This analysis leads to a determination of a function containing the drain-source current varying linearly with time.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145762
A. Stesmans, A. Revesz, H. Hughes
Silicon-on-insulator (SOI) structures formed on
绝缘体上硅(SOI)结构形成于
{"title":"Influence of gamma irradiation on ESR active defects in SIMOX structures","authors":"A. Stesmans, A. Revesz, H. Hughes","doi":"10.1109/SOSSOI.1990.145762","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145762","url":null,"abstract":"Silicon-on-insulator (SOI) structures formed on","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145713
E. A. Johnson, A. Dudkin
An ongoing program to develop manufacturing technology which will improve the availability and reduce the cost of SIMOX wafers is reported. A major thrust of this program is the identification of characterization and measurement techniques for in-process monitoring of SIMOX wafers. An improved method is developed for using optical reflectance to measure oxygen concentration versus depth in as-implanted and as-annealed SIMOX wafers. This method improves the speed of the fitting calculation by more than a factor of 2000 while improving the accuracy by more than an order of magnitude.<>
{"title":"Improved speed and accuracy for optical reflectance profiling of SIMOX wafers","authors":"E. A. Johnson, A. Dudkin","doi":"10.1109/SOSSOI.1990.145713","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145713","url":null,"abstract":"An ongoing program to develop manufacturing technology which will improve the availability and reduce the cost of SIMOX wafers is reported. A major thrust of this program is the identification of characterization and measurement techniques for in-process monitoring of SIMOX wafers. An improved method is developed for using optical reflectance to measure oxygen concentration versus depth in as-implanted and as-annealed SIMOX wafers. This method improves the speed of the fitting calculation by more than a factor of 2000 while improving the accuracy by more than an order of magnitude.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132137392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145732
F. Balestra, M. Benachir, G. Ghibaudo, J. Brini
No reliable analytical model exists for the case of fully depleted thin film depletion-mode (DM) SOI MOSFETs. The coupling between the front and back interfaces is particularly important in the weak accumulation regime. The authors propose analytical models for fully depleted DM SOI MOSFETs, by taking into consideration all the parameters of the SOI structure. The case of two or three interfaces (with a Si substrate) can be modeled.<>
对于完全耗尽的薄膜耗尽型SOI mosfet，目前还没有可靠的分析模型。在弱堆积区，前后界面之间的耦合尤为重要。作者通过考虑SOI结构的所有参数，提出了完全耗尽DM SOI mosfet的分析模型。可以对两个或三个界面(带有Si衬底)进行建模。
{"title":"Modeling of thin film depletion-mode SOI MOSFETs","authors":"F. Balestra, M. Benachir, G. Ghibaudo, J. Brini","doi":"10.1109/SOSSOI.1990.145732","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145732","url":null,"abstract":"No reliable analytical model exists for the case of fully depleted thin film depletion-mode (DM) SOI MOSFETs. The coupling between the front and back interfaces is particularly important in the weak accumulation regime. The authors propose analytical models for fully depleted DM SOI MOSFETs, by taking into consideration all the parameters of the SOI structure. The case of two or three interfaces (with a Si substrate) can be modeled.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"44 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134029514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145690
Y. Yamaguchi, T. Iwamatsu, T. Nishimura, Y. Akasaka
A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operation due to a floating body structure. Latch-up phenomena in a unit NMOS diminishes the reliable operation of the CMOS circuit. The problem can be solved by lowering the drain electric field to reduce generated holes from impact ionization which reinforces parasitic bipolar operation. The authors studied the LDD (lightly doped drain) structure and an advanced gate overlapped LDD structure for device application of the thin-SOI/MOSFET under and beyond the half-micron regime.<>
{"title":"Consideration of the structure design for thin SOI/MOSFET under and beyond the half micron regime","authors":"Y. Yamaguchi, T. Iwamatsu, T. Nishimura, Y. Akasaka","doi":"10.1109/SOSSOI.1990.145690","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145690","url":null,"abstract":"A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operation due to a floating body structure. Latch-up phenomena in a unit NMOS diminishes the reliable operation of the CMOS circuit. The problem can be solved by lowering the drain electric field to reduce generated holes from impact ionization which reinforces parasitic bipolar operation. The authors studied the LDD (lightly doped drain) structure and an advanced gate overlapped LDD structure for device application of the thin-SOI/MOSFET under and beyond the half-micron regime.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145692
H. Belhaddad, R. Gaillard, G. Poirault, A. Poncet
Studies of single-particle ion effects in SOI (silicon-on-insulator) devices show that a new mechanism can contribute to soft error rates: the electron-hole pairs generated in the silicon substrate can charge the back Si-SiO/sub 2/-Si capacitor. An analysis with the 2-D device simulator JUPIN shows that the bulk Si substrate current contribution to the charging current is greater than the normal photocurrent created in the drain-body junction. This current is important in the inversion mode and is still present but reduced in the accumulation mode. An analytical model has been developed to relate the current characteristics to physical parameters of the SOI structure.<>
{"title":"Single event charge enhancement in SOI devices","authors":"H. Belhaddad, R. Gaillard, G. Poirault, A. Poncet","doi":"10.1109/SOSSOI.1990.145692","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145692","url":null,"abstract":"Studies of single-particle ion effects in SOI (silicon-on-insulator) devices show that a new mechanism can contribute to soft error rates: the electron-hole pairs generated in the silicon substrate can charge the back Si-SiO/sub 2/-Si capacitor. An analysis with the 2-D device simulator JUPIN shows that the bulk Si substrate current contribution to the charging current is greater than the normal photocurrent created in the drain-body junction. This current is important in the inversion mode and is still present but reduced in the accumulation mode. An analytical model has been developed to relate the current characteristics to physical parameters of the SOI structure.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127392560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：