Multiple bridging faults in monotone networks (networks with out negations) are investigated. Complete test sets of monotone networks for single and multiple bridging faults are constructed. It is shown that the test complexity of fanout free monotone networks for the class of multiple bridging faults has an upper bound that is seen to be linear in the number of network input lines. For monotone networks, the paper shows how to carry over Aker's method for generating universal test sets for stuck-at faults to the bridging faults as well.
{"title":"Multiple bridging faults in monotone networks","authors":"A. Vogel","doi":"10.1049/IJ-CDT:19780016","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780016","url":null,"abstract":"Multiple bridging faults in monotone networks (networks with out negations) are investigated. Complete test sets of monotone networks for single and multiple bridging faults are constructed. It is shown that the test complexity of fanout free monotone networks for the class of multiple bridging faults has an upper bound that is seen to be linear in the number of network input lines. For monotone networks, the paper shows how to carry over Aker's method for generating universal test sets for stuck-at faults to the bridging faults as well.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124440154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-05-01DOI: 10.1049/IJ-CDT.1978.0018
S. M. Boxer, B. Batchelor
A linear array of microprocessors provides a powerful computing system that is particularly well suited to many pattern-recognition and cluster-analysis algorithms. These often rely heavily upon the calculation of distances in high-dimensional vector spaces: distances can be computed at high speed by an array of identical processing elements, operating in parallel under the command of a central controller. To achieve high computing speeds in those pattern recognition algorithms which refer an input vector to each member of a set of stored reference vectors, the processing elements should each contain some `local? storage. Of course, not all pattern-recognition algorithms are parallel, and to accomodate these, the processing elements may be required to operate autonomously. Nevertheless, the system controller must, at all times, be able to force the entire array to operate under its control again. The array can operate in a third mode, namely acting as a pipe-line processor, which is useful in some situations (e.g. computing polynomials) and for transferring data between the array's local store and the system controller. A rectangular array is even faster than a linear one, but is, of course, more expensive. The cost and performance of an array of Intel 8080 microprocessors are compared to those of other systems.
{"title":"Microprocessor arrays for pattern recognition","authors":"S. M. Boxer, B. Batchelor","doi":"10.1049/IJ-CDT.1978.0018","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0018","url":null,"abstract":"A linear array of microprocessors provides a powerful computing system that is particularly well suited to many pattern-recognition and cluster-analysis algorithms. These often rely heavily upon the calculation of distances in high-dimensional vector spaces: distances can be computed at high speed by an array of identical processing elements, operating in parallel under the command of a central controller. To achieve high computing speeds in those pattern recognition algorithms which refer an input vector to each member of a set of stored reference vectors, the processing elements should each contain some `local? storage. Of course, not all pattern-recognition algorithms are parallel, and to accomodate these, the processing elements may be required to operate autonomously. Nevertheless, the system controller must, at all times, be able to force the entire array to operate under its control again. The array can operate in a third mode, namely acting as a pipe-line processor, which is useful in some situations (e.g. computing polynomials) and for transferring data between the array's local store and the system controller. A rectangular array is even faster than a linear one, but is, of course, more expensive. The cost and performance of an array of Intel 8080 microprocessors are compared to those of other systems.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129514190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-05-01DOI: 10.1049/IJ-CDT.1978.0014
I. Aleksander
{"title":"The Theory of Computer Science","authors":"I. Aleksander","doi":"10.1049/IJ-CDT.1978.0014","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0014","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122127503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Banâtre, F. Kerangueven, H. Leroy, G. Paget, J. Routeau
The note describes a current research project aimed at breaking down the task of program compilation into processes that can be carried out in parallel. A further aim is to define an appropriate achitecture.
{"title":"Designing an application-oriented distributed system","authors":"J. Banâtre, F. Kerangueven, H. Leroy, G. Paget, J. Routeau","doi":"10.1049/IJ-CDT:19780019","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780019","url":null,"abstract":"The note describes a current research project aimed at breaking down the task of program compilation into processes that can be carried out in parallel. A further aim is to define an appropriate achitecture.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116469281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-02-01DOI: 10.1049/IJ-CDT.1978.0008
D. Green, M. Edkins
The synthesis of economical multilevel circuits for binary and multiple-valued switching circuits is described. The mode of function description is that provided by the algebra of finite fields and this leads to a highly modular form of circuit representation. A universal-logic tree composed of GF(q) adders and multipliers is used as a template on which to construct specific multilevel circuits. The paper describes methods for assigning the input variables to the network so as to reduce the complexity of the general tree by removing the redundant circuit elements. The resulting networks are invariably less costly than those from the direct synthesis of two-level sum-of-products expressions and they use only a restricted set of circuit elements.
{"title":"Synthesis procedures for switching circuits represented Reed-Muller form over a finite field","authors":"D. Green, M. Edkins","doi":"10.1049/IJ-CDT.1978.0008","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0008","url":null,"abstract":"The synthesis of economical multilevel circuits for binary and multiple-valued switching circuits is described. The mode of function description is that provided by the algebra of finite fields and this leads to a highly modular form of circuit representation. A universal-logic tree composed of GF(q) adders and multipliers is used as a template on which to construct specific multilevel circuits. The paper describes methods for assigning the input variables to the network so as to reduce the complexity of the general tree by removing the redundant circuit elements. The resulting networks are invariably less costly than those from the direct synthesis of two-level sum-of-products expressions and they use only a restricted set of circuit elements.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114604438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-02-01DOI: 10.1049/ij-cdt.1978.0010
A. Birch, A. Sullivan
The note outlines the operation of a bit-interleaved seven-channel data-multiplexing system using universal asynchronous receiver/transmitters (u.a.r.t.s). The scheme has been used in an initial multiplexing system at Thames Polytechnic, connecting a number of terminals to a computer at a remote site over a private line.
{"title":"Data multiplexing system using u.a.r.t.s","authors":"A. Birch, A. Sullivan","doi":"10.1049/ij-cdt.1978.0010","DOIUrl":"https://doi.org/10.1049/ij-cdt.1978.0010","url":null,"abstract":"The note outlines the operation of a bit-interleaved seven-channel data-multiplexing system using universal asynchronous receiver/transmitters (u.a.r.t.s). The scheme has been used in an initial multiplexing system at Thames Polytechnic, connecting a number of terminals to a computer at a remote site over a private line.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132209858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the philosophy and structure of the operating-system software which is currently being developed for a closely coupled multicomputer system. The proposed operating system is effectively distributed between the individual computing elements of the system. Each computing element or module contains a copy of a simple operating system or nucleus which has been designed on the one hand to provide a standard software interface for the applications software within the module and on the other to form an interface with other modules through the intercomputer-communication facility. A necessary and sufficient condition for a computing module to function in the proposed system is the possession of a copy of this nucleus. The nucleus software has been implemented in a high-level procedure-based language and is designed to provide the applications programmer with a basic set of commands or primitives which facilitate the creation and control of other application processes resident within other modules. The paper also includes details of the size of the implemented system.
{"title":"Software aspects of a closely coupled multicomputer system","authors":"F. Halsall, A. Fenesan","doi":"10.1049/IJ-CDT:19780007","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780007","url":null,"abstract":"This paper describes the philosophy and structure of the operating-system software which is currently being developed for a closely coupled multicomputer system. The proposed operating system is effectively distributed between the individual computing elements of the system. Each computing element or module contains a copy of a simple operating system or nucleus which has been designed on the one hand to provide a standard software interface for the applications software within the module and on the other to form an interface with other modules through the intercomputer-communication facility. A necessary and sufficient condition for a computing module to function in the proposed system is the possession of a copy of this nucleus. The nucleus software has been implemented in a high-level procedure-based language and is designed to provide the applications programmer with a basic set of commands or primitives which facilitate the creation and control of other application processes resident within other modules. The paper also includes details of the size of the implemented system.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134145592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.
{"title":"Modular minicomputer with an associative stack and a virtual-addressing capability","authors":"L.E.M. Warburton, J. S. Martin, D. Edwards","doi":"10.1049/IJ-CDT:19780004","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780004","url":null,"abstract":"The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-02-01DOI: 10.1049/IJ-CDT.1978.0002
J. Gosling
It is common knowledge that a commercial machine rarely comes up to the hopes of its original designer. Computing machines are often as much as three times slower than originally intended. The paper looks at one section of a computing machine and deduces the reason as inattention to `side effects? at a sufficiently early stage in the design process, and to `add-on? extras that have a greater effect than expected. The study illustrates the need for more attention to be given to these problems by researchers and the need for more willing co-operation between designer and user.
{"title":"Some pitfalls in computer design","authors":"J. Gosling","doi":"10.1049/IJ-CDT.1978.0002","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0002","url":null,"abstract":"It is common knowledge that a commercial machine rarely comes up to the hopes of its original designer. Computing machines are often as much as three times slower than originally intended. The paper looks at one section of a computing machine and deduces the reason as inattention to `side effects? at a sufficiently early stage in the design process, and to `add-on? extras that have a greater effect than expected. The study illustrates the need for more attention to be given to these problems by researchers and the need for more willing co-operation between designer and user.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114083305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1049/IJ-CDT.1979.0050
P. Lee
{"title":"Conference Report. 9th Annual International Symposium on Fault-Tolerant Computing (FTCS 9)","authors":"P. Lee","doi":"10.1049/IJ-CDT.1979.0050","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0050","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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