Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654140
R. Dick
This tutorial provides an overview of challenges to designing and implementing reliable integrated circuits and systems, and suggests areas for future study. It illustrates some concepts in detail, explaining the challenges of appropriately considering the impact of temperature on reliability in fault-tolerant systems. Finally, it points out considerations that may influence adoption of reliability modeling and optimization techniques and stresses the importance of considering the most relevant fault processes during reliability modeling and optimization.
{"title":"Reliability, thermal, and power modeling and optimization","authors":"R. Dick","doi":"10.1109/ICCAD.2010.5654140","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654140","url":null,"abstract":"This tutorial provides an overview of challenges to designing and implementing reliable integrated circuits and systems, and suggests areas for future study. It illustrates some concepts in detail, explaining the challenges of appropriately considering the impact of temperature on reliability in fault-tolerant systems. Finally, it points out considerations that may influence adoption of reliability modeling and optimization techniques and stresses the importance of considering the most relevant fault processes during reliability modeling and optimization.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133658603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653652
Danbee Park, Jungseob Lee, N. Kim, Taewhan Kim
This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functional units in microprocessor during the code execution, so that the leakage power is maximally saved. Precisely, based on an execution profile of code containing conditional braches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions into code with the objective of minimzing the expected total leakage power while considerig the power and delay overhead on power gating.
{"title":"Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors","authors":"Danbee Park, Jungseob Lee, N. Kim, Taewhan Kim","doi":"10.1109/ICCAD.2010.5653652","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653652","url":null,"abstract":"This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functional units in microprocessor during the code execution, so that the leakage power is maximally saved. Precisely, based on an execution profile of code containing conditional braches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions into code with the objective of minimzing the expected total leakage power while considerig the power and delay overhead on power gating.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115614430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654333
G. Shi
Determinant decision diagram (DDD) uses a Binary Decision Diagram (BDD) to represent the Laplace expansion of a determinant. It is used as the core computation engine in some modern symbolic circuit simulators. The traditional implementations rely on a BDD package for the common-data sharing operations in which symbol ordering plays an essential role. This paper proposes a simple implementation method which does not use any BDD package. Sharing is implemented by directly hashing minors, while the requirement on symbol ordering is weakened to an expansion ordering. The basic mechanism used is a natural formulation of layered expansion which is analogous to manual expansion of a determinant, hence it is easily understood. The simplified DDD construction method not only makes the DDD implementation straightforward, but also results in greater efficiency. A simulator developed based on this new method solves the μa725 op-amp circuit in a few seconds by flat expansion.
{"title":"A simple implementation of determinant decision diagram","authors":"G. Shi","doi":"10.1109/ICCAD.2010.5654333","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654333","url":null,"abstract":"Determinant decision diagram (DDD) uses a Binary Decision Diagram (BDD) to represent the Laplace expansion of a determinant. It is used as the core computation engine in some modern symbolic circuit simulators. The traditional implementations rely on a BDD package for the common-data sharing operations in which symbol ordering plays an essential role. This paper proposes a simple implementation method which does not use any BDD package. Sharing is implemented by directly hashing minors, while the requirement on symbol ordering is weakened to an expansion ordering. The basic mechanism used is a natural formulation of layered expansion which is analogous to manual expansion of a determinant, hence it is easily understood. The simplified DDD construction method not only makes the DDD implementation straightforward, but also results in greater efficiency. A simulator developed based on this new method solves the μa725 op-amp circuit in a few seconds by flat expansion.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115620990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654159
G. Gielen, Elie Maricau, P. D. Wit
Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to degradation mechanisms like NBTI or soft breakdown, as well as increased external interference such as caused by crosstalk and EMI, cause time-dependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and design tools that help designers coping with these reliability and variability problems. This tutorial paper gives a brief description of design tools for the efficient analysis and identification of reliability problems in analog circuits, as a first step towards the automated design of guaranteed reliable analog circuits.
{"title":"Design automation towards reliable analog integrated circuits","authors":"G. Gielen, Elie Maricau, P. D. Wit","doi":"10.1109/ICCAD.2010.5654159","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654159","url":null,"abstract":"Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to degradation mechanisms like NBTI or soft breakdown, as well as increased external interference such as caused by crosstalk and EMI, cause time-dependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and design tools that help designers coping with these reliability and variability problems. This tutorial paper gives a brief description of design tools for the efficient analysis and identification of reliability problems in analog circuits, as a first step towards the automated design of guaranteed reliable analog circuits.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115735695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654309
Dominik Lorenz, M. Barke, Ulf Schlichtmann
Aging, which can be regarded as a time-dependent variability, has until recently not received much attention in the field of electronic design automation. This is changing because increasing reliability costs threaten the continued scaling of ICs. We investigate the impact of aging effects on single combinatorial gates and present methods that help to reduce the reliability costs by accurately analyzing the performance degradation of aged circuits at gate and macro cell level.
{"title":"Aging analysis at gate and macro cell level","authors":"Dominik Lorenz, M. Barke, Ulf Schlichtmann","doi":"10.1109/ICCAD.2010.5654309","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654309","url":null,"abstract":"Aging, which can be regarded as a time-dependent variability, has until recently not received much attention in the field of electronic design automation. This is changing because increasing reliability costs threaten the continued scaling of ICs. We investigate the impact of aging effects on single combinatorial gates and present methods that help to reduce the reliability costs by accurately analyzing the performance degradation of aged circuits at gate and macro cell level.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115697125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654094
Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang
Global routing is a very crucial stage in a design cycle, because it physically plans the routes of nets on a chip. In order to boost the research and development of global routing techniques, ISPD held contests and released benchmarks in 2007 and 2008, respectively. However, the contests may lead researchers away from facing other real problems in practice. In this paper we study a new global routing problem that not only considers traditional routing objectives such as overflow and wirelength but also focuses on honoring layer directives that are usually specified for timing-critical nets to alleviate performance degrading. Based on novel extensions of an academic router, we present a new global router called GLADE for the addressed problem. The experimental results show that GLADE can effectively generate a high-quality solution, which balances the metrics under consideration, for each test case from the set of recently released ICCAD 2009 benchmarks.
{"title":"GLADE: A modern global router considering layer directives","authors":"Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang","doi":"10.1109/ICCAD.2010.5654094","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654094","url":null,"abstract":"Global routing is a very crucial stage in a design cycle, because it physically plans the routes of nets on a chip. In order to boost the research and development of global routing techniques, ISPD held contests and released benchmarks in 2007 and 2008, respectively. However, the contests may lead researchers away from facing other real problems in practice. In this paper we study a new global routing problem that not only considers traditional routing objectives such as overflow and wirelength but also focuses on honoring layer directives that are usually specified for timing-critical nets to alleviate performance degrading. Based on novel extensions of an academic router, we present a new global router called GLADE for the addressed problem. The experimental results show that GLADE can effectively generate a high-quality solution, which balances the metrics under consideration, for each test case from the set of recently released ICCAD 2009 benchmarks.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654317
K. Bowman, J. Tschanz
In this tutorial, a 45nm resilient microprocessor core with error-detection and recovery circuits demonstrates the opportunity for improving performance and energy efficiency by mitigating the impact of dynamic parameter variations. The design methodology describes the additional steps beyond a standard design flow for integrating error-detection and recovery circuits into a microprocessor core. Silicon measurements indicate that the resilient design enables a 41% throughput benefit at iso-energy or a 22% energy reduction at iso-throughput, as compared to a conventional design.
{"title":"Resilient microprocessor design for improving performance and energy efficiency","authors":"K. Bowman, J. Tschanz","doi":"10.1109/ICCAD.2010.5654317","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654317","url":null,"abstract":"In this tutorial, a 45nm resilient microprocessor core with error-detection and recovery circuits demonstrates the opportunity for improving performance and energy efficiency by mitigating the impact of dynamic parameter variations. The design methodology describes the additional steps beyond a standard design flow for integrating error-detection and recovery circuits into a microprocessor core. Silicon measurements indicate that the resilient design enables a 41% throughput benefit at iso-energy or a 22% energy reduction at iso-throughput, as compared to a conventional design.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123339362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654215
Chih-Fan Lai, J. H. Jiang, Kuo-Hua Wang
Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negation of their inputs and outputs. Despite its importance in design rectification, technology mapping, and other logic synthesis applications, there is no much direct study on this subject due to its generality and consequent computational complexity. This paper extends our prior Boolean matching decision procedure BooM to consider multiple-output functions. Through conflict-driven learning and partial assignment reduction, Boolean matching in the most general setting can still be accomplishable even when all other techniques lose their foundation and become unapplicable. Experiments demonstrate the indispensable power of strengthened learning for practical applications.
{"title":"Boolean matching of function vectors with strengthened learning","authors":"Chih-Fan Lai, J. H. Jiang, Kuo-Hua Wang","doi":"10.1109/ICCAD.2010.5654215","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654215","url":null,"abstract":"Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negation of their inputs and outputs. Despite its importance in design rectification, technology mapping, and other logic synthesis applications, there is no much direct study on this subject due to its generality and consequent computational complexity. This paper extends our prior Boolean matching decision procedure BooM to consider multiple-output functions. Through conflict-driven learning and partial assignment reduction, Boolean matching in the most general setting can still be accomplishable even when all other techniques lose their foundation and become unapplicable. Experiments demonstrate the indispensable power of strengthened learning for practical applications.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123648696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654269
V. Karkala, Joseph Wanstrath, Travis Lacour, S. Khatri
In this paper, we present an arithmetic sum-of-products (SOP) based realization of the general Multiple Constant Multiplication (MCM) algorithm. We also propose an enhanced SOP based algorithm, which uses Partial Max-SAT (PMSAT) to further optimize the SOP. The enhanced algorithm attempts to reduce the number of rows (partial products) of the SOP, by i) shifting coefficients to realize other coefficients when possible, ii) exploring multiple implementations of each coefficient using a Minimal Signed Digit (MSD) format and iii) exploiting the mutual exclusiveness within certain groups of partial products. Hardware implementations of the Fast Fourier Transform (FFT) algorithm require the incoming data to be multiplied by one of several constant coefficients. We test/validate it for FFT, which is an important problem. We compare our SOP-based architectures with the best existing implementation of MCM for FFT (which utilizes a cascade of adders), and show that our approaches show a significant improvement in area and delay. Our architecture was synthesized using 65nm technology libraries.
{"title":"Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT","authors":"V. Karkala, Joseph Wanstrath, Travis Lacour, S. Khatri","doi":"10.1109/ICCAD.2010.5654269","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654269","url":null,"abstract":"In this paper, we present an arithmetic sum-of-products (SOP) based realization of the general Multiple Constant Multiplication (MCM) algorithm. We also propose an enhanced SOP based algorithm, which uses Partial Max-SAT (PMSAT) to further optimize the SOP. The enhanced algorithm attempts to reduce the number of rows (partial products) of the SOP, by i) shifting coefficients to realize other coefficients when possible, ii) exploring multiple implementations of each coefficient using a Minimal Signed Digit (MSD) format and iii) exploiting the mutual exclusiveness within certain groups of partial products. Hardware implementations of the Fast Fourier Transform (FFT) algorithm require the incoming data to be multiplied by one of several constant coefficients. We test/validate it for FFT, which is an important problem. We compare our SOP-based architectures with the best existing implementation of MCM for FFT (which utilizes a cascade of adders), and show that our approaches show a significant improvement in area and delay. Our architecture was synthesized using 65nm technology libraries.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"11 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116800350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654194
Vineeth Veetil, D. Sylvester, D. Blaauw
Increase in variability in the nanometer era has contributed to pessimistic guardbands for conventional circuit design techniques that optimize at worst-case process corners. Smart deterministic approaches have been proposed that employ statistical timing analysis to reduce pessimism in the guardbands while retaining the deterministic nature of the algorithms. Other statistical optimization techniques focus on algorithms to maximize robustness of design while being aware of variability. It is not clear how much improvement can be gained using the latter set of approaches over more simple deterministic approaches. This work presents a new lower bound to evaluate these statistical optimization techniques, drawing inspiration from recent advances in sampling based SSTA. We prove that the presented lower bound gives the minimum possible area that can be achieved for a design while meeting a particular timing yield, which is the percentage of die that meeting a specified timing constraint. We then compare several statistical design optimization approaches, including one proposed in this paper called SLOP, against the computed lower bound. We show that even the simplest statistical optimization approaches produce area results which are, on average, within 9.6% of the lower bound while the best ones performed only marginally better, reaching within 3.7% of the bound. This demonstrates that the proposed bound is a close bound. In addition, it also shows that the existing optimization methods have nearly exhausted the obtainable improvement from being statistically aware and mostly provide trade-offs in runtime speed.
{"title":"A lower bound computation method for evaluation of statistical design techniques","authors":"Vineeth Veetil, D. Sylvester, D. Blaauw","doi":"10.1109/ICCAD.2010.5654194","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654194","url":null,"abstract":"Increase in variability in the nanometer era has contributed to pessimistic guardbands for conventional circuit design techniques that optimize at worst-case process corners. Smart deterministic approaches have been proposed that employ statistical timing analysis to reduce pessimism in the guardbands while retaining the deterministic nature of the algorithms. Other statistical optimization techniques focus on algorithms to maximize robustness of design while being aware of variability. It is not clear how much improvement can be gained using the latter set of approaches over more simple deterministic approaches. This work presents a new lower bound to evaluate these statistical optimization techniques, drawing inspiration from recent advances in sampling based SSTA. We prove that the presented lower bound gives the minimum possible area that can be achieved for a design while meeting a particular timing yield, which is the percentage of die that meeting a specified timing constraint. We then compare several statistical design optimization approaches, including one proposed in this paper called SLOP, against the computed lower bound. We show that even the simplest statistical optimization approaches produce area results which are, on average, within 9.6% of the lower bound while the best ones performed only marginally better, reaching within 3.7% of the bound. This demonstrates that the proposed bound is a close bound. In addition, it also shows that the existing optimization methods have nearly exhausted the obtainable improvement from being statistically aware and mostly provide trade-offs in runtime speed.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121621124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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