Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746404
Chunming Zhang, Zhibiao Shao
Modern power applications are driving the demand for power supply systems with fast transient response. A novel controlled slew-rate enhancement (CSRE) circuit for error amplifier in high frequency DC-DC converters is proposed to improve transient responds of DC-DC converters under large load current changes. The CSRE circuit with embedded current-detection is connected in parallel with the error amplifier. By detecting the maximum difference current corresponding to the maximum derivation of the output voltage and optimizing sizes of the CSRE circuit, the CSRE circuit can be controlled properly so that the system stability can be guaranteed in various operating conditions. When the proposed circuits was employed in 100 MHz buck DC-DC converters implemented in SMIC 0.18 mum CMOS process, the simulation results of transient responses show that the CSRE circuit improves the average 1% settling time by 20 times and overshoot by 16 times, while the total quiescent power is only increased by less than 7.1.
{"title":"Controlled slew rate enhancement circuit for error amplifier in high frequency DC-DC converters","authors":"Chunming Zhang, Zhibiao Shao","doi":"10.1109/APCCAS.2008.4746404","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746404","url":null,"abstract":"Modern power applications are driving the demand for power supply systems with fast transient response. A novel controlled slew-rate enhancement (CSRE) circuit for error amplifier in high frequency DC-DC converters is proposed to improve transient responds of DC-DC converters under large load current changes. The CSRE circuit with embedded current-detection is connected in parallel with the error amplifier. By detecting the maximum difference current corresponding to the maximum derivation of the output voltage and optimizing sizes of the CSRE circuit, the CSRE circuit can be controlled properly so that the system stability can be guaranteed in various operating conditions. When the proposed circuits was employed in 100 MHz buck DC-DC converters implemented in SMIC 0.18 mum CMOS process, the simulation results of transient responses show that the CSRE circuit improves the average 1% settling time by 20 times and overshoot by 16 times, while the total quiescent power is only increased by less than 7.1.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745972
Chunpeng Zhang, Qirong Jiang, L. Tong
Impact loads require STATCOM to have fast and robust performances. Based on the analysis of mathematic model, a decoupling control method of STATCOM is investigated in this paper. This method is implemented in two industrial STATCOMs and presents satisfied control capabilities. The compensated PCCs of impact loads obtain significant improvements of power quality.
{"title":"A decoupling-controlled STATCOM for power quality improvement of impact loads","authors":"Chunpeng Zhang, Qirong Jiang, L. Tong","doi":"10.1109/APCCAS.2008.4745972","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745972","url":null,"abstract":"Impact loads require STATCOM to have fast and robust performances. Based on the analysis of mathematic model, a decoupling control method of STATCOM is investigated in this paper. This method is implemented in two industrial STATCOMs and presents satisfied control capabilities. The compensated PCCs of impact loads obtain significant improvements of power quality.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"38 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114124447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746319
Mohamed N. Hassan, M. Benaissa
Implementing public key cryptosystems like elliptic curve cryptography on lightweight devices represents an ongoing challenge. An improved algorithm for Montgomery modular inversion over GF(2m) suitable for low resource scalable implementations is proposed. Two implementations for the proposed algorithm are presented and compared. The first is based on the Xilinx PicoBlaze soft core and the second is a dedicated novel FPGA hardware architecture for the proposed algorithm which is scalable for the binary fields recommended by the NIST (up to m les 571 ) and is parameterized to support different word lengths. Both designs are fully mapped onto the smallest size and lowest cost chip from Xilinx Spartan-III family (XC3S50).
{"title":"An improved Montgomery inversion algorithm over GF(2m) targeted for low area scalable inverter on FPGA","authors":"Mohamed N. Hassan, M. Benaissa","doi":"10.1109/APCCAS.2008.4746319","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746319","url":null,"abstract":"Implementing public key cryptosystems like elliptic curve cryptography on lightweight devices represents an ongoing challenge. An improved algorithm for Montgomery modular inversion over GF(2m) suitable for low resource scalable implementations is proposed. Two implementations for the proposed algorithm are presented and compared. The first is based on the Xilinx PicoBlaze soft core and the second is a dedicated novel FPGA hardware architecture for the proposed algorithm which is scalable for the binary fields recommended by the NIST (up to m les 571 ) and is parameterized to support different word lengths. Both designs are fully mapped onto the smallest size and lowest cost chip from Xilinx Spartan-III family (XC3S50).","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"409 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116133984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746090
Jianwu Chen, Yik-Chung Wu, T. Ng
In this paper, we investigate the problem of carrier frequency offset (CFO) estimation for orthogonal frequency division multiplexing (OFDM) system over doubly-selective channels. Representing the doubly-selective channels with basis expansion, the signal model is reformulated and one CFO estimator is derived. Furthermore, the Cramer-Rao bound (CRB) for the estimation problem is derived in closed form. The effectiveness of the proposed scheme is verified by simulations.
{"title":"Frequency synchronization for OFDM systems over doubly-selective channels","authors":"Jianwu Chen, Yik-Chung Wu, T. Ng","doi":"10.1109/APCCAS.2008.4746090","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746090","url":null,"abstract":"In this paper, we investigate the problem of carrier frequency offset (CFO) estimation for orthogonal frequency division multiplexing (OFDM) system over doubly-selective channels. Representing the doubly-selective channels with basis expansion, the signal model is reformulated and one CFO estimator is derived. Furthermore, the Cramer-Rao bound (CRB) for the estimation problem is derived in closed form. The effectiveness of the proposed scheme is verified by simulations.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121830373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746344
Yi Wang, Yikai Wang, Lenian He
This paper presents the behavioral models for operational amplifier (opamp) by using analog hardware description language, Verilog-A. The Opamppsilas behavioral model is built with limited unit-gain bandwidth, slew-rate and nonlinear gain. A hyperbolic tangent model has been used to describe the nonlinearity of the Opamppsilas gain, which provides the error less than 0.26% against the transistor-level implementation. During the simulation of sigma-delta modulator, the switch-capacitor circuits and comparator are implemented in transistor level, simulations are performed at the transistor and behavioral mixed level, thus the error caused by time sequence has been introduced into the simulation results. The comparative results show that the Verilog-A model for Opamp incurs an error of no more than 0.3 dB in the magnitude of harmonics while providing a 15times advantage in the simulation speed with respect to transistor-level implementations.
{"title":"Behavioral modeling for operational amplifier in sigma-delta modulators with Verilog-A","authors":"Yi Wang, Yikai Wang, Lenian He","doi":"10.1109/APCCAS.2008.4746344","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746344","url":null,"abstract":"This paper presents the behavioral models for operational amplifier (opamp) by using analog hardware description language, Verilog-A. The Opamppsilas behavioral model is built with limited unit-gain bandwidth, slew-rate and nonlinear gain. A hyperbolic tangent model has been used to describe the nonlinearity of the Opamppsilas gain, which provides the error less than 0.26% against the transistor-level implementation. During the simulation of sigma-delta modulator, the switch-capacitor circuits and comparator are implemented in transistor level, simulations are performed at the transistor and behavioral mixed level, thus the error caused by time sequence has been introduced into the simulation results. The comparative results show that the Verilog-A model for Opamp incurs an error of no more than 0.3 dB in the magnitude of harmonics while providing a 15times advantage in the simulation speed with respect to transistor-level implementations.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A CMOS sub-1 V capacitor-free low-power-consumption low-dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without off-chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9 V power supply voltage, the output voltage is designed as 0.6 V. The maximum output current of the LDO is 120 mA at an output of 0.6 V. The prototype of the LDO is fabricated with TSMC 0.35-mum CMOS processes. The chip area (including I/O pad) is only 927 mum times 969 mum.
{"title":"Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop","authors":"Jiann-Jong Chen, Ming-Shian Lin, Ho-Cheng Lin, Yuh-Shyan Hwang","doi":"10.1109/APCCAS.2008.4746076","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746076","url":null,"abstract":"A CMOS sub-1 V capacitor-free low-power-consumption low-dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without off-chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9 V power supply voltage, the output voltage is designed as 0.6 V. The maximum output current of the LDO is 120 mA at an output of 0.6 V. The prototype of the LDO is fabricated with TSMC 0.35-mum CMOS processes. The chip area (including I/O pad) is only 927 mum times 969 mum.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125105366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746055
T. Tsai, Chia-Hao Yeh, Yu-Jung Huang
The Hough transform is a widely used technique by converting the original spatial information in an image into a parameter space representation. It can be applied to detect straight lines, circles, ellipses and various other curves in two dimensional scenes as well as in the recognition of three dimensional objects. In this article, the trigonometric cosine and sine functions required in the computation of Hough transform are realized using a CORDIC based floating-point arithmetic scheme. The Hough transformation is simulated by Simulink simulation tools. The architecture of image enhance processing based on Laplace filtering is verified and simulated with Cadence design tools. The image enhancement system is also demonstrated on the Cyclone II FPGA device.
霍夫变换是将图像中原始空间信息转换为参数空间表示的一种广泛应用的技术。它既可以用于二维场景中直线、圆、椭圆等各种曲线的检测，也可以用于三维物体的识别。本文采用基于CORDIC的浮点算法实现了计算霍夫变换所需的三角余弦函数和正弦函数。利用Simulink仿真工具对Hough变换进行了仿真。利用Cadence设计工具对基于拉普拉斯滤波的图像增强处理体系结构进行了验证和仿真。图像增强系统也在Cyclone II FPGA器件上进行了演示。
{"title":"Cordic architecture for Hough Transform applications","authors":"T. Tsai, Chia-Hao Yeh, Yu-Jung Huang","doi":"10.1109/APCCAS.2008.4746055","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746055","url":null,"abstract":"The Hough transform is a widely used technique by converting the original spatial information in an image into a parameter space representation. It can be applied to detect straight lines, circles, ellipses and various other curves in two dimensional scenes as well as in the recognition of three dimensional objects. In this article, the trigonometric cosine and sine functions required in the computation of Hough transform are realized using a CORDIC based floating-point arithmetic scheme. The Hough transformation is simulated by Simulink simulation tools. The architecture of image enhance processing based on Laplace filtering is verified and simulated with Cadence design tools. The image enhancement system is also demonstrated on the Cyclone II FPGA device.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122826029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746384
Mu-Tien Chang, W. Hwang
SRAM cell stability is a major challenge in subthreshold SRAM design. In this paper, a robust, fully-differential subthreshold 10-transistors SRAM cell with auto-compensation is proposed. With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM). The cell structure also prevents storage nodes from bitline noise interference, thus improving read SNM. Moreover, better write ability is achieved by applying write assist technique. Based on UMC 90 nm CMOS technology, simulation results shows that at 200 mV supply voltage, the proposed cell has 1.22X hold SNM improvement, 2.09X read SNM improvement, and 2.03X write margin improvement compared to the conventional 6T SRAM cell.
{"title":"A fully-differential subthreshold SRAM cell with auto-compensation","authors":"Mu-Tien Chang, W. Hwang","doi":"10.1109/APCCAS.2008.4746384","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746384","url":null,"abstract":"SRAM cell stability is a major challenge in subthreshold SRAM design. In this paper, a robust, fully-differential subthreshold 10-transistors SRAM cell with auto-compensation is proposed. With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM). The cell structure also prevents storage nodes from bitline noise interference, thus improving read SNM. Moreover, better write ability is achieved by applying write assist technique. Based on UMC 90 nm CMOS technology, simulation results shows that at 200 mV supply voltage, the proposed cell has 1.22X hold SNM improvement, 2.09X read SNM improvement, and 2.03X write margin improvement compared to the conventional 6T SRAM cell.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"44 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127572381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746023
Baofeng Li, Y. Dou, Yuanwu Lei
Because of serial inherence of the arithmetic encoder (AE) for the embedded block coding algorithm in JPEG2000, efficient hardware implementation of AE plays a key role in overall system throughput. In this paper, four pipelined architectures which are single-symbol coding 3-stage pipeline, single-symbol coding 4-stage pipeline, two-symbol coding 3-stage pipeline and two-symbol coding 4-stage pipeline, are investigated. Results from FPGA-based implementations show that the single-symbol coding 3-stage pipeline architecture has the best actual throughput ((133N)/(N + 2) CX/S pairs per second) and occupies the least resources (1100 ALUTs and 365 registers) in all four. Compared with several related works, our designs outperforms them in terms of tradeoff of area and throughput.
{"title":"Area and throughput trade-offs in design of arithmetic encoder for JPEG2000","authors":"Baofeng Li, Y. Dou, Yuanwu Lei","doi":"10.1109/APCCAS.2008.4746023","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746023","url":null,"abstract":"Because of serial inherence of the arithmetic encoder (AE) for the embedded block coding algorithm in JPEG2000, efficient hardware implementation of AE plays a key role in overall system throughput. In this paper, four pipelined architectures which are single-symbol coding 3-stage pipeline, single-symbol coding 4-stage pipeline, two-symbol coding 3-stage pipeline and two-symbol coding 4-stage pipeline, are investigated. Results from FPGA-based implementations show that the single-symbol coding 3-stage pipeline architecture has the best actual throughput ((133N)/(N + 2) CX/S pairs per second) and occupies the least resources (1100 ALUTs and 365 registers) in all four. Compared with several related works, our designs outperforms them in terms of tradeoff of area and throughput.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128059739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746022
Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo
This paper presents a high throughput VLSI architecture for H.264/AVC in-loop de-blocking filter (ILF) supporting baseline, main, and high profile (BP/MP/HP) video decoding targeted at HDTV applications. We develop a 4times4/8times8 filter and a buffer management scheme to perform the various coding tools in H.264 de-blocking filter for supporting the coding tools of picture adaptive frame/field (PAFF) coding, macroblock adaptive frame/field (MBAFF) coding, and 8times8 transform coding. In particular, we adopt two local buffers to store the reference MB pair data and reschedule the internal pixels when switching the filtering operations on the horizontal and vertical edges without writing it out to the external memory. Adopting TSMC 0.13 mum CMOS technology, we implement the proposed design with the cost of 36.9 K gates and 672 bytes of local memory when operating at 225 MHz. Moreover, the proposed design achieves the data throughput rate of 260 cycles per MB in average, which meets the real-time processing requirement for H.264 16 VGA (2560times1920)@30 fps video decoding.
{"title":"A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding","authors":"Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo","doi":"10.1109/APCCAS.2008.4746022","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746022","url":null,"abstract":"This paper presents a high throughput VLSI architecture for H.264/AVC in-loop de-blocking filter (ILF) supporting baseline, main, and high profile (BP/MP/HP) video decoding targeted at HDTV applications. We develop a 4times4/8times8 filter and a buffer management scheme to perform the various coding tools in H.264 de-blocking filter for supporting the coding tools of picture adaptive frame/field (PAFF) coding, macroblock adaptive frame/field (MBAFF) coding, and 8times8 transform coding. In particular, we adopt two local buffers to store the reference MB pair data and reschedule the internal pixels when switching the filtering operations on the horizontal and vertical edges without writing it out to the external memory. Adopting TSMC 0.13 mum CMOS technology, we implement the proposed design with the cost of 36.9 K gates and 672 bytes of local memory when operating at 225 MHz. Moreover, the proposed design achieves the data throughput rate of 260 cycles per MB in average, which meets the real-time processing requirement for H.264 16 VGA (2560times1920)@30 fps video decoding.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132727571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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