We have seen a peak birth-rate in recent years. Meanwhile more DSI (dysfunction of sensory integration) symptoms were observed from young children. The sensory integration is indeed very important for young children, but current relevant pedagogy seems too inadequate to train the sensory integration. Therefore, we designed an intelligent sensory integration training system DSIGame which employs many high technologies such as wireless sensor network, RFID, ubiquitous computing, database, augmented virtual reality and so on. This system can help the trained children to achieve better sensory integration so as to fulfill the requirement of equal education without distinction between classes of children.
{"title":"A novel WSN based intelligent training system for children’s sensory integration","authors":"Shaohua Liu, Junsheng Yu, Yinglong Ma, Qi Dang, Yilang Cen, Hua Wang, Di Wu","doi":"10.1109/APCCAS.2008.4746048","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746048","url":null,"abstract":"We have seen a peak birth-rate in recent years. Meanwhile more DSI (dysfunction of sensory integration) symptoms were observed from young children. The sensory integration is indeed very important for young children, but current relevant pedagogy seems too inadequate to train the sensory integration. Therefore, we designed an intelligent sensory integration training system DSIGame which employs many high technologies such as wireless sensor network, RFID, ubiquitous computing, database, augmented virtual reality and so on. This system can help the trained children to achieve better sensory integration so as to fulfill the requirement of equal education without distinction between classes of children.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127114389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746395
Nguyen Huu Quynh, Ngo Quoc Tao, Ngo Truong Giang
This paper deals with a novel technique that utilizes a weighted undirected graph for each color, called GHSG, and applied in landscape images including three steps: Calculating the similarity between query image and all database images based on global color histogram method. Making a set of images includes all the images that are filtered from the image database. The similarity of query image with each image in the above image set is calculated according to a method which constructs sector graph for each color. We carried out an experiment on an image database containing 7,560 landscape images. Experimental result shows that our technique is more effective than the local color histogram and cell/color histograms.
{"title":"Efficient content based image retrieval through sector histogram","authors":"Nguyen Huu Quynh, Ngo Quoc Tao, Ngo Truong Giang","doi":"10.1109/APCCAS.2008.4746395","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746395","url":null,"abstract":"This paper deals with a novel technique that utilizes a weighted undirected graph for each color, called GHSG, and applied in landscape images including three steps: Calculating the similarity between query image and all database images based on global color histogram method. Making a set of images includes all the images that are filtered from the image database. The similarity of query image with each image in the above image set is calculated according to a method which constructs sector graph for each color. We carried out an experiment on an image database containing 7,560 landscape images. Experimental result shows that our technique is more effective than the local color histogram and cell/color histograms.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130003465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746181
W. Jaikla, M. Siripruchyanun
This article presents a current-mode universal biquadratic filter (low-pass, high-pass, band-pass functions), based on multiple-output current controlled current conveyor transconductance amplifiers (MO-CCCCTAs). The features of the circuit are that: the quality factor and pole frequency can be tuned orthogonally via the input bias currents: the circuit description is very simple, consisting of merely 2 MO-CCCCTAs and 2 grounded capacitors. Without any external resistors, requiring no component matching conditions, and using only grounded elements, the proposed circuit is very appropriate to further develop into an integrated circuit. Moreover, the proposed circuit enables easy cascading in current-mode, due to high-output impedances. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation. The power consumption is approximately 4.04 mW at plusmn1.5 V power supply voltages.
{"title":"A cascadable current-mode universal biquadratic filter using MO-CCCCTAs","authors":"W. Jaikla, M. Siripruchyanun","doi":"10.1109/APCCAS.2008.4746181","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746181","url":null,"abstract":"This article presents a current-mode universal biquadratic filter (low-pass, high-pass, band-pass functions), based on multiple-output current controlled current conveyor transconductance amplifiers (MO-CCCCTAs). The features of the circuit are that: the quality factor and pole frequency can be tuned orthogonally via the input bias currents: the circuit description is very simple, consisting of merely 2 MO-CCCCTAs and 2 grounded capacitors. Without any external resistors, requiring no component matching conditions, and using only grounded elements, the proposed circuit is very appropriate to further develop into an integrated circuit. Moreover, the proposed circuit enables easy cascading in current-mode, due to high-output impedances. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation. The power consumption is approximately 4.04 mW at plusmn1.5 V power supply voltages.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128913370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745990
A. Guntoro, M. Glesner
In this paper, we present the design and the implementation of a 3-input IEEE 754-compliant floating-point adder. 3 level pipeline stages are used in order to distribute the critical paths and to maximize the operating frequency. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 97207 mum square area and has an operating frequency of 420 MHz in a 0.18-mum process.
{"title":"Low-latency VLSI architecture of a 3-input floating-point adder","authors":"A. Guntoro, M. Glesner","doi":"10.1109/APCCAS.2008.4745990","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745990","url":null,"abstract":"In this paper, we present the design and the implementation of a 3-input IEEE 754-compliant floating-point adder. 3 level pipeline stages are used in order to distribute the critical paths and to maximize the operating frequency. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 97207 mum square area and has an operating frequency of 420 MHz in a 0.18-mum process.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129163184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746033
Yuichi Nakamura
This paper describes a new design method for skew-tolerant latch design (STLD) and evaluation on a commercial chip design. The conventional edge-triggered flip-flop (FF) design methods using clock synchronization are very practical, since only the timing constraints defined by a given clock frequency are optimized. However, clock skew that has a strong influence on clock frequency design prevents the FF design because of the variations. Thus, level-triggered latch design methods have been proposed as alternatives to FF-based design methods. An STLD is a kind of level-triggered latch design in which an FF is replaced by a pair of latches: a low-level triggered latch and a high-level triggered latch, and these two latches are moved after replacement. Although STLD can improve clock skew problems, this method is very complicated. We propose a new and more general design method for STLD that uses a new latch moving method. The experimental results indicated that about 6000 timing violation points were improved by using the proposed method on a 100 K gate circuit without resulting in a large penalty area.
{"title":"A design method for skew tolerant latch design","authors":"Yuichi Nakamura","doi":"10.1109/APCCAS.2008.4746033","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746033","url":null,"abstract":"This paper describes a new design method for skew-tolerant latch design (STLD) and evaluation on a commercial chip design. The conventional edge-triggered flip-flop (FF) design methods using clock synchronization are very practical, since only the timing constraints defined by a given clock frequency are optimized. However, clock skew that has a strong influence on clock frequency design prevents the FF design because of the variations. Thus, level-triggered latch design methods have been proposed as alternatives to FF-based design methods. An STLD is a kind of level-triggered latch design in which an FF is replaced by a pair of latches: a low-level triggered latch and a high-level triggered latch, and these two latches are moved after replacement. Although STLD can improve clock skew problems, this method is very complicated. We propose a new and more general design method for STLD that uses a new latch moving method. The experimental results indicated that about 6000 timing violation points were improved by using the proposed method on a 100 K gate circuit without resulting in a large penalty area.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122386364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Overall understanding on the nature and characteristics of the harmonics penetration between different voltage levels is necessary and significative. Factors affecting harmonic penetration are checked in the paper. After comprehensive analysis considering more than one factor simultaneously with the help of 3-dimension mesh plots, the distribution characteristics of with respect to key factors in acceptable ranges are summarized. Especially two kinds of situations in which the harmonic penetration coefficient is close to or even much larger than 1.0 must be regarded, one of which is owing to smaller impedance ratio, and the other is owing to the impedance angle of loads at next voltage level. The method proposed and results provided are universal to be applied.
{"title":"Research on harmonic penetration between different voltage levels","authors":"Tengfei Wang, Yongqiang Zhu, Yonghai Xu, Xiangning Xiao","doi":"10.1109/APCCAS.2008.4745971","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745971","url":null,"abstract":"Overall understanding on the nature and characteristics of the harmonics penetration between different voltage levels is necessary and significative. Factors affecting harmonic penetration are checked in the paper. After comprehensive analysis considering more than one factor simultaneously with the help of 3-dimension mesh plots, the distribution characteristics of with respect to key factors in acceptable ranges are summarized. Especially two kinds of situations in which the harmonic penetration coefficient is close to or even much larger than 1.0 must be regarded, one of which is owing to smaller impedance ratio, and the other is owing to the impedance angle of loads at next voltage level. The method proposed and results provided are universal to be applied.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3D map building is an important task of autonomous land vehicle (ALV) for obstacle detection, path planning. Traditional methods using stereo vision usually relies on dense disparity map obtained by stereo matching, and 3D map is built based on the disparity map. Traditional methods are sensitive to mismatch pixels in disparity map, and dense stereo matching increases lots of unnecessary computation. This paper proposes a novel 3D map building method based on projection of virtual height line(VHL). Unlike traditional methods, the proposed neednpsilat obtain the disparity map, so it reduces the computation cost and can be highly real-time. Simulation and experimental result is given to show that the built 3D map is basically correct and meets the need of ALV navigation. Furthermore, combined with information from INS and GPS, a global 3D map that reflects the actual scene basically and meets the need of ALV navigation, is built based on the local 3D map.
{"title":"3D map building based on projection of virtual height line","authors":"Huahua Chen, Minhui Dong","doi":"10.1109/ICINIS.2008.86","DOIUrl":"https://doi.org/10.1109/ICINIS.2008.86","url":null,"abstract":"3D map building is an important task of autonomous land vehicle (ALV) for obstacle detection, path planning. Traditional methods using stereo vision usually relies on dense disparity map obtained by stereo matching, and 3D map is built based on the disparity map. Traditional methods are sensitive to mismatch pixels in disparity map, and dense stereo matching increases lots of unnecessary computation. This paper proposes a novel 3D map building method based on projection of virtual height line(VHL). Unlike traditional methods, the proposed neednpsilat obtain the disparity map, so it reduces the computation cost and can be highly real-time. Simulation and experimental result is given to show that the built 3D map is basically correct and meets the need of ALV navigation. Furthermore, combined with information from INS and GPS, a global 3D map that reflects the actual scene basically and meets the need of ALV navigation, is built based on the local 3D map.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131335170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746313
P. Silapan, W. Jaikla, M. Siripruchyanun
This article introduces a novel version for implementing current-mode precision full-wave rectifier. The features of the proposed circuit are that: it can rectify and amplify current signal with controllable output magnitude via an input bias current: the output current is free from temperature variation. In addition, direction of the output current signal can be arbitrarily controlled by controlled current in the circuit to be either positive or negative without changing circuit topology, which differs from the previous literatures. Circuit description merely consists of 3 BiCMOS CCCDBAs, without any passive component. The performances of the proposed circuit are investigated through PSPICE. They show that the proposed circuit can function as a current-mode precision full-wave rectifier, where input current range from -240 muA to 240 muA can be achieved at plusmn1.5 V power supplies. The maximum power consumption is 11.8 mW. In addition, the highest frequency is restricted at up to megahertz range.
{"title":"A high-performance current-mode precision full-wave rectifier based on BiCMOS-CCCDBAs","authors":"P. Silapan, W. Jaikla, M. Siripruchyanun","doi":"10.1109/APCCAS.2008.4746313","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746313","url":null,"abstract":"This article introduces a novel version for implementing current-mode precision full-wave rectifier. The features of the proposed circuit are that: it can rectify and amplify current signal with controllable output magnitude via an input bias current: the output current is free from temperature variation. In addition, direction of the output current signal can be arbitrarily controlled by controlled current in the circuit to be either positive or negative without changing circuit topology, which differs from the previous literatures. Circuit description merely consists of 3 BiCMOS CCCDBAs, without any passive component. The performances of the proposed circuit are investigated through PSPICE. They show that the proposed circuit can function as a current-mode precision full-wave rectifier, where input current range from -240 muA to 240 muA can be achieved at plusmn1.5 V power supplies. The maximum power consumption is 11.8 mW. In addition, the highest frequency is restricted at up to megahertz range.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129174371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746029
S. Pei, Jian-Jiun Ding, Jiun-De Huang, Guo-Cyuan Guo
In this paper, we define the short-response Hilbert transform (SRHLT) and use it for edge detection. The SRHLT has a parameter b. When b = 0, it becomes the Hilbert transform (HLT). When b is infinite, it becomes differentiation. Many edge detection algorithms are based on differentiation. However, they are sensitive to noise. By contrast, when using the HLT for edge detection, the noise is reduced but the resolution is poor. The proposed SRHLT in this paper can compromise the advantages of differentiation and HLTs. It is robust to noise and can simultaneously distinguish edges from non-edge regions very successfully.
{"title":"Short response Hilbert transform for edge detection","authors":"S. Pei, Jian-Jiun Ding, Jiun-De Huang, Guo-Cyuan Guo","doi":"10.1109/APCCAS.2008.4746029","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746029","url":null,"abstract":"In this paper, we define the short-response Hilbert transform (SRHLT) and use it for edge detection. The SRHLT has a parameter b. When b = 0, it becomes the Hilbert transform (HLT). When b is infinite, it becomes differentiation. Many edge detection algorithms are based on differentiation. However, they are sensitive to noise. By contrast, when using the HLT for edge detection, the noise is reduced but the resolution is poor. The proposed SRHLT in this paper can compromise the advantages of differentiation and HLTs. It is robust to noise and can simultaneously distinguish edges from non-edge regions very successfully.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746001
Lifei Chen, Q. Jiang, Shengrui Wang
As an important issue in cluster analysis, cluster validation is the process of evaluating performance of clustering algorithms under varying input conditions. Many existing methods address clustering results of low-dimensional data. This paper presents new solution to the problem of cluster validation for subspace clustering on high dimensional data. We first propose two new measurements for the intra-cluster compactness and inter-cluster separation of subspace clusters. Based on these measurements and the conventional indices, three new cluster validity indices that can be applied to subspace clustering are presented. Combining with a soft subspace clustering algorithm, the new indices are used to determine the number of clusters in high dimensional data. The experimental results on synthetic and real world datasets have shown their effectiveness.
{"title":"Cluster validation for subspace clustering on high dimensional data","authors":"Lifei Chen, Q. Jiang, Shengrui Wang","doi":"10.1109/APCCAS.2008.4746001","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746001","url":null,"abstract":"As an important issue in cluster analysis, cluster validation is the process of evaluating performance of clustering algorithms under varying input conditions. Many existing methods address clustering results of low-dimensional data. This paper presents new solution to the problem of cluster validation for subspace clustering on high dimensional data. We first propose two new measurements for the intra-cluster compactness and inter-cluster separation of subspace clusters. Based on these measurements and the conventional indices, three new cluster validity indices that can be applied to subspace clustering are presented. Combining with a soft subspace clustering algorithm, the new indices are used to determine the number of clusters in high dimensional data. The experimental results on synthetic and real world datasets have shown their effectiveness.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122966452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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