Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706460
Z. H. A. Rahman, M. H. M. Md Khir, Z. A. Burhanudin, A. Rahman, W. A. W. Jamil
This paper presents the design of micro-scale thermoelectric generator (TEG) using CMOS-MEMS technology. Electrical energy is obtained by means of thermal energy harvesting technique. Thermal energy harvesting has become a promising solution to power up low power system such as wireless sensor networks (WSNs) and portable devices. Thermal energy or heat which is widely available in natural and also human made environments can be converted into electrical power using Seebeck effect. The proposed TEG is compatible with standard CMOS technology which consists of p-doped and n-doped polysilicon thermocouples arranged electrically in series and thermally in parallel. In order to increase the temperature difference between the hot and cold parts, a layer of heat sink with low thermal conductivity material is insulated at the cold part area. Trenches are included in-between each thermocouple to disperse heat efficiently to ambient air. Post-CMOS process is included to illustrate proper procedures for a successful device release. Simulation results show that with temperature difference of 10 K, output voltage and power attained is 301 mV and 45 μW, respectively.
{"title":"Design of CMOS-MEMS based thermoelectric generator","authors":"Z. H. A. Rahman, M. H. M. Md Khir, Z. A. Burhanudin, A. Rahman, W. A. W. Jamil","doi":"10.1109/RSM.2013.6706460","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706460","url":null,"abstract":"This paper presents the design of micro-scale thermoelectric generator (TEG) using CMOS-MEMS technology. Electrical energy is obtained by means of thermal energy harvesting technique. Thermal energy harvesting has become a promising solution to power up low power system such as wireless sensor networks (WSNs) and portable devices. Thermal energy or heat which is widely available in natural and also human made environments can be converted into electrical power using Seebeck effect. The proposed TEG is compatible with standard CMOS technology which consists of p-doped and n-doped polysilicon thermocouples arranged electrically in series and thermally in parallel. In order to increase the temperature difference between the hot and cold parts, a layer of heat sink with low thermal conductivity material is insulated at the cold part area. Trenches are included in-between each thermocouple to disperse heat efficiently to ambient air. Post-CMOS process is included to illustrate proper procedures for a successful device release. Simulation results show that with temperature difference of 10 K, output voltage and power attained is 301 mV and 45 μW, respectively.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706553
S. M. Sultan, P. Ashburn, R. Ismail, H. Chong
Top-down Zinc Oxide (ZnO) nanowire FETs have been fabricated using conventional photolithography, ZnO atomic layer deposition (ALD) and dry etching. This paper investigates the hysteresis characteristics of these transistors at different gate bias sweep rates. Hysteresis is a measure of charge trapping and detrapping activities on the nanowire surface. Maximum hysteresis width obtained for this top-down ZnO NWFET device when measured in air was 2.2 V. This value is smaller compared to other bottom up devices which indicates better interface quality between ZnO nanowire/SiO2 interface. Subsequently, this is an important feature in order to produce reliable platform for electronic applications particularly sensing applications.
{"title":"Hysteresis behaviour of top-down fabricated ZnO nanowire transistors","authors":"S. M. Sultan, P. Ashburn, R. Ismail, H. Chong","doi":"10.1109/RSM.2013.6706553","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706553","url":null,"abstract":"Top-down Zinc Oxide (ZnO) nanowire FETs have been fabricated using conventional photolithography, ZnO atomic layer deposition (ALD) and dry etching. This paper investigates the hysteresis characteristics of these transistors at different gate bias sweep rates. Hysteresis is a measure of charge trapping and detrapping activities on the nanowire surface. Maximum hysteresis width obtained for this top-down ZnO NWFET device when measured in air was 2.2 V. This value is smaller compared to other bottom up devices which indicates better interface quality between ZnO nanowire/SiO2 interface. Subsequently, this is an important feature in order to produce reliable platform for electronic applications particularly sensing applications.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124416381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706572
S. Soeung, N. B. Z. Ali, M. H. M. Md Khir
This paper presents the 3D electromagnetic simulation investigation of magnetic field behavior of faulty and fault free interconnects in Computer Simulation Technology (CST) Microwave Studio. The interconnects have been modeled in three conditions: short fault, open fault, and normal. The simulations of interconnect fault inspection have been performed on two different observations. First on the induced magnetic field intensity behavior where the conductive lines are excited by voltage ports. The induced magnetic field intensities are detected by virtual probes available in CST at the location of 3 mm above the lines. Second observation is on the changes of the induced voltages across the eddy current coil sensor. The interconnects are exposed to an alternating magnetic field generating secondary magnetic field. This field induces changes of voltage which are detected by eddy current sensor placed at 1.5 mm above the interconnects. The simulation results generated from both cases have shown that in the presence of the short faults on interconnect, the peak magnetic field intensity and induced voltage are higher compared to the normal or reference interconnect of 0.708 mV. Whereas, open or discontinuity faults on the lines induced lower magnetic field intensity and voltage compared to the normal lines voltage of 0.708 mV.
{"title":"3D electromagnetic simulation of interconnect fault inspection based on magnetic field behavior","authors":"S. Soeung, N. B. Z. Ali, M. H. M. Md Khir","doi":"10.1109/RSM.2013.6706572","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706572","url":null,"abstract":"This paper presents the 3D electromagnetic simulation investigation of magnetic field behavior of faulty and fault free interconnects in Computer Simulation Technology (CST) Microwave Studio. The interconnects have been modeled in three conditions: short fault, open fault, and normal. The simulations of interconnect fault inspection have been performed on two different observations. First on the induced magnetic field intensity behavior where the conductive lines are excited by voltage ports. The induced magnetic field intensities are detected by virtual probes available in CST at the location of 3 mm above the lines. Second observation is on the changes of the induced voltages across the eddy current coil sensor. The interconnects are exposed to an alternating magnetic field generating secondary magnetic field. This field induces changes of voltage which are detected by eddy current sensor placed at 1.5 mm above the interconnects. The simulation results generated from both cases have shown that in the presence of the short faults on interconnect, the peak magnetic field intensity and induced voltage are higher compared to the normal or reference interconnect of 0.708 mV. Whereas, open or discontinuity faults on the lines induced lower magnetic field intensity and voltage compared to the normal lines voltage of 0.708 mV.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"23 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125290954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706459
M. Ahmad, M. H. M. Md Khir, J. Dennis
Conversion of the mechanical vibration into electrical energy has been found feasible with MEMS (Micro-Electro-Mechanical-System) electrostatic energy harvesting method. The electrostatic energy harvesting device is fabricated on a silicon wafer for use on miniaturize applications. This paper presents the detail fabrication processes of the electrostatic energy harvester components, i.e. the Trapezoidal electrodes and Electrets. The trapezoidal electrodes structure comprises of the seismic mass, serpentine beams and Aluminum electrodes whereas the electrets is made up of Silicon Dioxides (SiO2). The energy harvester components are designed with Cadence Virtuoso software and later fabricated at the wafer foundry leveraging the 0.35 μm CMOS processes on 200 mm silicon wafers. The trapezoidal electrodes and electrets fabrications went through seven and two masking steps respectively. Performance of the electrets material are evaluated with Corona charging method. Characterization results show that the CVD oxide exhibits good charge retention capability, hence is recommended for application as electrets material on the vibration-based electrostatic energy harvester.
{"title":"Fabrication of the Trapezoidal electrodes and Electrets material for electrostatic energy harvester","authors":"M. Ahmad, M. H. M. Md Khir, J. Dennis","doi":"10.1109/RSM.2013.6706459","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706459","url":null,"abstract":"Conversion of the mechanical vibration into electrical energy has been found feasible with MEMS (Micro-Electro-Mechanical-System) electrostatic energy harvesting method. The electrostatic energy harvesting device is fabricated on a silicon wafer for use on miniaturize applications. This paper presents the detail fabrication processes of the electrostatic energy harvester components, i.e. the Trapezoidal electrodes and Electrets. The trapezoidal electrodes structure comprises of the seismic mass, serpentine beams and Aluminum electrodes whereas the electrets is made up of Silicon Dioxides (SiO2). The energy harvester components are designed with Cadence Virtuoso software and later fabricated at the wafer foundry leveraging the 0.35 μm CMOS processes on 200 mm silicon wafers. The trapezoidal electrodes and electrets fabrications went through seven and two masking steps respectively. Performance of the electrets material are evaluated with Corona charging method. Characterization results show that the CVD oxide exhibits good charge retention capability, hence is recommended for application as electrets material on the vibration-based electrostatic energy harvester.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706476
N. S. Nadzri, V. Retnasamy, Z. Sauli, S. Taniselass, T. Mei
The fundamental principles of fluid flow characteristics is vital in a microfluidic system. The integration of fluid flow exploitation and fabrication technologycreates good platform in various fields such as biomedical, clinical instrumentation and cell culture system. One of the important parameter to characterize a fluid is its pressure. In this article, characterization of pressure distribution in forward facing step (FFS) microchannel has been investigated using CFD-Ansys software. The primary goal of this research is to study the effect of the step height in FFS configuration on fluid flow pressure distribution. Hence, three different step heights have been employed as measurement comparison. Pressure drop trend was observed across the microchannel. The highest step height showed the highest pressure drop.
{"title":"Pressure distribution characterization in forward facing step (FFS) microchannel using Ansys","authors":"N. S. Nadzri, V. Retnasamy, Z. Sauli, S. Taniselass, T. Mei","doi":"10.1109/RSM.2013.6706476","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706476","url":null,"abstract":"The fundamental principles of fluid flow characteristics is vital in a microfluidic system. The integration of fluid flow exploitation and fabrication technologycreates good platform in various fields such as biomedical, clinical instrumentation and cell culture system. One of the important parameter to characterize a fluid is its pressure. In this article, characterization of pressure distribution in forward facing step (FFS) microchannel has been investigated using CFD-Ansys software. The primary goal of this research is to study the effect of the step height in FFS configuration on fluid flow pressure distribution. Hence, three different step heights have been employed as measurement comparison. Pressure drop trend was observed across the microchannel. The highest step height showed the highest pressure drop.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125411424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706543
Wong King Kiat, R. Ismail, M. Ahmadi
A two-dimensional honeycomb lattice of single layer of carbon called graphene is a very interesting material that exhibits high electron mobility at room temperature. This unique property holds a promising potential to replace current silicon technology in the future. However graphene is a gapless material which is a major problem in semiconductor economy. To overcome this problem graphene nanoribbon is introduced where the band-gap of graphene nanoribbon can be easily obtained by controlling the width of the ribbon. In this paper, schottky barrier lowering effect on graphene nanoribbon based schottky barrier diode is investigated. Schottky barrier effect alters the schottky barrier height and also the overall performance of schottky barrier diode. The study of the relationship between applied voltage and schottky barrier lowering effect for non-degenerate region and degenerate region is presented. As the applied voltage is increased, the schottky barrier lowering is also increasing but the increment only increases until certain point. After that, effect starts to decline due to the ambipolar characteristic of graphene nanoribbon. Degenerate region shows higher value of schottky barrier lowering compared to non-degenerate region is reported. Besides that, higher temperature value resulted in higher schottky barrier lowering effect is also reported.
{"title":"Schottky barrier lowering effect on graphene nanoribbon based schottky diode","authors":"Wong King Kiat, R. Ismail, M. Ahmadi","doi":"10.1109/RSM.2013.6706543","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706543","url":null,"abstract":"A two-dimensional honeycomb lattice of single layer of carbon called graphene is a very interesting material that exhibits high electron mobility at room temperature. This unique property holds a promising potential to replace current silicon technology in the future. However graphene is a gapless material which is a major problem in semiconductor economy. To overcome this problem graphene nanoribbon is introduced where the band-gap of graphene nanoribbon can be easily obtained by controlling the width of the ribbon. In this paper, schottky barrier lowering effect on graphene nanoribbon based schottky barrier diode is investigated. Schottky barrier effect alters the schottky barrier height and also the overall performance of schottky barrier diode. The study of the relationship between applied voltage and schottky barrier lowering effect for non-degenerate region and degenerate region is presented. As the applied voltage is increased, the schottky barrier lowering is also increasing but the increment only increases until certain point. After that, effect starts to decline due to the ambipolar characteristic of graphene nanoribbon. Degenerate region shows higher value of schottky barrier lowering compared to non-degenerate region is reported. Besides that, higher temperature value resulted in higher schottky barrier lowering effect is also reported.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128666914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706483
A. Dehzangi, F. Larki, B. Majlis, M. Hamidon, P. Menon, A. Jalar, M. Islam, S. M. Md Ali
Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.
{"title":"Numerical investigation of channel width variation in junctionless transistors performance","authors":"A. Dehzangi, F. Larki, B. Majlis, M. Hamidon, P. Menon, A. Jalar, M. Islam, S. M. Md Ali","doi":"10.1109/RSM.2013.6706483","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706483","url":null,"abstract":"Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122858679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706489
A. Maheran, P. Menon, I. Ahmad, Z. Yusoff
In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of Vth. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.
{"title":"Threshold voltage optimization in a 22nm High-k/Salicide PMOS device","authors":"A. Maheran, P. Menon, I. Ahmad, Z. Yusoff","doi":"10.1109/RSM.2013.6706489","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706489","url":null,"abstract":"In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of Vth. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706555
R. A. Rahim, B. Bais, B. Majlis, Sheik Fareed
In this paper, an optimization on the mechanical behaviour of silicon piezoresistive microcantilever (PRM) has been carried out. Using CoventorWare 2008, the mechanical behavior of the PRM structure was investigated by studying few contributing factors that affect the performance of the device. The performance was represented with mechanical displacement of the suspended PRM sensor with regards to various factors such as the microcantilever shape and geometrical dimensions, the materials and the effect of incorporating stress concentration region (SCR) on the device structure. In this research work, a single-layer piezoresistive microcantilever in which both piezoresistor and microcantilever structures are made of the same material of single-crystalline silicon is utilized. Two dual-leg shaped piezoresistive microcantilever designs have been proposed: piezoresistive microcantilever with and without a square hole. From the simulation results, it can be seen that the maximum displacement is observed at maximum microcantilever's length and minimum thickness. The incorporation of a square hole as an SCR not only shows a significant increase in Mises stress value but also in the displacement of the microcantilever structure. Single-crystalline Si was chosen as the device material for the fabrication of single-layer piezoresistive microcantilever due to its high piezoresistive coefficients and thermal conductivity.
{"title":"Design optimization of MEMS dual-leg shaped piezoresistive microcantilever","authors":"R. A. Rahim, B. Bais, B. Majlis, Sheik Fareed","doi":"10.1109/RSM.2013.6706555","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706555","url":null,"abstract":"In this paper, an optimization on the mechanical behaviour of silicon piezoresistive microcantilever (PRM) has been carried out. Using CoventorWare 2008, the mechanical behavior of the PRM structure was investigated by studying few contributing factors that affect the performance of the device. The performance was represented with mechanical displacement of the suspended PRM sensor with regards to various factors such as the microcantilever shape and geometrical dimensions, the materials and the effect of incorporating stress concentration region (SCR) on the device structure. In this research work, a single-layer piezoresistive microcantilever in which both piezoresistor and microcantilever structures are made of the same material of single-crystalline silicon is utilized. Two dual-leg shaped piezoresistive microcantilever designs have been proposed: piezoresistive microcantilever with and without a square hole. From the simulation results, it can be seen that the maximum displacement is observed at maximum microcantilever's length and minimum thickness. The incorporation of a square hole as an SCR not only shows a significant increase in Mises stress value but also in the displacement of the microcantilever structure. Single-crystalline Si was chosen as the device material for the fabrication of single-layer piezoresistive microcantilever due to its high piezoresistive coefficients and thermal conductivity.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126661534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706504
R. Vairavan, Z. Sauli, V. Retnasamy
Thermal management is a prime concern in the LED lighting industry as the reliability and performance of the LED is significantly affected by the heat produced within the LED package. The evaluation of junction temperature is one of the methods used to determine the heat dissipation of a LED. This paper demonstrates the heat dissipation of a single chip high power LED package through simulation. The junction temperature and the stress of the LED chip with cylindrical aluminum heat slug were assessed. Simulation was carried at natural convection condition using Ansys version 11. The evaluation was done at input power of 0.1 W and 1 W. Result showed that at input power of 1 W, the maximum junction temperature of the LED chip is 121.71°C with Von Mises stress of 277.70 MPa.
热管理是LED照明行业主要关注的问题，因为LED封装内产生的热量对LED的可靠性和性能有很大影响。结温的评估是用于确定LED散热的方法之一。本文通过仿真验证了单芯片大功率LED封装的散热性能。对带圆柱形铝热段的LED芯片的结温和应力进行了评估。利用Ansys version 11在自然对流条件下进行仿真。在0.1 W和1w的输入功率下进行评估。结果表明，在输入功率为1 W时，LED芯片的最高结温为121.71℃，Von Mises应力为277.70 MPa。
{"title":"High power LED heat dissipation analysis using cylindrical Al based slug using Ansys","authors":"R. Vairavan, Z. Sauli, V. Retnasamy","doi":"10.1109/RSM.2013.6706504","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706504","url":null,"abstract":"Thermal management is a prime concern in the LED lighting industry as the reliability and performance of the LED is significantly affected by the heat produced within the LED package. The evaluation of junction temperature is one of the methods used to determine the heat dissipation of a LED. This paper demonstrates the heat dissipation of a single chip high power LED package through simulation. The junction temperature and the stress of the LED chip with cylindrical aluminum heat slug were assessed. Simulation was carried at natural convection condition using Ansys version 11. The evaluation was done at input power of 0.1 W and 1 W. Result showed that at input power of 1 W, the maximum junction temperature of the LED chip is 121.71°C with Von Mises stress of 277.70 MPa.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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