Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706576
Siti Khatijah Md Saad, A. Umar, S. Nafisah, M. Salleh, B. Majlis
The effect of morphology of anatase TiO2 nanoparticles as photoanode in dye sensitized solar cells (DSSCs) has been investigated. Two types of TiO2 nanostructures, namely nanograss and nanospherical particles, used in this study have been prepared via liquid phase deposition (LPD) method. Electrochemical impedance spectroscopy (EIS) analysis of DSSCs device with a sandwich structure of ITO/TiO2/dye/electrolyte/ Pt film indicated that the device utilizing TiO2 nanograss exhibited the lower in charge transfer resistance (Rct), of 49.1 Ω. This might be due to the high-porous characteristic of TiO2 nanograss compared to the nanospherical particles that provides facile charge transport and ion diffusion. Power conversion efficiency as high as 0.97% has been recorded from the device utilizing nanograss of TiO2, which was 3 times higher compared to TiO2 nanospherical particles of which its conversion efficiency was only 0.33%.
{"title":"Effect of TiO2 nanostructure's shape on the DSSCs performance","authors":"Siti Khatijah Md Saad, A. Umar, S. Nafisah, M. Salleh, B. Majlis","doi":"10.1109/RSM.2013.6706576","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706576","url":null,"abstract":"The effect of morphology of anatase TiO2 nanoparticles as photoanode in dye sensitized solar cells (DSSCs) has been investigated. Two types of TiO2 nanostructures, namely nanograss and nanospherical particles, used in this study have been prepared via liquid phase deposition (LPD) method. Electrochemical impedance spectroscopy (EIS) analysis of DSSCs device with a sandwich structure of ITO/TiO2/dye/electrolyte/ Pt film indicated that the device utilizing TiO2 nanograss exhibited the lower in charge transfer resistance (Rct), of 49.1 Ω. This might be due to the high-porous characteristic of TiO2 nanograss compared to the nanospherical particles that provides facile charge transport and ion diffusion. Power conversion efficiency as high as 0.97% has been recorded from the device utilizing nanograss of TiO2, which was 3 times higher compared to TiO2 nanospherical particles of which its conversion efficiency was only 0.33%.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706473
I. M. Rusni, A. Ismail, A. Alhawari, M. Hamidon, N. Yusof, M. Isa
In general, a classical Split Ring Resonator (SRR) structure exhibits high Q-factor based on deeper and sharper transmission dips at resonance as well as produce high electric field density at the gaps. It is believed, by introducing more gaps, a strong and localized E-field will be obtained in the area between the split gaps. Based on these features, three types of rectangular multiple Split Ring Resonators (SRRs) were proposed to resonate in the frequency range of 3-7 GHz and simulated using Computer Simulation Technology (CST) Microwave Studio to determine the transmission characteristics and the resonance frequency. A Nicolson-Ross-Weir (NRW) technique is used to retrieve the effective parameters from the resultant S-parameter. It is shown that the resonance frequency of investigated structures falls in a frequency region in which the real part of permeability is negative. Later, the simulated results were investigated and the performances as well as the size of each unit cell itself were compared. Simulation for three different type of dielectric samples were also presented to demonstrate that the proposed structure may be well suited for bio-sensing.
{"title":"Centered-gap and aligned-gap multiple split ring resonator for bio-sensing application","authors":"I. M. Rusni, A. Ismail, A. Alhawari, M. Hamidon, N. Yusof, M. Isa","doi":"10.1109/RSM.2013.6706473","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706473","url":null,"abstract":"In general, a classical Split Ring Resonator (SRR) structure exhibits high Q-factor based on deeper and sharper transmission dips at resonance as well as produce high electric field density at the gaps. It is believed, by introducing more gaps, a strong and localized E-field will be obtained in the area between the split gaps. Based on these features, three types of rectangular multiple Split Ring Resonators (SRRs) were proposed to resonate in the frequency range of 3-7 GHz and simulated using Computer Simulation Technology (CST) Microwave Studio to determine the transmission characteristics and the resonance frequency. A Nicolson-Ross-Weir (NRW) technique is used to retrieve the effective parameters from the resultant S-parameter. It is shown that the resonance frequency of investigated structures falls in a frequency region in which the real part of permeability is negative. Later, the simulated results were investigated and the performances as well as the size of each unit cell itself were compared. Simulation for three different type of dielectric samples were also presented to demonstrate that the proposed structure may be well suited for bio-sensing.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706530
N. D. Md Sin, A. Shafura, M. H. Mamat, A. Mohamad, M. Rusop
SnO2 nanoparticle thin film has been synthesized by using thermal chemical vapor deposition (CVD). The SnO2 nanoparticle were growth on Au catalyst at different substrate temperature (400~550oC). The surface morphology of were characterized using field emission scanning electron microscopy (FESEM). The sensing properties of SnO2 nanoparticle thin film were examined using two point probe current-voltage (I-V) measurement (Keithley 2400). Heavily distribution of SnO2 nanoparticle thin film at 450°C that reveal from the FESEM image. The higher sensitivity of SnO2 nanoparticle thin film was performed good at 450°C compare to others samples with 45 ratio. The response and recovery of SnO2 nanoparticle thin film were 485 s and 24s respectively.
{"title":"Humidity sensor based on SnO2 nanoparticle thin film synthesized by thermal chemical vapor deposition (CVD)","authors":"N. D. Md Sin, A. Shafura, M. H. Mamat, A. Mohamad, M. Rusop","doi":"10.1109/RSM.2013.6706530","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706530","url":null,"abstract":"SnO2 nanoparticle thin film has been synthesized by using thermal chemical vapor deposition (CVD). The SnO2 nanoparticle were growth on Au catalyst at different substrate temperature (400~550oC). The surface morphology of were characterized using field emission scanning electron microscopy (FESEM). The sensing properties of SnO2 nanoparticle thin film were examined using two point probe current-voltage (I-V) measurement (Keithley 2400). Heavily distribution of SnO2 nanoparticle thin film at 450°C that reveal from the FESEM image. The higher sensitivity of SnO2 nanoparticle thin film was performed good at 450°C compare to others samples with 45 ratio. The response and recovery of SnO2 nanoparticle thin film were 485 s and 24s respectively.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115921360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706468
M. Ya, A. Nordin, N. Soin
This paper presents the design and analysis of a radio frequency (RF) micro-electromechanical system (MEMS) switch with low actuation voltage using MIMOS 0.35μm complementary metal oxide semiconductor (CMOS) process. The advantage of this RF MEMS switch is very low actuation voltage design which is compatible with other CMOS circuit without employing a separate on-chip voltage source or charge pump unit. Moreover, using CMOS technology to design can highly simplify the fabrication process, reduce the cost and improve the device performance. The RF MEMS switch is a capacitive shunt-connection type device which uses four folded beams to support a big membrane above the signal transmission line. The pull-in voltage, von Mises stress distribution and vertical displacement of the membrane, up-state and down-state capacitances, as well as the switch impedance is calculated and analyzed by finite element modelling (FEM) simulation.
{"title":"Design and analysis of a low-voltage electrostatic actuated RF CMOS-MEMS switch","authors":"M. Ya, A. Nordin, N. Soin","doi":"10.1109/RSM.2013.6706468","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706468","url":null,"abstract":"This paper presents the design and analysis of a radio frequency (RF) micro-electromechanical system (MEMS) switch with low actuation voltage using MIMOS 0.35μm complementary metal oxide semiconductor (CMOS) process. The advantage of this RF MEMS switch is very low actuation voltage design which is compatible with other CMOS circuit without employing a separate on-chip voltage source or charge pump unit. Moreover, using CMOS technology to design can highly simplify the fabrication process, reduce the cost and improve the device performance. The RF MEMS switch is a capacitive shunt-connection type device which uses four folded beams to support a big membrane above the signal transmission line. The pull-in voltage, von Mises stress distribution and vertical displacement of the membrane, up-state and down-state capacitances, as well as the switch impedance is calculated and analyzed by finite element modelling (FEM) simulation.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132973839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706540
I. Saad, C. B. Seng, H. M. Zuhir, B. Nurmin, A. M. Khairul, B. Ghosh, R. Ismail, U. Hashim
Single Channel (SC) and Dual Channel (DC) Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS) has been successfully simulated and analyzed in this paper. Found out that SC VESIMOS operate in conventional MOSFET mode at VDS = 1.75V, with 10% to 30% Ge mole fraction. However for Ge=50%, it's operated in Impact Ionization (II) mode with fast switching speed of subthreshold value, S=9.8 mV/dec. A better performance in threshold voltage, VTH, S value and ION/IOFF ratio were found in DC VESIMOS as compared to SC VESIMOS. The VTH=0.6V, S=10.98 mV/dec and ION/IOFF = 1×1013 were measured in DC VESIMOS with Ge=30% that clarify the advantage of DC utilization on VESIMOS device. These improvements were mainly due to the enhancement of electron mobility from 600 m2/V-s (first channel) to 1400 m2/V-s (second channel). The electron mobility was increased due to the splitting of conduction band valley into six fold where the electron mass are reduced in out of plane direction and thus enhanced the mobility of electron.
{"title":"Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)","authors":"I. Saad, C. B. Seng, H. M. Zuhir, B. Nurmin, A. M. Khairul, B. Ghosh, R. Ismail, U. Hashim","doi":"10.1109/RSM.2013.6706540","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706540","url":null,"abstract":"Single Channel (SC) and Dual Channel (DC) Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS) has been successfully simulated and analyzed in this paper. Found out that SC VESIMOS operate in conventional MOSFET mode at V<sub>DS</sub> = 1.75V, with 10% to 30% Ge mole fraction. However for Ge=50%, it's operated in Impact Ionization (II) mode with fast switching speed of subthreshold value, S=9.8 mV/dec. A better performance in threshold voltage, V<sub>TH</sub>, S value and I<sub>ON</sub>/I<sub>OFF</sub> ratio were found in DC VESIMOS as compared to SC VESIMOS. The V<sub>TH</sub>=0.6V, S=10.98 mV/dec and I<sub>ON</sub>/I<sub>OFF</sub> = 1×10<sup>13</sup> were measured in DC VESIMOS with Ge=30% that clarify the advantage of DC utilization on VESIMOS device. These improvements were mainly due to the enhancement of electron mobility from 600 m<sup>2</sup>/V-s (first channel) to 1400 m<sup>2</sup>/V-s (second channel). The electron mobility was increased due to the splitting of conduction band valley into six fold where the electron mass are reduced in out of plane direction and thus enhanced the mobility of electron.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131026584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706495
K. Ashraf, M. H. M. Md Khir, J. Dennis, Z. Baharudin
With the fast development in the ubiquitous computing and wireless sensing technologies, a new era of smart cities is evolving. Future smart cities will gather sensory data, needed for effective management of the city, using wireless sensor networks. Exhaustive power sources such as batteries need periodic replacement and hence increase the cost of ownership of wireless sensor network. On the other hand, renewable vibration energy is found in abundance in many target environments of wireless sensor network, which can be harvested to power up the sensor node. The average power of a vibration energy harvester strongly depends on the frequency of vibration and quality factor of the harvester. Unfortunately, most of the environmental vibrations occur in a low frequency range of few tens of Hz. This paper analytically investigates the challenges in designing a low frequency energy harvester with a high quality factor.
{"title":"Frequency dependence of quality factor in vibration energy harvesting","authors":"K. Ashraf, M. H. M. Md Khir, J. Dennis, Z. Baharudin","doi":"10.1109/RSM.2013.6706495","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706495","url":null,"abstract":"With the fast development in the ubiquitous computing and wireless sensing technologies, a new era of smart cities is evolving. Future smart cities will gather sensory data, needed for effective management of the city, using wireless sensor networks. Exhaustive power sources such as batteries need periodic replacement and hence increase the cost of ownership of wireless sensor network. On the other hand, renewable vibration energy is found in abundance in many target environments of wireless sensor network, which can be harvested to power up the sensor node. The average power of a vibration energy harvester strongly depends on the frequency of vibration and quality factor of the harvester. Unfortunately, most of the environmental vibrations occur in a low frequency range of few tens of Hz. This paper analytically investigates the challenges in designing a low frequency energy harvester with a high quality factor.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706490
Nurul Izzati Mohammad Noh, K. A. Yusof, M. Zolkapli, A. Abdullah, W. Abdullah, S. H. Herman
The effect of channel width-to-length (W/L) ratio on MOSFET-ISFET structures was investigated from simulation and experimental approach. A metal-oxide-semiconductor field-effect-transistor (MOSFET) has been adopted to investigate the isothermal point of an ion-sensitive FET (ISFET), which is needed to suit the readout interfacing circuit of an ISFET sensor. The MOSFET structure with different W/L ratio has been characterized in order to see the effect of W/L ratio to the isothermal point. The Keithley 236 Parameter Analyzer and Semi-auto prober micromanipulator system were used to measure the drain-source current (IDS) versus gate to source voltage (VGS) curves at various temperatures from 30 °C to 60 °C. The simulation result showed that the reduction of W/L ratio can decrease the isothermal point and this was proven by the actual measurement.
{"title":"Effect of channel width-to-length ratio on isothermal point of MOSFET-ISFET structure","authors":"Nurul Izzati Mohammad Noh, K. A. Yusof, M. Zolkapli, A. Abdullah, W. Abdullah, S. H. Herman","doi":"10.1109/RSM.2013.6706490","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706490","url":null,"abstract":"The effect of channel width-to-length (W/L) ratio on MOSFET-ISFET structures was investigated from simulation and experimental approach. A metal-oxide-semiconductor field-effect-transistor (MOSFET) has been adopted to investigate the isothermal point of an ion-sensitive FET (ISFET), which is needed to suit the readout interfacing circuit of an ISFET sensor. The MOSFET structure with different W/L ratio has been characterized in order to see the effect of W/L ratio to the isothermal point. The Keithley 236 Parameter Analyzer and Semi-auto prober micromanipulator system were used to measure the drain-source current (IDS) versus gate to source voltage (VGS) curves at various temperatures from 30 °C to 60 °C. The simulation result showed that the reduction of W/L ratio can decrease the isothermal point and this was proven by the actual measurement.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"9 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706474
U. Abidin, B. Majlis, J. Yunas
Development of integrated ferromagnetic materials structure as magnetic core is crucial for high performance MEMS sensors and actuators. A core structure is able to improve the magnetic flux linkage and concentrate the magnetic flux density in the magnetic device resulting high magnetic field generation. Previous research has utilized various ferromagnetic materials of different structures embedded into the silicon substrate as MEMS magnetic core. This paper presents fabrication of V-shaped magnetic core by anisotropic wet etching of 30 percent potassium hydroxide (KOH) at 75 °C to produce V-shaped silicon cavity structure. Filling process of Permalloy (Ni80Fe20) into the cavity is done by DC electroplating technique. Low current density of 10 mA/cm2 is used to electrodeposit Ni80Fe20 magnetic film in this study. Saccharin addition into the electrolyte composition produced a bright and crack free structure as internal stress in the electrodeposited film is reduced. This effect is essential to have good magnetic properties of the magnetic core. Thicker structure of electroplated Ni80Fe20 is observed at the sharp edges of the V-shaped cavity tip. The reason of this effect to happen is because high current flux density occurrence at those edges. From this work, fabrication of V-shaped Ni80Fe20 magnetic core has been successfully demonstrated. This magnetic core is expected to give superior magnetic performance for on chip MEMS device applications.
{"title":"Ni80Fe20 V-shaped magnetic core for high performance MEMS sensors and actuators","authors":"U. Abidin, B. Majlis, J. Yunas","doi":"10.1109/RSM.2013.6706474","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706474","url":null,"abstract":"Development of integrated ferromagnetic materials structure as magnetic core is crucial for high performance MEMS sensors and actuators. A core structure is able to improve the magnetic flux linkage and concentrate the magnetic flux density in the magnetic device resulting high magnetic field generation. Previous research has utilized various ferromagnetic materials of different structures embedded into the silicon substrate as MEMS magnetic core. This paper presents fabrication of V-shaped magnetic core by anisotropic wet etching of 30 percent potassium hydroxide (KOH) at 75 °C to produce V-shaped silicon cavity structure. Filling process of Permalloy (Ni80Fe20) into the cavity is done by DC electroplating technique. Low current density of 10 mA/cm2 is used to electrodeposit Ni80Fe20 magnetic film in this study. Saccharin addition into the electrolyte composition produced a bright and crack free structure as internal stress in the electrodeposited film is reduced. This effect is essential to have good magnetic properties of the magnetic core. Thicker structure of electroplated Ni80Fe20 is observed at the sharp edges of the V-shaped cavity tip. The reason of this effect to happen is because high current flux density occurrence at those edges. From this work, fabrication of V-shaped Ni80Fe20 magnetic core has been successfully demonstrated. This magnetic core is expected to give superior magnetic performance for on chip MEMS device applications.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115665754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706566
H. Wong
The on-chip interconnects technology has faced a number of challenges in recent years. With the significant advancement in silicon integrated photonics, possibility of introducing on-chip optical interconnects for future gigascale circuits has been explored intensely in the last decade. The successful development of on-chip optical interconnects will be one of the major moves for the next technology revolution for the integrated circuits. Over the years, technology for making optical micro-waveguides based on CMOS processes has been developed and there are several proposals for making Si-based light sources. This talk highlights some attempts reported recently for making waveguide and light emitting devices based on the conventional CMOS processes. These technologies look promising for the on-chip optical interconnects in future gigascale CMOS technology.
{"title":"Silicon photonics for microelectronic op-chip optical interconnects","authors":"H. Wong","doi":"10.1109/RSM.2013.6706566","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706566","url":null,"abstract":"The on-chip interconnects technology has faced a number of challenges in recent years. With the significant advancement in silicon integrated photonics, possibility of introducing on-chip optical interconnects for future gigascale circuits has been explored intensely in the last decade. The successful development of on-chip optical interconnects will be one of the major moves for the next technology revolution for the integrated circuits. Over the years, technology for making optical micro-waveguides based on CMOS processes has been developed and there are several proposals for making Si-based light sources. This talk highlights some attempts reported recently for making waveguide and light emitting devices based on the conventional CMOS processes. These technologies look promising for the on-chip optical interconnects in future gigascale CMOS technology.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122010008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706462
B. S. Rao, M. Nurfaiz, U. Hashim
One of the delicate processes in semiconductor microfabrication is the photolithography. It is the process that sets the design dimensions on various parts of the device. In order to complete this process, two requirements need to be satisfied. First is to create, the exact dimensions and pattern as established in design phase, which in other word can be referred as the resolution of the images on the wafer. The second is the correct placement of the device pattern on the wafer relative to the crystal orientation of the wafer substrate. This is called alignment or registration of patterns in correct position. This registration requirement is similar to the correct alignment of the different floors of a building. It is easy to visualize that misalignment of elevator shafts and stair wells would render the building useless. In a circuit, the effects of misaligned mask layers can cause the entire circuit to fail. In this paper we have reported a couple of results that leads to photoresist development and optimization technique as a standard manufacturing process to form 1μm microbridge for later process of size reduction to form nanogap. Therefore, at the final stage of fabrication, a nano-diagnostic biochip device is developed to use it as a biomolecule detection biosensor. The development of biosensors is still an open field and much remains to be done before many of these bioelectronic devices become commercialized. In this research, the key factors such as resist thickness, post-exposure bake (PEB) time and developer concentration are taken into account to study the optimum measurements and process. The thickness of resist will affect the resolution of image transferred and developing time. Both PEB and developer concentration also has the tendency to affect the device pattern and developing time. As the result, the photoresist thickness is optimized at 1500nm, the developer RD6 concentration diluted at 10:25 (DI water: RD6) and PEB time optimized at 65s.
{"title":"Photoresist microbridge pattern optimization at 1μm using conventional photolithography technique","authors":"B. S. Rao, M. Nurfaiz, U. Hashim","doi":"10.1109/RSM.2013.6706462","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706462","url":null,"abstract":"One of the delicate processes in semiconductor microfabrication is the photolithography. It is the process that sets the design dimensions on various parts of the device. In order to complete this process, two requirements need to be satisfied. First is to create, the exact dimensions and pattern as established in design phase, which in other word can be referred as the resolution of the images on the wafer. The second is the correct placement of the device pattern on the wafer relative to the crystal orientation of the wafer substrate. This is called alignment or registration of patterns in correct position. This registration requirement is similar to the correct alignment of the different floors of a building. It is easy to visualize that misalignment of elevator shafts and stair wells would render the building useless. In a circuit, the effects of misaligned mask layers can cause the entire circuit to fail. In this paper we have reported a couple of results that leads to photoresist development and optimization technique as a standard manufacturing process to form 1μm microbridge for later process of size reduction to form nanogap. Therefore, at the final stage of fabrication, a nano-diagnostic biochip device is developed to use it as a biomolecule detection biosensor. The development of biosensors is still an open field and much remains to be done before many of these bioelectronic devices become commercialized. In this research, the key factors such as resist thickness, post-exposure bake (PEB) time and developer concentration are taken into account to study the optimum measurements and process. The thickness of resist will affect the resolution of image transferred and developing time. Both PEB and developer concentration also has the tendency to affect the device pattern and developing time. As the result, the photoresist thickness is optimized at 1500nm, the developer RD6 concentration diluted at 10:25 (DI water: RD6) and PEB time optimized at 65s.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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