Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706535
M. Amalina, M. Rusop
This research demonstrated the effect of solution concentration of copper (I) iodide (CuI) to the thin films properties and photovoltaic performance. The CuI concentration was varied from 0.01M to 0.09M. The CuI solution was prepared by mixing the CuI powder with 50 ml of acetonitrile as a solvent. A novel method of mist atomization technique has been used for the deposition of CuI materials. For the thin film properties, the surface morphology and electrical properties of CuI thin films which was deposited on the glass substrates were investigated. The result shows the CuI thin film properties strongly depends on its precursor concentration. The nano size CuI particles were observed for all thin films. The electrical properties indicates the increased of conductivity until optimum point of 0.05M. The highest device efficiency obtained in this research is 1.05%. The pore filling issues and electrical conductivity of hole conductor were the main factors contributed to the overall performance of solar cells.
{"title":"The properties of P-type copper (I) iodide (CuI) as a hole conductor for solid-state dye sensitized solar cells","authors":"M. Amalina, M. Rusop","doi":"10.1109/RSM.2013.6706535","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706535","url":null,"abstract":"This research demonstrated the effect of solution concentration of copper (I) iodide (CuI) to the thin films properties and photovoltaic performance. The CuI concentration was varied from 0.01M to 0.09M. The CuI solution was prepared by mixing the CuI powder with 50 ml of acetonitrile as a solvent. A novel method of mist atomization technique has been used for the deposition of CuI materials. For the thin film properties, the surface morphology and electrical properties of CuI thin films which was deposited on the glass substrates were investigated. The result shows the CuI thin film properties strongly depends on its precursor concentration. The nano size CuI particles were observed for all thin films. The electrical properties indicates the increased of conductivity until optimum point of 0.05M. The highest device efficiency obtained in this research is 1.05%. The pore filling issues and electrical conductivity of hole conductor were the main factors contributed to the overall performance of solar cells.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134538494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706552
Aishah Fauthan, M. Hamidon, B. Majlis, Z. Yunuza
This paper presents the processes of fabrication method in the selective area of growth Carbon Nanotubes (CNTs) on the substrate with an Interdigitated (IDE) electrodes pattern using resist AZ1500. The substrate used in this work was Gallium Phosphate with Chromium (0.021μm) and Platinum (0.11μm) as the metal layer. The CNTS was grown in two different temperatures using chemical vapor deposition (CVD) with hydrogen as the process gas and benzene as the hydrocarbon. The most suitable temperature growth for CNTs in this work was found to be 800oC. In this study, CNTs were produced by CVD impregnated with iron nitrate (Fe(NO3)3·9H2O) solution and Resist AZ1500 as the mask for the selective area grown. Maximum temperature for Resist AZ1500 was at 120oC. Therefore Iron Nitrate was used as the protector to protect the resist to be evaporated. The Resist AZ1500 and the Iron Nitrate were coated in different layer on the substrate using standard lithography method.
{"title":"Lithography method for selective area of CNTs growth","authors":"Aishah Fauthan, M. Hamidon, B. Majlis, Z. Yunuza","doi":"10.1109/RSM.2013.6706552","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706552","url":null,"abstract":"This paper presents the processes of fabrication method in the selective area of growth Carbon Nanotubes (CNTs) on the substrate with an Interdigitated (IDE) electrodes pattern using resist AZ1500. The substrate used in this work was Gallium Phosphate with Chromium (0.021μm) and Platinum (0.11μm) as the metal layer. The CNTS was grown in two different temperatures using chemical vapor deposition (CVD) with hydrogen as the process gas and benzene as the hydrocarbon. The most suitable temperature growth for CNTs in this work was found to be 800oC. In this study, CNTs were produced by CVD impregnated with iron nitrate (Fe(NO3)3·9H2O) solution and Resist AZ1500 as the mask for the selective area grown. Maximum temperature for Resist AZ1500 was at 120oC. Therefore Iron Nitrate was used as the protector to protect the resist to be evaporated. The Resist AZ1500 and the Iron Nitrate were coated in different layer on the substrate using standard lithography method.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706492
Sparsh Raut Dessai, Pramath Keny, U. Gaitonde, M. S. Chandra
Variable Gain Amplifier (VGA) is an integral part of Analog Systems, a special class of VGA called the Programmable Variable Gain Amplifier (PVGA) has revolutionized modern electronic systems. In this paper a highly specific Programmable Gain Operational Amplifier (PGOA) is presented. The Op-Amp design is based on a low distortion source coupled differential amplifier model. The gain of the Op-Amp is varied by adjusting an array of internal series and feedback resistors; to facilitate this setting, three 8-bit programmable registers are provided using which a gain of 24 dB can be attained. Additionally, the design also features two 8-bit registers for status read back operation of the Op-Amp. The overall gain of the Op-Amp varies from -12dB to 12dB for a single stage. The design is embedded application interface compatible. The PGOA is an ideal solution to systems which require variable gain in real time applications and in signal processing. The modeling of the PGOA is made using CMOS device technology and the detailed analysis is summarized.
{"title":"Design of CMOS based Programmable Gain Operational Amplifier","authors":"Sparsh Raut Dessai, Pramath Keny, U. Gaitonde, M. S. Chandra","doi":"10.1109/RSM.2013.6706492","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706492","url":null,"abstract":"Variable Gain Amplifier (VGA) is an integral part of Analog Systems, a special class of VGA called the Programmable Variable Gain Amplifier (PVGA) has revolutionized modern electronic systems. In this paper a highly specific Programmable Gain Operational Amplifier (PGOA) is presented. The Op-Amp design is based on a low distortion source coupled differential amplifier model. The gain of the Op-Amp is varied by adjusting an array of internal series and feedback resistors; to facilitate this setting, three 8-bit programmable registers are provided using which a gain of 24 dB can be attained. Additionally, the design also features two 8-bit registers for status read back operation of the Op-Amp. The overall gain of the Op-Amp varies from -12dB to 12dB for a single stage. The design is embedded application interface compatible. The PGOA is an ideal solution to systems which require variable gain in real time applications and in signal processing. The modeling of the PGOA is made using CMOS device technology and the detailed analysis is summarized.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706531
Z. Habibah, M. Wahid, L. N. Ismail, R. A. Bakar, M. Rozana, M. Rusop
Magnesium oxide and bilayer ZnO/MgO dielectrics film were successfully deposited using spin coating technique. The effect of MgO layer thickness towards prepared dielectric films behaviour was determined by controlling the deposition time. The comparison of the MgO and ZnO/MgO dielectrics film properties shows that the bilayer ZnO/MgO with 238nm MgO layer thickness shows better dielectrics properties compared to others. This was due to its small surface roughness which resulted in better electrical properties that have high resistivity and low leakage current. Optimized bilayer ZnO/MgO film was then used as the dielectrics film for fabrication of organic capacitor. Capacitor performance was determined via capacitance-voltage (C-V) analysis at different frequency applied and it revealed that, the capacitance value increased from 2.4pF to 10pF with addition of PVDF-TrFE organic ferroelectric layer on bilayer ZnO/MgO film caused by high polarization produced in the film.
{"title":"Improvement in dielectric properties of bilayer ZnO/MgO films deposited by Sol-Gel technique","authors":"Z. Habibah, M. Wahid, L. N. Ismail, R. A. Bakar, M. Rozana, M. Rusop","doi":"10.1109/RSM.2013.6706531","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706531","url":null,"abstract":"Magnesium oxide and bilayer ZnO/MgO dielectrics film were successfully deposited using spin coating technique. The effect of MgO layer thickness towards prepared dielectric films behaviour was determined by controlling the deposition time. The comparison of the MgO and ZnO/MgO dielectrics film properties shows that the bilayer ZnO/MgO with 238nm MgO layer thickness shows better dielectrics properties compared to others. This was due to its small surface roughness which resulted in better electrical properties that have high resistivity and low leakage current. Optimized bilayer ZnO/MgO film was then used as the dielectrics film for fabrication of organic capacitor. Capacitor performance was determined via capacitance-voltage (C-V) analysis at different frequency applied and it revealed that, the capacitance value increased from 2.4pF to 10pF with addition of PVDF-TrFE organic ferroelectric layer on bilayer ZnO/MgO film caused by high polarization produced in the film.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129275800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706514
N. F. Za'bah, Kelvin S. K. Kwa, A. O'Neill
A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using <;100> Silicon-on Insulator (SOI) as the starting substrate. The use of ODE etchant such as potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) is known to create geometrical structures due to its anisotropic mechanism of etching. In this process flow, using the <;100> SOI substrate, a triangular shape silicon nanowire is successfully fabricated. The triangle silicon nanowire has <;111> planes on each side which theoretically produces an angle of 54.7° with the <;100> horizontal plane. One of the geometrical characterizing methods that were used to confirm the fabrication of the silicon nanowire is by using Atomic Force Microscope (AFM). In this paper, the study on the aspect ratio of the AFM measurements is presented. This experimental study would demonstrate the importance of having a high aspect ratio cantilever when a nanowire with a thickness of less than 200 nm is concerned.
{"title":"The study on the aspect ratio of Atomic Force Microscope (AFM) measurements for triangular silicon nanowire","authors":"N. F. Za'bah, Kelvin S. K. Kwa, A. O'Neill","doi":"10.1109/RSM.2013.6706514","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706514","url":null,"abstract":"A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using <;100> Silicon-on Insulator (SOI) as the starting substrate. The use of ODE etchant such as potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) is known to create geometrical structures due to its anisotropic mechanism of etching. In this process flow, using the <;100> SOI substrate, a triangular shape silicon nanowire is successfully fabricated. The triangle silicon nanowire has <;111> planes on each side which theoretically produces an angle of 54.7° with the <;100> horizontal plane. One of the geometrical characterizing methods that were used to confirm the fabrication of the silicon nanowire is by using Atomic Force Microscope (AFM). In this paper, the study on the aspect ratio of the AFM measurements is presented. This experimental study would demonstrate the importance of having a high aspect ratio cantilever when a nanowire with a thickness of less than 200 nm is concerned.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706506
K. Kamran, Khatami Saeid, Raissi Farshid, Khorramshahi Fatemeh
Novel porous structure on silicon is proposed for selective ultra violet detection with high quantum efficiency. In order to exploit the single electron effect for this goal, Pt-Si schottky barrier was formed. N-type silicon was electro chemically etched and pores with the height of less than 1 micron were fabricated followed by electrochemical deposition of Platinum. Distinctive and highly responsive behavior of the detector to 365-380 nm wave lengths compared to that of visible range is assumed to be in close relationship with its structural characterizations which is justified through the manner of the shift in breakdown voltage in reverse bias, as the respondent parameter, presented in this report.
{"title":"Highly sensitive porous PtSi/Si UV detector with high selectivity","authors":"K. Kamran, Khatami Saeid, Raissi Farshid, Khorramshahi Fatemeh","doi":"10.1109/RSM.2013.6706506","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706506","url":null,"abstract":"Novel porous structure on silicon is proposed for selective ultra violet detection with high quantum efficiency. In order to exploit the single electron effect for this goal, Pt-Si schottky barrier was formed. N-type silicon was electro chemically etched and pores with the height of less than 1 micron were fabricated followed by electrochemical deposition of Platinum. Distinctive and highly responsive behavior of the detector to 365-380 nm wave lengths compared to that of visible range is assumed to be in close relationship with its structural characterizations which is justified through the manner of the shift in breakdown voltage in reverse bias, as the respondent parameter, presented in this report.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706482
K. A. Yusof, Nurul Izzati Mohammad Noh, S. H. Herman, A. Abdullah, M. Hussin, W. Abdullah
This study presents the effect of source-drain metal shield in FET structure on drain leakage current. The FET structure was fabricated on the wafer by using MIMOS's standard fabrication process. Aluminum (Al) was sputtered with thickness of 400 nm as metal shield layer at the source and drain area of FET structure. There are four different layout designs of source-drain metal shield that were tested by Keithley 236 current-voltage sourcing under light and dark conditions. The measurements were carried out in a dark box with controllable light intensity. Besides the drain leakage current investigation, this study also investigates the light effect of various layout designs with source-drain metal shield on FET structure. It was found that the layout design with source-drain metal shield has lower drain leakage current compared to the layout design without source-drain metal shield. However, the various layout design of source-drain metal shield cannot eliminate the light effect.
{"title":"Effect of source-drain metal shield in FET structure on drain leakage current","authors":"K. A. Yusof, Nurul Izzati Mohammad Noh, S. H. Herman, A. Abdullah, M. Hussin, W. Abdullah","doi":"10.1109/RSM.2013.6706482","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706482","url":null,"abstract":"This study presents the effect of source-drain metal shield in FET structure on drain leakage current. The FET structure was fabricated on the wafer by using MIMOS's standard fabrication process. Aluminum (Al) was sputtered with thickness of 400 nm as metal shield layer at the source and drain area of FET structure. There are four different layout designs of source-drain metal shield that were tested by Keithley 236 current-voltage sourcing under light and dark conditions. The measurements were carried out in a dark box with controllable light intensity. Besides the drain leakage current investigation, this study also investigates the light effect of various layout designs with source-drain metal shield on FET structure. It was found that the layout design with source-drain metal shield has lower drain leakage current compared to the layout design without source-drain metal shield. However, the various layout design of source-drain metal shield cannot eliminate the light effect.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706501
A. F. Malik, Z. A. Burhanudin, V. Jeoti, U. Hashim, K. L. Foo, M. Ismail
The design, fabrication and characterization of Surface Acoustic Wave (SAW) delay lines on piezo-crystalline and polymer substrate is outlined in this paper. The SAW delay lines consist of two sets of Inter-Digital Transducers (IDT) separated by a certain distance on the surface of the piezoelectric substrate. Initially, the design parameters of the SAW delay lines are obtained using Impulse Response model. Then, the device is fabricated using conventional lithography process. The transmission coefficients (S21) of the SAW devices fabricated on 500 μm-thick Lithium Niobate (LiNbO3) and on 110 μm-thick polyvinyldeneflouride (PVDF) substrates are then observed using vector network analyzer. It is found that SAW devices designed to operate at 55-196 MHz on LiNbO3 has S21 with losses within 10-20 dB. On the other hand, SAW devices designed to operate on PVDF, do not show any credible signal. The successful transmission of SAW on LiNbO3 shows that appropriate design, fabrication and characterization methodology has been adopted. Unfortunately, due to the thin PVDF layer, the acoustic signal transverse downward beyond the thickness of the PVDF rendering the SAW devices non-operational. From the data collected, it is therefore believed that successful generation of SAW on piezo-crystal and polymer substrate could only be realized if the thickness of the PVDF is at least six times the acoustic wavelength of the SAW itself.
{"title":"Acoustic wavelength effects on the propagation of SAW on piezo-crystal and polymer substrates","authors":"A. F. Malik, Z. A. Burhanudin, V. Jeoti, U. Hashim, K. L. Foo, M. Ismail","doi":"10.1109/RSM.2013.6706501","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706501","url":null,"abstract":"The design, fabrication and characterization of Surface Acoustic Wave (SAW) delay lines on piezo-crystalline and polymer substrate is outlined in this paper. The SAW delay lines consist of two sets of Inter-Digital Transducers (IDT) separated by a certain distance on the surface of the piezoelectric substrate. Initially, the design parameters of the SAW delay lines are obtained using Impulse Response model. Then, the device is fabricated using conventional lithography process. The transmission coefficients (S21) of the SAW devices fabricated on 500 μm-thick Lithium Niobate (LiNbO3) and on 110 μm-thick polyvinyldeneflouride (PVDF) substrates are then observed using vector network analyzer. It is found that SAW devices designed to operate at 55-196 MHz on LiNbO3 has S21 with losses within 10-20 dB. On the other hand, SAW devices designed to operate on PVDF, do not show any credible signal. The successful transmission of SAW on LiNbO3 shows that appropriate design, fabrication and characterization methodology has been adopted. Unfortunately, due to the thin PVDF layer, the acoustic signal transverse downward beyond the thickness of the PVDF rendering the SAW devices non-operational. From the data collected, it is therefore believed that successful generation of SAW on piezo-crystal and polymer substrate could only be realized if the thickness of the PVDF is at least six times the acoustic wavelength of the SAW itself.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124027585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706487
R. A. Bakar, S. H. Herman, H. Hassan, W. Ahmad, F. Mohamad, M. Aminuddin
Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively studied as the potential absorber layer for solar cell thin film application. Using sputtering technique however could result in the formation of several types of defects for example microscopic defects. Microscopic defects are formed within the absorber layer due to the formation of pinholes after surface treatment process. Since the effects of the formation of pinholes in CIS-based thin film solar cell is not well understood yet, a detail study is therefore necessary. In this work, a solar cell model was developed and simulated using Silvaco TCAD tools. Cylindrical pinholes of various diameters and depths were created and analyzed. The simulation results predicted that the number and depth of the pinholes affect the performance of the CIS-based thin film solar cell. The variation of pinhole diameter however did not exhibit any significant effect. It was found that the increases in the number of the pinholes resulted in the increases of solar cell efficiency. The efficiency was predicted to be of around 17.5% when ten pinholes existed within the CIS layer. No significant effect was found as the diameter of the pinhole became wider. Deeper the pinhole depth into the layer however produced the solar cell efficiency of only 1.37%.
{"title":"Modeling and simulation of microscopic defects in CIS-based solar cell thin film using silvaco TCAD","authors":"R. A. Bakar, S. H. Herman, H. Hassan, W. Ahmad, F. Mohamad, M. Aminuddin","doi":"10.1109/RSM.2013.6706487","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706487","url":null,"abstract":"Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively studied as the potential absorber layer for solar cell thin film application. Using sputtering technique however could result in the formation of several types of defects for example microscopic defects. Microscopic defects are formed within the absorber layer due to the formation of pinholes after surface treatment process. Since the effects of the formation of pinholes in CIS-based thin film solar cell is not well understood yet, a detail study is therefore necessary. In this work, a solar cell model was developed and simulated using Silvaco TCAD tools. Cylindrical pinholes of various diameters and depths were created and analyzed. The simulation results predicted that the number and depth of the pinholes affect the performance of the CIS-based thin film solar cell. The variation of pinhole diameter however did not exhibit any significant effect. It was found that the increases in the number of the pinholes resulted in the increases of solar cell efficiency. The efficiency was predicted to be of around 17.5% when ten pinholes existed within the CIS layer. No significant effect was found as the diameter of the pinhole became wider. Deeper the pinhole depth into the layer however produced the solar cell efficiency of only 1.37%.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122111894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706505
A. N. Fadzilah, K. Dayana, L. N. Ismail, M. Rusop
We have successfully deposit the a-C and nitrogen doped a-C (a-C:N) using the custom-made Aerosol-assisted CVD (AACVD). Natural precursor, camphor oil (C10H16O) was selected as the carbon source. The electrical and optical properties were characterized by BUKOH KEIKI CEP2000 solar simulator system and Perkin Elmer LAMBDA 750 UV-vis-NIR spectroscope respectively. Five samples were prepared for the a-C and a-C: N respectively, with the deposition temperatures ranging from 400°C to 600°C. An ohmic contact was acquired between the carbon/metal configurations from the current-voltage solar simulator system. Higher conductivity at a-C: N, ~x10-2 Scm-1 is due to the decrease in defects since the spin density gap decrease with the nitrogen addition. Pure a-C exhibit absorption coefficient, a of 10 cm-1, whereas for a-C:N, a is of 10 cm-1. The high σ value is at a-C:N is due to the presence of more graphitic component (sp2 carbon bonding) in the carbon films.
{"title":"Analysis on electrical and optical properties of nitrogen incorporated amorphous carbon prepared by aerosol-assisted CVD method","authors":"A. N. Fadzilah, K. Dayana, L. N. Ismail, M. Rusop","doi":"10.1109/RSM.2013.6706505","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706505","url":null,"abstract":"We have successfully deposit the a-C and nitrogen doped a-C (a-C:N) using the custom-made Aerosol-assisted CVD (AACVD). Natural precursor, camphor oil (C10H16O) was selected as the carbon source. The electrical and optical properties were characterized by BUKOH KEIKI CEP2000 solar simulator system and Perkin Elmer LAMBDA 750 UV-vis-NIR spectroscope respectively. Five samples were prepared for the a-C and a-C: N respectively, with the deposition temperatures ranging from 400°C to 600°C. An ohmic contact was acquired between the carbon/metal configurations from the current-voltage solar simulator system. Higher conductivity at a-C: N, ~x10-2 Scm-1 is due to the decrease in defects since the spin density gap decrease with the nitrogen addition. Pure a-C exhibit absorption coefficient, a of 10 cm-1, whereas for a-C:N, a is of 10 cm-1. The high σ value is at a-C:N is due to the presence of more graphitic component (sp2 carbon bonding) in the carbon films.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125042595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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