Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706569
M. Radhakrishnan
Summary form only given. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to curb the extension of even atomic level defects, especially when the dimensions are at nanometer level. Many of such defects can be traced using the fault localization tools. However these tools have limitations in revealing the actual defects or defect sites at atomic diensions. Tools employing photon, electron and ion beams as well as nanoprobing have been revisited to reveal the limitations and the need for better techniques [1,2]. The necessity at this stage is the capability to compare the real time results from simulation with the analysis results from the tools. Understanding the physical phenomenon with which devices mal-function becomes more difficult and poses higher difficulty in solving both the device and process problems. One of the most important and interesting area is interfaces and understanding the related issues. Two sets of interfaces - one concerning the basic transistor and the other related to interconnects - have shown unassumable problems in device reliability studies. Physical analysis in correlation with electrical characterization in nano devices using ultrathin gate dielectrics depicts certain limitations at the interfaces and some new phenomenon which affects the performance. As the gate dielectric thickness reduces to atomic levels, the modes of conduction in the region itself changes and the structure gets modified which can affect the device reliability [3]. Use of lowK dielectrics for inter-layers and copper for metallization has introduced new phenomenon and modifications in the understanding of electron conduction through local interconnects from a reliability point of view. The thermal management in such devices is an area of concern. Use of new materials like CNTs for interconnect vias may yield better performance [4], but the interfaces have to be thoroughly studied. Some of the recent studies to understand the conduction mechanisms, microstructural damages, interface interactions as well as the physical effects in the structural integrity in nano silicon devices will be discussed in this talk.
{"title":"Analysis challenges and interface physics in silicon nanodevices","authors":"M. Radhakrishnan","doi":"10.1109/RSM.2013.6706569","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706569","url":null,"abstract":"Summary form only given. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to curb the extension of even atomic level defects, especially when the dimensions are at nanometer level. Many of such defects can be traced using the fault localization tools. However these tools have limitations in revealing the actual defects or defect sites at atomic diensions. Tools employing photon, electron and ion beams as well as nanoprobing have been revisited to reveal the limitations and the need for better techniques [1,2]. The necessity at this stage is the capability to compare the real time results from simulation with the analysis results from the tools. Understanding the physical phenomenon with which devices mal-function becomes more difficult and poses higher difficulty in solving both the device and process problems. One of the most important and interesting area is interfaces and understanding the related issues. Two sets of interfaces - one concerning the basic transistor and the other related to interconnects - have shown unassumable problems in device reliability studies. Physical analysis in correlation with electrical characterization in nano devices using ultrathin gate dielectrics depicts certain limitations at the interfaces and some new phenomenon which affects the performance. As the gate dielectric thickness reduces to atomic levels, the modes of conduction in the region itself changes and the structure gets modified which can affect the device reliability [3]. Use of lowK dielectrics for inter-layers and copper for metallization has introduced new phenomenon and modifications in the understanding of electron conduction through local interconnects from a reliability point of view. The thermal management in such devices is an area of concern. Use of new materials like CNTs for interconnect vias may yield better performance [4], but the interfaces have to be thoroughly studied. Some of the recent studies to understand the conduction mechanisms, microstructural damages, interface interactions as well as the physical effects in the structural integrity in nano silicon devices will be discussed in this talk.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126890203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706538
M. Sarah, F. Zahid, M. Eliás, U. Noor, M. Rusop
This paper discussed the effect of different composition ratio of Iodine doped multiwalled carbon nanotubes (I-MWCNTs) in MEH-PPV for organic solar cell applications. The I-MWCNTs compositions were varied from 0, 30, 50, 60 and 80 wt% and the effect to the electrical, optical and physical properties were investigated. The MWCNTs was doped with acceptor atoms which is Iodine, before it is being mix to the MEH-PPV solution. This nanocomposited MEH-PPV:I-MWNTs solution was deposited on glass and ITO substrates by spin coating technique. The photo-current showed linearly increased as the composition ratio increase, meanwhile the photoconductivity showed the highest value at 60 wt% with 0.16 Ω/m. This value is supported by the value of absorption coefficient which is around 9.7 × 105 m-1. Therefore, 60 wt% was used to fabricate organic solar cells, which gave efficiency around 0.0008%, Voc = 0.094 V, Jsc = 0.031 mA/cm2 and fill factor = 0.269.
{"title":"Iodine doped multiwall carbon nanotubes in MEH-PPV:I-MWCNTs nanocomposite for organic solar cell applications","authors":"M. Sarah, F. Zahid, M. Eliás, U. Noor, M. Rusop","doi":"10.1109/RSM.2013.6706538","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706538","url":null,"abstract":"This paper discussed the effect of different composition ratio of Iodine doped multiwalled carbon nanotubes (I-MWCNTs) in MEH-PPV for organic solar cell applications. The I-MWCNTs compositions were varied from 0, 30, 50, 60 and 80 wt% and the effect to the electrical, optical and physical properties were investigated. The MWCNTs was doped with acceptor atoms which is Iodine, before it is being mix to the MEH-PPV solution. This nanocomposited MEH-PPV:I-MWNTs solution was deposited on glass and ITO substrates by spin coating technique. The photo-current showed linearly increased as the composition ratio increase, meanwhile the photoconductivity showed the highest value at 60 wt% with 0.16 Ω/m. This value is supported by the value of absorption coefficient which is around 9.7 × 105 m-1. Therefore, 60 wt% was used to fabricate organic solar cells, which gave efficiency around 0.0008%, Voc = 0.094 V, Jsc = 0.031 mA/cm2 and fill factor = 0.269.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125825980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706467
M. Nawi, A. A. Manaf, Mohamad Faizal Abd Rahman, M. Arshad, O. Sidek
This paper presents the development of the novel fluidic based one side electrode pressure sensor. The structure of the sensor consists of container and an electrode. For the container, the membrane and microchannel were combined in one structure. Meanwhile, the design of the electrode was extended from the pattern of coplanar electrode based on the previous study. The microfluidic technology by using a small amount of liquid as a sensing element was proposed to measure the external pressure. When the external pressure was applied to the sensor, the membrane was deflected and the liquid displaced inside the microchannel. The sensing electrode measured the changes using electrical double layer concepts and gave the output in capacitance. The sensor was successfully fabricated for electrode using printed circuit board (PCB) process and the container using polymer fabrication process. The polymer such as PDMS was chosen because it was suitable to be implemented as a membrane. The methanol was used as a liquid due to its dielectric constant. The data experiment was recorded and measured using LCR meter for different applied pressure. The capacitance response was demonstrated for pressure 2kPa until 30kPa. The sensitivity of the sensor was 0.06pF/kPa. Also, the standard deviation of output capacitance equaled to 0.04.
{"title":"A novel of fluidic based one side electrode type pressure sensor","authors":"M. Nawi, A. A. Manaf, Mohamad Faizal Abd Rahman, M. Arshad, O. Sidek","doi":"10.1109/RSM.2013.6706467","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706467","url":null,"abstract":"This paper presents the development of the novel fluidic based one side electrode pressure sensor. The structure of the sensor consists of container and an electrode. For the container, the membrane and microchannel were combined in one structure. Meanwhile, the design of the electrode was extended from the pattern of coplanar electrode based on the previous study. The microfluidic technology by using a small amount of liquid as a sensing element was proposed to measure the external pressure. When the external pressure was applied to the sensor, the membrane was deflected and the liquid displaced inside the microchannel. The sensing electrode measured the changes using electrical double layer concepts and gave the output in capacitance. The sensor was successfully fabricated for electrode using printed circuit board (PCB) process and the container using polymer fabrication process. The polymer such as PDMS was chosen because it was suitable to be implemented as a membrane. The methanol was used as a liquid due to its dielectric constant. The data experiment was recorded and measured using LCR meter for different applied pressure. The capacitance response was demonstrated for pressure 2kPa until 30kPa. The sensitivity of the sensor was 0.06pF/kPa. Also, the standard deviation of output capacitance equaled to 0.04.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125187628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706509
Chong Soon Weng, U. Hashim, Wei‐Wen Liu
In this work, the fabrication of silicon nitride ion sensitive field-effect transistor is presented. The ISFET structure is similar to metal oxide semiconductor field-effect transistor (MOSFET) but the gate metal electrode is replaced by a layer of ion sensitive material, also known as the sensing membrane. The fabrication process utilized four masks which consist of the source and drain, gate, contacts and metal mask. The buffered oxide etch was used for etching the silicon oxide and silicon nitride as it is easily available in the cleanroom. In this work, the self-aligned method was used to fabricate the ISFET and this method has shortened the fabrication step as compared to conventional fabrication method. The sample was inspected using high powered microscope after each step of the fabrication and has shown convincing results. The result of this work is an ISFET with silicon nitride as the gate material.
{"title":"Fabrication of silicon nitride ion sensitive field-effect transistor (ISFET)","authors":"Chong Soon Weng, U. Hashim, Wei‐Wen Liu","doi":"10.1109/RSM.2013.6706509","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706509","url":null,"abstract":"In this work, the fabrication of silicon nitride ion sensitive field-effect transistor is presented. The ISFET structure is similar to metal oxide semiconductor field-effect transistor (MOSFET) but the gate metal electrode is replaced by a layer of ion sensitive material, also known as the sensing membrane. The fabrication process utilized four masks which consist of the source and drain, gate, contacts and metal mask. The buffered oxide etch was used for etching the silicon oxide and silicon nitride as it is easily available in the cleanroom. In this work, the self-aligned method was used to fabricate the ISFET and this method has shortened the fabrication step as compared to conventional fabrication method. The sample was inspected using high powered microscope after each step of the fabrication and has shown convincing results. The result of this work is an ISFET with silicon nitride as the gate material.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134062321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706511
M. Nuzaihan, U. Hashim, T. Nazwa, A. R. Ruslinda
We have demonstrated a simple and low-cost method to fabricate poly-silicon microwire by conventional photolithography technique. There are two different steps process flow were involved in the conventional photolithography technique which are employed the positive resist as a mask and aluminium (Al) as hard mask. Low pressure chemical vapour deposition (LPCVD) was used to deposit 50 nm poly-silicon layer on the Si-SiO2-Si3N4 layer. Wire mask must be first designed using AutoCAD before patterning onto chrome mask. Initially the 300 nm thick layer of positive resist is coated on the sample. Subsequently, the coated sample were exposed to UV light for 10 seconds and followed by development process. The critical part in this development process is to control the development time and resist profile. There are three types of resist profile problems such as underdevelopment, incomplete development and overdevelopment resist profile. These resist profiles problems can negatively affect in the subsequent etch process. Next process is an etching process. For positive resist as a mask process flow, the developed sample was loaded into SAMCO Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) 10iP to anisotropic etching of poly-silicon for 7 seconds. Meanwhile, for Al as a hard mask, the developed sample was dipped into Aluminium (Al) etchant for 3 minutes then followed by resist stripping and anisotropic etching of poly-silicon as similar to the resist mask process flow. Finally, the dimensions and etch profiles of <; 1um poly-silicon microwire were morphologically characterized using optical microscopy.
{"title":"Fabrication of poly-silicon microwire using conventional photolithography technique: Positive resist mask vs aluminium hard mask","authors":"M. Nuzaihan, U. Hashim, T. Nazwa, A. R. Ruslinda","doi":"10.1109/RSM.2013.6706511","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706511","url":null,"abstract":"We have demonstrated a simple and low-cost method to fabricate poly-silicon microwire by conventional photolithography technique. There are two different steps process flow were involved in the conventional photolithography technique which are employed the positive resist as a mask and aluminium (Al) as hard mask. Low pressure chemical vapour deposition (LPCVD) was used to deposit 50 nm poly-silicon layer on the Si-SiO2-Si3N4 layer. Wire mask must be first designed using AutoCAD before patterning onto chrome mask. Initially the 300 nm thick layer of positive resist is coated on the sample. Subsequently, the coated sample were exposed to UV light for 10 seconds and followed by development process. The critical part in this development process is to control the development time and resist profile. There are three types of resist profile problems such as underdevelopment, incomplete development and overdevelopment resist profile. These resist profiles problems can negatively affect in the subsequent etch process. Next process is an etching process. For positive resist as a mask process flow, the developed sample was loaded into SAMCO Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) 10iP to anisotropic etching of poly-silicon for 7 seconds. Meanwhile, for Al as a hard mask, the developed sample was dipped into Aluminium (Al) etchant for 3 minutes then followed by resist stripping and anisotropic etching of poly-silicon as similar to the resist mask process flow. Finally, the dimensions and etch profiles of <; 1um poly-silicon microwire were morphologically characterized using optical microscopy.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131120098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706537
A. Shafura, N. D. Md Sin, M. H. Mamat, M. Uzer, A. Mohamad, M. Rusop
Nanostructured Aluminium (Al) doped zinc oxide (ZnO) has been prepared using sol-gel spin-coating method. The annealing temperature was varied and the effect on the surface characteristic of ZnO thin film was studied. The surface topography and morphology of the thin films were characterised using X-ray Diffractometer (XRD), Atomic Force Microscopy (AFM) and Field Emission Scanning Electron Microscopy (FESEM). The paper reveals the effect of annealing temperature and Al doping on the surface characteristic of ZnO thin film. At optimum annealing temperature with doping, the ZnO thin film was observed to have more porous structure with smaller grain size which might enhance the gas sensing performance.
{"title":"Structural properties of Al-doped ZnO thin films deposited by Sol-Gel spin-coating method","authors":"A. Shafura, N. D. Md Sin, M. H. Mamat, M. Uzer, A. Mohamad, M. Rusop","doi":"10.1109/RSM.2013.6706537","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706537","url":null,"abstract":"Nanostructured Aluminium (Al) doped zinc oxide (ZnO) has been prepared using sol-gel spin-coating method. The annealing temperature was varied and the effect on the surface characteristic of ZnO thin film was studied. The surface topography and morphology of the thin films were characterised using X-ray Diffractometer (XRD), Atomic Force Microscopy (AFM) and Field Emission Scanning Electron Microscopy (FESEM). The paper reveals the effect of annealing temperature and Al doping on the surface characteristic of ZnO thin film. At optimum annealing temperature with doping, the ZnO thin film was observed to have more porous structure with smaller grain size which might enhance the gas sensing performance.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115610354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706570
M. Ertuğrul
Due to their outstanding features, superconductors give the opportunity to develop technology available in many areas and to improve the performance of the devices. Superconducting materials are used in many fields particularly in industry, transport, electronics, generation and storage of electricity and transport of electrical current. They are used in industry in the construction of powerful superconducting magnet and superconducting motor and transformer, in transportation, in levitation trains and superconducting motor boats, and in electronics, in the construction of the SQUID, superconducting transistors, particle accelerators, microchips, sensors, detectors, resonators and filters. Rapid developments in the field of electronics make it necessary to increase performances of electronic devices. Because of features such as high speed, low loss, and high resolution, superconductors are preferred in electronics more than the conventional devices. However, studies on superconducting devices have not been completed yet and the physics behind these devices has not been fully understood. Micro-wave resonator improved in terms of quality and performance is used in many areas such as aerospace, communication, television technology, radar, medicine, industry and military. While superconducting devices are made of low-temperature super-conductors such as Nb and NbSn3, high-temperature superconductors are preferred in recent years because of their working capacity at liquid nitrogen temperature and their high critical current and field values. Among high-temperature superconductors, YBCO stands out for microwave applications. Pd nano-dots have been formed on the substrates and, in YBCO, non-superconducting BZO nano-columns have been formed spontaneously on these nano-dots. These nano-columns in YBCO strip act as artificial pinning center. On the studies of use of the Pd to form nano-columns in YBCO, we have shown that artificial pinning centers significantly enhance the performance of the superconducting strip in magnetic field.
{"title":"Artificial pinning centers for superconducting microwave resonators","authors":"M. Ertuğrul","doi":"10.1109/RSM.2013.6706570","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706570","url":null,"abstract":"Due to their outstanding features, superconductors give the opportunity to develop technology available in many areas and to improve the performance of the devices. Superconducting materials are used in many fields particularly in industry, transport, electronics, generation and storage of electricity and transport of electrical current. They are used in industry in the construction of powerful superconducting magnet and superconducting motor and transformer, in transportation, in levitation trains and superconducting motor boats, and in electronics, in the construction of the SQUID, superconducting transistors, particle accelerators, microchips, sensors, detectors, resonators and filters. Rapid developments in the field of electronics make it necessary to increase performances of electronic devices. Because of features such as high speed, low loss, and high resolution, superconductors are preferred in electronics more than the conventional devices. However, studies on superconducting devices have not been completed yet and the physics behind these devices has not been fully understood. Micro-wave resonator improved in terms of quality and performance is used in many areas such as aerospace, communication, television technology, radar, medicine, industry and military. While superconducting devices are made of low-temperature super-conductors such as Nb and NbSn3, high-temperature superconductors are preferred in recent years because of their working capacity at liquid nitrogen temperature and their high critical current and field values. Among high-temperature superconductors, YBCO stands out for microwave applications. Pd nano-dots have been formed on the substrates and, in YBCO, non-superconducting BZO nano-columns have been formed spontaneously on these nano-dots. These nano-columns in YBCO strip act as artificial pinning center. On the studies of use of the Pd to form nano-columns in YBCO, we have shown that artificial pinning centers significantly enhance the performance of the superconducting strip in magnetic field.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"401 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120882332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706485
B. S. Iksannurazmi, A. Nordin, A. Alam
In recent years, wireless communication particularly in the front-end transceiver architecture has increased its functionality. This trend is continuously expanding and of particular is reconfigurable radio frequency (RF) front-end. A multi-band single chip architecture which consists of an array of switches and filters could simplify the complexity of the current superheterodyne architecture. In this paper, the design of a Single Pole Double Throw (SPDT) switch using 0.35μm Complementary Metal Oxide Semiconductor (CMOS) technology is discussed. The SPDT RF CMOS switch was then simulated in the range of frequency of 0-2GHz. At 2 GHz, the switch exhibits insertion loss of 1.153dB, isolation of 21.24dB, P1dB of 21.73dBm and IIP3 of 26.02dBm. Critical RF T/R switch characteristic such as insertion loss, isolation, power 1dB compression point and third order intercept point, IIP3 is discussed and compared with other type of switch designs. Pre and post layout simulation of the SPDT RF CMOS switch are also discussed to analyze the effect of parasitic capacitance between components' interconnection.
{"title":"0.35μm SPDT RF CMOS switch for wireless communication application","authors":"B. S. Iksannurazmi, A. Nordin, A. Alam","doi":"10.1109/RSM.2013.6706485","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706485","url":null,"abstract":"In recent years, wireless communication particularly in the front-end transceiver architecture has increased its functionality. This trend is continuously expanding and of particular is reconfigurable radio frequency (RF) front-end. A multi-band single chip architecture which consists of an array of switches and filters could simplify the complexity of the current superheterodyne architecture. In this paper, the design of a Single Pole Double Throw (SPDT) switch using 0.35μm Complementary Metal Oxide Semiconductor (CMOS) technology is discussed. The SPDT RF CMOS switch was then simulated in the range of frequency of 0-2GHz. At 2 GHz, the switch exhibits insertion loss of 1.153dB, isolation of 21.24dB, P1dB of 21.73dBm and IIP3 of 26.02dBm. Critical RF T/R switch characteristic such as insertion loss, isolation, power 1dB compression point and third order intercept point, IIP3 is discussed and compared with other type of switch designs. Pre and post layout simulation of the SPDT RF CMOS switch are also discussed to analyze the effect of parasitic capacitance between components' interconnection.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124696478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706472
Fatemeh Banitorfian, F. Eshghabadi, A. A. Manaf, P. Pons, N. Noh, M. T. Mustaffa, O. Sidek
This paper proposed a novel tunable MEMS solenoid inductor. This tunable solenoid inductor benefits from a liquid-injected core which varies the permeability of the core corresponding to the level of injection of the liquid; hence, the change in permeability of the core causes the change in the inductance. In this work, HFSS is used for 3D EM simulation. The proposed Solenoid inductor is simulated in Silicon substrate with Copper metal as the coil and injected salted water (CaCl2 solved in water) as the solenoid core. The similar previous works for tunable MEMS inductor employing ferromagnetic cores and liquid-based spiral inductors could not exceed an operating frequency of 2 GHz and a Q factor of 12. Here, a maximum Q factor of 18 and tuning range of 60% were achieved at 18 GHz. Also, the implementation procedure of the proposed variable solenoid inductor is simpler and more cost-effective than the other works.
{"title":"A novel tunable water-based RF MEMS solenoid inductor","authors":"Fatemeh Banitorfian, F. Eshghabadi, A. A. Manaf, P. Pons, N. Noh, M. T. Mustaffa, O. Sidek","doi":"10.1109/RSM.2013.6706472","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706472","url":null,"abstract":"This paper proposed a novel tunable MEMS solenoid inductor. This tunable solenoid inductor benefits from a liquid-injected core which varies the permeability of the core corresponding to the level of injection of the liquid; hence, the change in permeability of the core causes the change in the inductance. In this work, HFSS is used for 3D EM simulation. The proposed Solenoid inductor is simulated in Silicon substrate with Copper metal as the coil and injected salted water (CaCl2 solved in water) as the solenoid core. The similar previous works for tunable MEMS inductor employing ferromagnetic cores and liquid-based spiral inductors could not exceed an operating frequency of 2 GHz and a Q factor of 12. Here, a maximum Q factor of 18 and tuning range of 60% were achieved at 18 GHz. Also, the implementation procedure of the proposed variable solenoid inductor is simpler and more cost-effective than the other works.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127573123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706551
Z. Yunusa, M. Hamidon, S. Rashid
In this paper, Multi-Walled Carbon Nanotubes were grown on a surface of a substrate that consists of a quartz piezoelectric substrate with titanium under layer and platinum electrodes. The Carbon Nanotubes (CNT) was grown using thermal CVD with Iron Nitrate as the catalyst. The growth of the carbon nanotubes was carried out at a temperature of 8000C with hydrogen as the process gas and benzene as the hydrocarbon. Characterization of the as grown CNT was done using Scanning Electron Microscope (SEM) and Raman Spectroscopy. The Raman spectroscopy was carried out on a selected area of 100micron by 100 micron and the peaks of the D-band, G-band and the second order modes were observed from the Raman spectra. Image j image processing software was also used for the extraction of the diameter of the nanotube in which the average diameter was computed to be 46nm.
在本文中，多壁碳纳米管生长在由石英压电衬底、钛衬底和铂电极组成的衬底表面。以硝酸铁为催化剂，采用热气相沉积法制备了碳纳米管(CNT)。在8000C的温度下，以氢为工艺气体，苯为碳氢化合物，进行了碳纳米管的生长。利用扫描电镜(SEM)和拉曼光谱对生长的碳纳米管进行了表征。选取100 μ m × 100 μ m的区域进行拉曼光谱分析，观察到d波段、g波段和二阶模式的拉曼光谱峰。同时利用图像处理软件对纳米管直径进行提取，计算出纳米管的平均直径为46nm。
{"title":"Growth of Multi-Walled Carbon Nanotubes on platinum","authors":"Z. Yunusa, M. Hamidon, S. Rashid","doi":"10.1109/RSM.2013.6706551","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706551","url":null,"abstract":"In this paper, Multi-Walled Carbon Nanotubes were grown on a surface of a substrate that consists of a quartz piezoelectric substrate with titanium under layer and platinum electrodes. The Carbon Nanotubes (CNT) was grown using thermal CVD with Iron Nitrate as the catalyst. The growth of the carbon nanotubes was carried out at a temperature of 8000C with hydrogen as the process gas and benzene as the hydrocarbon. Characterization of the as grown CNT was done using Scanning Electron Microscope (SEM) and Raman Spectroscopy. The Raman spectroscopy was carried out on a selected area of 100micron by 100 micron and the peaks of the D-band, G-band and the second order modes were observed from the Raman spectra. Image j image processing software was also used for the extraction of the diameter of the nanotube in which the average diameter was computed to be 46nm.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126028453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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