Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706528
O. T. Say, Z. Sauli, V. Retnasamy
Light has been used to examine the quality of the products or surface finishing of most products by the industries in recent times. In this research, a lab module tester was designed and built to investigation on the different type of printing paper quality which available commercially was done. Laser light was utilized as a manipulator to distinguish the quality of printing paper and the light reflectance element was used. The photodiode was used as sensing element to detect the reflected light from the surface of printing paper. The both of laser diode and photodiode were placed in a light box. The laser was used to emit light on the sample and the photodiode detects light intensity from the surface printing paper in the light box. Different level of intensity correlates to different voltage output. The investigation on the different type of printing paper including of 70 g/m2, 80 g/m2 and 100 g/m2 were done respectively. The result showed that the 100 g/m2 printing paper has a higher reflected voltage output compared to 80 g/m2 and 70 g/m2 printing paper.
{"title":"High density printing paper quality investigation","authors":"O. T. Say, Z. Sauli, V. Retnasamy","doi":"10.1109/RSM.2013.6706528","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706528","url":null,"abstract":"Light has been used to examine the quality of the products or surface finishing of most products by the industries in recent times. In this research, a lab module tester was designed and built to investigation on the different type of printing paper quality which available commercially was done. Laser light was utilized as a manipulator to distinguish the quality of printing paper and the light reflectance element was used. The photodiode was used as sensing element to detect the reflected light from the surface of printing paper. The both of laser diode and photodiode were placed in a light box. The laser was used to emit light on the sample and the photodiode detects light intensity from the surface printing paper in the light box. Different level of intensity correlates to different voltage output. The investigation on the different type of printing paper including of 70 g/m2, 80 g/m2 and 100 g/m2 were done respectively. The result showed that the 100 g/m2 printing paper has a higher reflected voltage output compared to 80 g/m2 and 70 g/m2 printing paper.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706486
S. Rasidah, N. Samsuri, N. Kushairi, N. A. Ngah
This paper presents a thorough design of 15 GHz Ku-Band medium Power Amplifier (MPA). The technology used for this design is 0.15 μm GaAs p-HEMT technology from WIN semiconductor. The type of active device selected for this design is from the depletion mode p-HEMT. The device consumes 4.5 V of voltage supply and -0.2 V of DC bias. At operating frequency of 15 GHz, the circuit is design to have optimum power with 50 Ω impedance matching for both input and output network, high input and output return loss, high small signal gain, linear output power and high power aided efficiency (PAE).
{"title":"15 GHz medium power amplifier design based On 0.15 μm p-HEMT GaAs technology for wideband applications","authors":"S. Rasidah, N. Samsuri, N. Kushairi, N. A. Ngah","doi":"10.1109/RSM.2013.6706486","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706486","url":null,"abstract":"This paper presents a thorough design of 15 GHz Ku-Band medium Power Amplifier (MPA). The technology used for this design is 0.15 μm GaAs p-HEMT technology from WIN semiconductor. The type of active device selected for this design is from the depletion mode p-HEMT. The device consumes 4.5 V of voltage supply and -0.2 V of DC bias. At operating frequency of 15 GHz, the circuit is design to have optimum power with 50 Ω impedance matching for both input and output network, high input and output return loss, high small signal gain, linear output power and high power aided efficiency (PAE).","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129085923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706502
K. A. Mohamad, A. Alias, I. Saad, B. Gosh, K. Uesugi, H. Fukuda
The influence of [6,6]-phenyl C61-butyric acid methyl ester (PCBM) agglomerated nanostructure on device performance of pentacene-based organic thin-film transistors (OTFTs) were reported. The presence of PCBM layers on a SiO2 gate dielectric resulted in a good electrical characteristics of pentacene-based OTFTs, including a relatively high mobility (μ = 0.95-2.2 cm2 V-1 s-1), low threshold voltages (Vth = -1.1 - -5.4 V), a high on/off current ratio (Ion/Ioff = 104), and a high value of subthreshold slope (SS = 6.5 V/decade). The surface topography studies reveal that the PCBM nanostructure could favor the reduction of grain boundaries, which resulted in a better transistor performance of pentacene-based OTFTs. The influence of PCBM on the molecular microstructure of pentacene thin films elucidates a reasonable explanation for higher performance on OTFTs.
{"title":"Effect of [6,6]-Phenyl-C61 butyric acid methyl ester (PCBM) agglomerated nanostructure on device performance in organic thin-film transistors","authors":"K. A. Mohamad, A. Alias, I. Saad, B. Gosh, K. Uesugi, H. Fukuda","doi":"10.1109/RSM.2013.6706502","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706502","url":null,"abstract":"The influence of [6,6]-phenyl C<sub>61</sub>-butyric acid methyl ester (PCBM) agglomerated nanostructure on device performance of pentacene-based organic thin-film transistors (OTFTs) were reported. The presence of PCBM layers on a SiO<sub>2</sub> gate dielectric resulted in a good electrical characteristics of pentacene-based OTFTs, including a relatively high mobility (μ = 0.95-2.2 cm<sup>2</sup> V<sup>-1</sup> s<sup>-1</sup>), low threshold voltages (V<sub>th</sub> = -1.1 - -5.4 V), a high on/off current ratio (I<sub>on</sub>/I<sub>off</sub> = 10<sup>4</sup>), and a high value of subthreshold slope (SS = 6.5 V/decade). The surface topography studies reveal that the PCBM nanostructure could favor the reduction of grain boundaries, which resulted in a better transistor performance of pentacene-based OTFTs. The influence of PCBM on the molecular microstructure of pentacene thin films elucidates a reasonable explanation for higher performance on OTFTs.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706488
Nurul Arfah Che Mustapha, A. Alam, Sheroz Khan, A. Azman
This work presents an ultra-low voltage DC-DC boost converter vibration-based energy harvesting. A switching gate controlled concept is used which is well suited for low vibration-based frequency and voltage applications. The 0.1-0.5 V input voltage range is linearly increased with the increase of output voltage range, 4-22 V. The transient analysis is simulated to verify the optimum value of the inductive resistance, switching rise and fall times circuit under test. The 10 kΩ load circuit is using 160 μH inductor and 10 μF load capacitor. This voltage converter is suitable for energy harvesting applications in automotive, buried electronic devices for broadband frequency range from 1 kHz to 10 kHz.
{"title":"Parametric analysis for designing low voltage and low frequency energy harvester booster","authors":"Nurul Arfah Che Mustapha, A. Alam, Sheroz Khan, A. Azman","doi":"10.1109/RSM.2013.6706488","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706488","url":null,"abstract":"This work presents an ultra-low voltage DC-DC boost converter vibration-based energy harvesting. A switching gate controlled concept is used which is well suited for low vibration-based frequency and voltage applications. The 0.1-0.5 V input voltage range is linearly increased with the increase of output voltage range, 4-22 V. The transient analysis is simulated to verify the optimum value of the inductive resistance, switching rise and fall times circuit under test. The 10 kΩ load circuit is using 160 μH inductor and 10 μF load capacitor. This voltage converter is suitable for energy harvesting applications in automotive, buried electronic devices for broadband frequency range from 1 kHz to 10 kHz.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"139 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115788659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706534
S. R. Kasjoo, U. Hashim, A. Song
Unipolar nanodiodes, known as the self-switching diodes (SSDs), have recently been demonstrated as terahertz (THz) detectors at room temperature. The SSDs have also shown promising properties as THz emitters and nanomemory devices. Here, we report the fabrication of SSDs on a GaAs/AlGaAs substrate using an atomic-force microscope (AFM) lithography which utilizes AFM-tip ploughing technique and the use of a suitable polymethyl methacrylate layer with thermal-annealing treatment. This approach has successfully overcome some typical problems associated with the tip-ploughing method including the refilling of the SSD's trenches by debris generated during the ploughing process. In this report, all SSDs defined using the AFM lithoghraphy have shown standard diode-like I-V characteristics, indicating the reproducibility of the abovementioned approach. In addition, this method might be useful to realize electronic devices in nanoscale dimensions.
{"title":"Fabrication of nanodiodes using atomic-force microscope lithography","authors":"S. R. Kasjoo, U. Hashim, A. Song","doi":"10.1109/RSM.2013.6706534","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706534","url":null,"abstract":"Unipolar nanodiodes, known as the self-switching diodes (SSDs), have recently been demonstrated as terahertz (THz) detectors at room temperature. The SSDs have also shown promising properties as THz emitters and nanomemory devices. Here, we report the fabrication of SSDs on a GaAs/AlGaAs substrate using an atomic-force microscope (AFM) lithography which utilizes AFM-tip ploughing technique and the use of a suitable polymethyl methacrylate layer with thermal-annealing treatment. This approach has successfully overcome some typical problems associated with the tip-ploughing method including the refilling of the SSD's trenches by debris generated during the ploughing process. In this report, all SSDs defined using the AFM lithoghraphy have shown standard diode-like I-V characteristics, indicating the reproducibility of the abovementioned approach. In addition, this method might be useful to realize electronic devices in nanoscale dimensions.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127244021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706507
Z. Nurbaya, M. Rusop
Lead based titanate (PbTiO3) is one of ferroelectric ceramic family that has been widely investigated of its dielectric property towards high capacitance passive device, i.e. capacitor. It has been known that high annealing temperature is needed to perform perfect crystal level of ferroelectric ceramic that is averagely 650°C done by using crystalline Si substrate with Pt/Ti as intermediate layer. This had been confirmed as the ideal process to have perfectly distribution of uniform grain size with tendency of stable dipole moment. However, high temperature does affect the nucleation site of domain wall where here lays the factor contributes to Pb volatilization and yields to thin films degradation. Further investigation of PbTiO3 thin films preparation at relatively lower temperature was at least 200°C could be the most desirable thin films ever to answer the limitation of source. Therefore, these temperatures make deposition of PbTiO3 possible for glass substrate which has low melting temperature. The current study investigates preparation of PbTiO3 thin films on platinum coated glass substrate through sol-gel spin coating method. The optimum thickness of thin films was achieved by five times of depositions and punctuated with drying process about 200°C for 10mins for each layer. Annealing process was carried out in hot furnace at temperature 300°C to 500°C for 30mins. The prepared thin films were then being measured by impedance analyzer under low frequency about 1000Hz for the dielectric property investigation. It was found that the dielectric constant have linear relationship with annealing temperature. Nevertheless, high dielectric constant resulted to the factor of high dielectric loss that plays a role as in AC signal. In addition, the capacitance value of PbTiO3 thin films is being obtained under low frequency of dielectric constant measurement. Concisely, both dielectric constant and nanometer scaled thin films had influenced much to the capability for high energy storage which will be discussed later in future investigation.
{"title":"Dielectric property of lead titanate thin films prepared on glass substrate at low temperature","authors":"Z. Nurbaya, M. Rusop","doi":"10.1109/RSM.2013.6706507","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706507","url":null,"abstract":"Lead based titanate (PbTiO3) is one of ferroelectric ceramic family that has been widely investigated of its dielectric property towards high capacitance passive device, i.e. capacitor. It has been known that high annealing temperature is needed to perform perfect crystal level of ferroelectric ceramic that is averagely 650°C done by using crystalline Si substrate with Pt/Ti as intermediate layer. This had been confirmed as the ideal process to have perfectly distribution of uniform grain size with tendency of stable dipole moment. However, high temperature does affect the nucleation site of domain wall where here lays the factor contributes to Pb volatilization and yields to thin films degradation. Further investigation of PbTiO3 thin films preparation at relatively lower temperature was at least 200°C could be the most desirable thin films ever to answer the limitation of source. Therefore, these temperatures make deposition of PbTiO3 possible for glass substrate which has low melting temperature. The current study investigates preparation of PbTiO3 thin films on platinum coated glass substrate through sol-gel spin coating method. The optimum thickness of thin films was achieved by five times of depositions and punctuated with drying process about 200°C for 10mins for each layer. Annealing process was carried out in hot furnace at temperature 300°C to 500°C for 30mins. The prepared thin films were then being measured by impedance analyzer under low frequency about 1000Hz for the dielectric property investigation. It was found that the dielectric constant have linear relationship with annealing temperature. Nevertheless, high dielectric constant resulted to the factor of high dielectric loss that plays a role as in AC signal. In addition, the capacitance value of PbTiO3 thin films is being obtained under low frequency of dielectric constant measurement. Concisely, both dielectric constant and nanometer scaled thin films had influenced much to the capability for high energy storage which will be discussed later in future investigation.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"26 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706465
V. Perumal, N. Amil, N. Aiman, U. Hashim
Microwire makes good sensors because their small dimensions which enhance their sensitivity. To be useful, microelectrode sensors must be integrated with electronic capable of processing those signal. In this research, we demonstrated a method to fabricated and characterize metal microwire device for biosensing application. Using conventional photolithography technique and other experimental techniques, we developed a reliable procedure for producing aluminium wires with micron-scale features. Significantly, in micro fabrication the critical dimension (CD) of wafers in photolithography is the most important parameter that determines the final performance of devices. Hence, it is paramount to have high resolution, high sensitivity and precise alignment to successfully transfer the original pattern to wafer. The process was optimized by control the spin speed for photoresist (PR) coating, spin time, post exposure bake time, developer concentration ratio, hard bake and aluminium etch time so as to achieve the possible fabrication process and get the expected microwire size. The process begins with the photoresists coating and spinning at 3000 rpm to form a thin and uniform layer. Subsequently, the PR coated substrates were exposed to UV light for 10s. After the alignment and exposure, the substrate were developed using the resists developer with 25:10 ratio in which 25 parts of developer and 10 parts of deionized water. Eventually, the post exposure bake and hard bake time were optimized for a better throughput on the pattern transfer process. The aluminium microwire has been successfully fabricated with the contact pads. The wires range in thickness from 1 μm-4μm to achieve a resistivity as low as possible for nano range limit of detection. This microelectrodes transducer will be eventually used as biomolecule detection kit. The fabricated microwire was morphologically characterized using Atomic force microscope (AFM), Scanning electron microscope (SEM), High power microscope (HPM). Besides that, the electrical properties of the fabricated aluminium microwire were studied using source meter.
{"title":"Fabrication and characterization of metal microwire transducer for biochip application","authors":"V. Perumal, N. Amil, N. Aiman, U. Hashim","doi":"10.1109/RSM.2013.6706465","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706465","url":null,"abstract":"Microwire makes good sensors because their small dimensions which enhance their sensitivity. To be useful, microelectrode sensors must be integrated with electronic capable of processing those signal. In this research, we demonstrated a method to fabricated and characterize metal microwire device for biosensing application. Using conventional photolithography technique and other experimental techniques, we developed a reliable procedure for producing aluminium wires with micron-scale features. Significantly, in micro fabrication the critical dimension (CD) of wafers in photolithography is the most important parameter that determines the final performance of devices. Hence, it is paramount to have high resolution, high sensitivity and precise alignment to successfully transfer the original pattern to wafer. The process was optimized by control the spin speed for photoresist (PR) coating, spin time, post exposure bake time, developer concentration ratio, hard bake and aluminium etch time so as to achieve the possible fabrication process and get the expected microwire size. The process begins with the photoresists coating and spinning at 3000 rpm to form a thin and uniform layer. Subsequently, the PR coated substrates were exposed to UV light for 10s. After the alignment and exposure, the substrate were developed using the resists developer with 25:10 ratio in which 25 parts of developer and 10 parts of deionized water. Eventually, the post exposure bake and hard bake time were optimized for a better throughput on the pattern transfer process. The aluminium microwire has been successfully fabricated with the contact pads. The wires range in thickness from 1 μm-4μm to achieve a resistivity as low as possible for nano range limit of detection. This microelectrodes transducer will be eventually used as biomolecule detection kit. The fabricated microwire was morphologically characterized using Atomic force microscope (AFM), Scanning electron microscope (SEM), High power microscope (HPM). Besides that, the electrical properties of the fabricated aluminium microwire were studied using source meter.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125312659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706464
R. Pawinanto, J. Yunas, B. Majlis, A. A. Hamzah
In this work, a theoretical analysis on the magnetic force generation of micro-actuator driven by planar microcoil is reported. The actuator design is optimized to increase the magnetic force and flux density that is useful for mechanical membrane deformation of an actuator. Therefore, this work is focused on the design and simulation of actuator material and structure using a finite element analysis method. As the results, the obtained magnetic force of maximum 11.4 mN has been observed for the actuator design having coil geometry of width w = 100 μm, space s =100 μm, turn N = 20 and thickness t =20 μm with NdFeB as magnet material. Hence, the optimized design geometry of the coil can be used as reference for the fabrication of electromagnetic actuator for micropump application.
{"title":"Finite element analysis on magnetic force generation of electromagnetic microactuator for micropump","authors":"R. Pawinanto, J. Yunas, B. Majlis, A. A. Hamzah","doi":"10.1109/RSM.2013.6706464","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706464","url":null,"abstract":"In this work, a theoretical analysis on the magnetic force generation of micro-actuator driven by planar microcoil is reported. The actuator design is optimized to increase the magnetic force and flux density that is useful for mechanical membrane deformation of an actuator. Therefore, this work is focused on the design and simulation of actuator material and structure using a finite element analysis method. As the results, the obtained magnetic force of maximum 11.4 mN has been observed for the actuator design having coil geometry of width w = 100 μm, space s =100 μm, turn N = 20 and thickness t =20 μm with NdFeB as magnet material. Hence, the optimized design geometry of the coil can be used as reference for the fabrication of electromagnetic actuator for micropump application.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125780927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706512
A. Rasmi, A. Marzuki, M. Ismail, N. A. Ngah, A. Rahim
The design and performances of two-stage monolithic microwave integrated circuit (MMIC) medium power amplifier (MPA) for 5.8 GHz applications are presented using a 0.5um commercial GaAs pseudomorphic high electron mobility transistor (PHEMT) technology. The simulated performance shows a two-stage MPA are achieves an associated gain of 16.39dB, P1dB of 20.18dBm, power gain of 15.18 dB and the PAE of 25.30%. While, the measured performance shows a two-stage MPA is achieves an associated gain of 8.33dB. At 5.0V of drain voltage, VDS and 0V of gate voltage, VGS; this MPA consume 111mA of simulated total current and 200.2mA of measured total current. The chip size is 1.7 × 0.85 mm2.
{"title":"Two-stage MMIC medium power amplifier using depletion mode PHEMT for 5.8GHz applications","authors":"A. Rasmi, A. Marzuki, M. Ismail, N. A. Ngah, A. Rahim","doi":"10.1109/RSM.2013.6706512","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706512","url":null,"abstract":"The design and performances of two-stage monolithic microwave integrated circuit (MMIC) medium power amplifier (MPA) for 5.8 GHz applications are presented using a 0.5um commercial GaAs pseudomorphic high electron mobility transistor (PHEMT) technology. The simulated performance shows a two-stage MPA are achieves an associated gain of 16.39dB, P1dB of 20.18dBm, power gain of 15.18 dB and the PAE of 25.30%. While, the measured performance shows a two-stage MPA is achieves an associated gain of 8.33dB. At 5.0V of drain voltage, VDS and 0V of gate voltage, VGS; this MPA consume 111mA of simulated total current and 200.2mA of measured total current. The chip size is 1.7 × 0.85 mm2.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130671775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706565
A. Chin
Summary form only given. The IC chips consume a large amount of energy globally and will continue to increase in the near future. The present IC is a charge-based technology that has logic and memory functions to mimic the human brain. To operate the IC at higher speed, the CMOS inverter of logic IC needs to deliver higher current to charge the capacitors. Thus higher inversion charge (Qinv) is required in CMOS devices. The conventional method to increase Qinv in MOSFET is to scale down the gate oxide thickness (tox) that also improves the short channel effect. Unfortunately, the scaling tox has reached an ultra-thin thickness of ~1.2 nm at 65 nm node CMOS, which causes high gate leakage and DC power (PDC) consumption by direct quantum-mechanical tunneling. Alternatively, higher Qinv can also be obtained by using high dielectric constant (κ) from fundamental physics of Q=CV. We pioneered the high-κ gate dielectric CMOS starting 1998. Nevertheless, the unwanted high transistor threshold voltage (Vt) is the major challenge. Using unique dipole charge of La2O3 and Al2O3 high-κ dielectrics, low Vt n- and p-MOSFETs were achieved at 0.6~0.9 nm equivalent-oxide thickness (EOT). Such La2O3 and Al2O3 high-κ dielectrics have been successfully implemented in 32-nm gate-first CMOS manufacture. To further lower the AC power (PAC) of CV2/2, we invented the small EG defect-free Ge-on-Insulator (GOI or GeOI) MOSFET. The 2.5X higher hole mobility and 1.6X better electron mobility were reached in Ge CMOS at 1~1.4 nm EOT that enable the high-performance Ge logic at lower Vd and PAC. The PAC can be further lowered down by our initiated 3-dimensional (3D) IC based on the Ge CMOS. Low PAC non-volatile memory is also required for IC function. Applying high-κ dielectrics into flash memory, fast 100 μs speed and low write voltage of ~10 V were achieved and listed in the Intl. Technology Roadmap for Semiconductors (ITRS). Such high-κ layers can improve the controllability of charge-storage layer and realize simpler planar structure. At present, the high-κ flash memory has been successfully implemented at 20 nm 128 Gb array manufacture. These high-κ CMOS and flash memory realize the low power green electronic devices.
{"title":"Low power green electronic devices","authors":"A. Chin","doi":"10.1109/RSM.2013.6706565","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706565","url":null,"abstract":"Summary form only given. The IC chips consume a large amount of energy globally and will continue to increase in the near future. The present IC is a charge-based technology that has logic and memory functions to mimic the human brain. To operate the IC at higher speed, the CMOS inverter of logic IC needs to deliver higher current to charge the capacitors. Thus higher inversion charge (Q<sub>inv</sub>) is required in CMOS devices. The conventional method to increase Q<sub>inv</sub> in MOSFET is to scale down the gate oxide thickness (t<sub>ox</sub>) that also improves the short channel effect. Unfortunately, the scaling t<sub>ox</sub> has reached an ultra-thin thickness of ~1.2 nm at 65 nm node CMOS, which causes high gate leakage and DC power (PDC) consumption by direct quantum-mechanical tunneling. Alternatively, higher Q<sub>inv</sub> can also be obtained by using high dielectric constant (κ) from fundamental physics of Q=CV. We pioneered the high-κ gate dielectric CMOS starting 1998. Nevertheless, the unwanted high transistor threshold voltage (V<sub>t</sub>) is the major challenge. Using unique dipole charge of La<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3</sub> high-κ dielectrics, low V<sub>t</sub> n- and p-MOSFETs were achieved at 0.6~0.9 nm equivalent-oxide thickness (EOT). Such La<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3</sub> high-κ dielectrics have been successfully implemented in 32-nm gate-first CMOS manufacture. To further lower the AC power (P<sub>AC</sub>) of CV<sup>2</sup>/2, we invented the small E<sub>G</sub> defect-free Ge-on-Insulator (GOI or GeOI) MOSFET. The 2.5X higher hole mobility and 1.6X better electron mobility were reached in Ge CMOS at 1~1.4 nm EOT that enable the high-performance Ge logic at lower V<sub>d</sub> and P<sub>AC</sub>. The P<sub>AC</sub> can be further lowered down by our initiated 3-dimensional (3D) IC based on the Ge CMOS. Low P<sub>AC</sub> non-volatile memory is also required for IC function. Applying high-κ dielectrics into flash memory, fast 100 μs speed and low write voltage of ~10 V were achieved and listed in the Intl. Technology Roadmap for Semiconductors (ITRS). Such high-κ layers can improve the controllability of charge-storage layer and realize simpler planar structure. At present, the high-κ flash memory has been successfully implemented at 20 nm 128 Gb array manufacture. These high-κ CMOS and flash memory realize the low power green electronic devices.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133084479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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