Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00282
Pan Liu, Liangtao Li, Z. Zeng, Guoqi Zhang, Pengfei Liu, Jon Qingchun Zhang, Jing Zhang
Ultrasonic wire bonding is one of the critical challenges for power semiconductor manufacturing process, especially for silicon carbide (SiC) power devices. Packaging-related strain on the dies is one of the limiting factors for SiC devices scaling towards mass-production. Furthermore, due to the high current demand for SiC power device packaging, thick bond wires are often needed, which brings major challenges for the ultrasonic wire bonding process. Thus, computational simulation methods are under development to assist the wire bonding process. This paper presents a simulation method that can quickly narrow the process window for thick bond wires on SiC power devices beforehand. A process model was created to adapt process parameters of bonding force and power. This model aims to simulate the bond deformation for a discretized bonding area. Wire deformation and equivalent plastic strain were then examined and compared. The model was further validated through experiments. Experimental validation of the wire bonding model reveals a suitable deformation of bond wires, which helps to improve thick wire bonding reliability for power electronics packaging.
{"title":"Ultrasonic Thick Wire Bonding Process Simulation and Validation for Silicon Carbide Power Devices","authors":"Pan Liu, Liangtao Li, Z. Zeng, Guoqi Zhang, Pengfei Liu, Jon Qingchun Zhang, Jing Zhang","doi":"10.1109/ECTC32696.2021.00282","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00282","url":null,"abstract":"Ultrasonic wire bonding is one of the critical challenges for power semiconductor manufacturing process, especially for silicon carbide (SiC) power devices. Packaging-related strain on the dies is one of the limiting factors for SiC devices scaling towards mass-production. Furthermore, due to the high current demand for SiC power device packaging, thick bond wires are often needed, which brings major challenges for the ultrasonic wire bonding process. Thus, computational simulation methods are under development to assist the wire bonding process. This paper presents a simulation method that can quickly narrow the process window for thick bond wires on SiC power devices beforehand. A process model was created to adapt process parameters of bonding force and power. This model aims to simulate the bond deformation for a discretized bonding area. Wire deformation and equivalent plastic strain were then examined and compared. The model was further validated through experiments. Experimental validation of the wire bonding model reveals a suitable deformation of bond wires, which helps to improve thick wire bonding reliability for power electronics packaging.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115016641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00246
Sepehr Soroushiani, Huy Nguyen, Carlos Riera Cercado, Abdulhameed Abdal, Christopher Bolig, S. Y. B. Sayeed, S. Bhardwaj, Wei-Chiang Lin, P. Raj
The objective of this paper is to demonstrate flex-embedded and surface-assembled photonic devices, inductive telemetry, and passive integration to form next-generation miniaturized biophotonic sensors. A hybrid combination of embedding and surface-assembled devices on flex is pursued to reduce the lateral and thickness dimensions of biophotonic systems. Embedding of premanufactured discrete passive devices is demonstrated by inserting in cavities, followed by printed fan-out connections to form the bridge connects between devices and other system components. Initial prototypes showed functional response to color shifts and reliability under bending loads on tissue phantoms. Measurements also confirmed responses to muscle activity as seen through changes in the backscattered light intensity during fist-closure with human subject hands. Initial bending test and reliability after water immersion indicate the stability of the chosen material systems towards flexible and wearable applications. This system concept can eventually be integrated with other system components such as RF transceivers for data telemetry, leading to completely autonomous wireless photosensors for wearable and implantable systems.
{"title":"Wireless Photonic Sensors with Flex Fan-Out Packaged Devices and Enhanced Power Telemetry","authors":"Sepehr Soroushiani, Huy Nguyen, Carlos Riera Cercado, Abdulhameed Abdal, Christopher Bolig, S. Y. B. Sayeed, S. Bhardwaj, Wei-Chiang Lin, P. Raj","doi":"10.1109/ECTC32696.2021.00246","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00246","url":null,"abstract":"The objective of this paper is to demonstrate flex-embedded and surface-assembled photonic devices, inductive telemetry, and passive integration to form next-generation miniaturized biophotonic sensors. A hybrid combination of embedding and surface-assembled devices on flex is pursued to reduce the lateral and thickness dimensions of biophotonic systems. Embedding of premanufactured discrete passive devices is demonstrated by inserting in cavities, followed by printed fan-out connections to form the bridge connects between devices and other system components. Initial prototypes showed functional response to color shifts and reliability under bending loads on tissue phantoms. Measurements also confirmed responses to muscle activity as seen through changes in the backscattered light intensity during fist-closure with human subject hands. Initial bending test and reliability after water immersion indicate the stability of the chosen material systems towards flexible and wearable applications. This system concept can eventually be integrated with other system components such as RF transceivers for data telemetry, leading to completely autonomous wireless photosensors for wearable and implantable systems.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00074
Yonglin Zhang, Haibin Chen, H. Fan, Jinglei Yang, Jingshen Wu
The conventional thermo-compression bonding method in either solder-based or solder-less approaches for the 3D chip integration lead to reliability issues including warpage, delamination and die crack due to high temperature and pressure. To eliminate the issues, an approach of microfluidic electroless interconnection featured with low temperature and pressure has been reported. In this work, the multi-physical field model was firstly developed to understand the deposition mechanism of the microfluidic electroless interconnection method based on a simulation framework considering electrochemistry, fluid flow and mass transfer, and experimental validation was conducted. The results of the numerical work manifest good agreement with the experimental data, and the dominant limitation of the technology is insufficient mass transfer in the microchannel introducing deposition thickness non-uniformity reaching 90%. To eliminate the non-uniformity, the effects of flow velocity and reverse flow are investigated demonstrating remarkable enhancement. The theoretical simulation model shows good feasibility and accuracy providing insight and understanding in the process and mechanism of the technology.
{"title":"Numerical Investigation on Microfluidic Electroless Deposition for Uniform Copper Pillar Microbumps Interconnection","authors":"Yonglin Zhang, Haibin Chen, H. Fan, Jinglei Yang, Jingshen Wu","doi":"10.1109/ECTC32696.2021.00074","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00074","url":null,"abstract":"The conventional thermo-compression bonding method in either solder-based or solder-less approaches for the 3D chip integration lead to reliability issues including warpage, delamination and die crack due to high temperature and pressure. To eliminate the issues, an approach of microfluidic electroless interconnection featured with low temperature and pressure has been reported. In this work, the multi-physical field model was firstly developed to understand the deposition mechanism of the microfluidic electroless interconnection method based on a simulation framework considering electrochemistry, fluid flow and mass transfer, and experimental validation was conducted. The results of the numerical work manifest good agreement with the experimental data, and the dominant limitation of the technology is insufficient mass transfer in the microchannel introducing deposition thickness non-uniformity reaching 90%. To eliminate the non-uniformity, the effects of flow velocity and reverse flow are investigated demonstrating remarkable enhancement. The theoretical simulation model shows good feasibility and accuracy providing insight and understanding in the process and mechanism of the technology.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125299236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00304
Xu Liu, Quan Zhou, Xu Zhao, S. Koh, H. Ye, Guoqi Zhang
Nano-metal sintering has been proven to be a promising die attachment technology for power electronics packaging in the high-end application. Compared with nano silver technology, it is believed that copper-based sintering technology has better cost and performance superiority, and thus has more potential to be utilized in the industry in the future. However, most of the current developed nano copper sintering material and technology shows bad performance with high sintering energy input. In this study, a novel nano-copper based paste has been developed with excellent process ability (sinterable below 280°C for 10 min with low pressure assisted) and good material property (over 40 MPa shear strength), which turns out to be suitable for the state-of-the-art packaging process. Then the material was applied into a SiC power module packaging scenario which shows comparable performance as silver sintering. The whole process only consumed less than 0.5h for each batch, which indicates that the copper sintering technology has great potential for the packaging application in high power situation.
{"title":"Study and Application of Nano Copper Sintering Technology in Power Electronics Packaging","authors":"Xu Liu, Quan Zhou, Xu Zhao, S. Koh, H. Ye, Guoqi Zhang","doi":"10.1109/ECTC32696.2021.00304","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00304","url":null,"abstract":"Nano-metal sintering has been proven to be a promising die attachment technology for power electronics packaging in the high-end application. Compared with nano silver technology, it is believed that copper-based sintering technology has better cost and performance superiority, and thus has more potential to be utilized in the industry in the future. However, most of the current developed nano copper sintering material and technology shows bad performance with high sintering energy input. In this study, a novel nano-copper based paste has been developed with excellent process ability (sinterable below 280°C for 10 min with low pressure assisted) and good material property (over 40 MPa shear strength), which turns out to be suitable for the state-of-the-art packaging process. Then the material was applied into a SiC power module packaging scenario which shows comparable performance as silver sintering. The whole process only consumed less than 0.5h for each batch, which indicates that the copper sintering technology has great potential for the packaging application in high power situation.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126160598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00221
Shuye Zhang, Jianhao Xu, Shang Zhang, P. He, Mingjia Sun, Jianqun Yang, Xingji Li, K. Paik
In this paper, reliability analysis of 3D CSP MEMS and IC under thermal cycle-impact coupled multi-physics loads was investigated. COMSOL Multiphysics, a finite element software, was used to analyze the mechanical behavior of our device under a −55°C/125°C thermal cycling and 1500G@1ms with half-sine pulse impact coupled load. MEMS chip was bonded on a silicon interposer by solder balls. An application specific integrated circuit (ASIC) for the signal processing was placed on the interposer beneath the MEMS. Combining the effects of thermal stress and impact loads, we hope to find out the failure modes of interconnect structures including solder joints and whole device. The deformation and stress distribution of the overall device will be carried out for layout optimization of interconnect structures.
{"title":"Reliability analysis of 3D CSP MEMS and IC under thermal cycle-impact coupled multi-physics loads","authors":"Shuye Zhang, Jianhao Xu, Shang Zhang, P. He, Mingjia Sun, Jianqun Yang, Xingji Li, K. Paik","doi":"10.1109/ECTC32696.2021.00221","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00221","url":null,"abstract":"In this paper, reliability analysis of 3D CSP MEMS and IC under thermal cycle-impact coupled multi-physics loads was investigated. COMSOL Multiphysics, a finite element software, was used to analyze the mechanical behavior of our device under a −55°C/125°C thermal cycling and 1500G@1ms with half-sine pulse impact coupled load. MEMS chip was bonded on a silicon interposer by solder balls. An application specific integrated circuit (ASIC) for the signal processing was placed on the interposer beneath the MEMS. Combining the effects of thermal stress and impact loads, we hope to find out the failure modes of interconnect structures including solder joints and whole device. The deformation and stress distribution of the overall device will be carried out for layout optimization of interconnect structures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129314249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00034
K. Sikka, R. Bonam, Yang Liu, P. Andry, Dishit P. Parekh, Aakrati Jain, M. Bergendahl, R. Divakaruni, Maryse Cournoyer, P. Gagnon, Catherine Dufort, I. de Sousa, Hongqing Zhang, Ed Cropp, T. Wassick, H. Mori, S. Kohara
We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.
{"title":"Direct Bonded Heterogeneous Integration (DBHi) Si Bridge","authors":"K. Sikka, R. Bonam, Yang Liu, P. Andry, Dishit P. Parekh, Aakrati Jain, M. Bergendahl, R. Divakaruni, Maryse Cournoyer, P. Gagnon, Catherine Dufort, I. de Sousa, Hongqing Zhang, Ed Cropp, T. Wassick, H. Mori, S. Kohara","doi":"10.1109/ECTC32696.2021.00034","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00034","url":null,"abstract":"We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121793033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00348
C. T. Chong, Lim Teck Guan, D. Ho, Han Yong, C. Choong, Sharon Lim Pei Siang, S. Bhattacharya
High density heterogeneous integration of ASIC and HBM2 through the use of embedded fine pitch interconnect (EFI) in face-to-face configuration using RDL 1st fan-out wafer packaging platform is demonstrated. The EFI configuration, thermal design consideration and heat dissipation for high power application, mechanical structural modeling for warpage control, wafer fabrication and assembly process integration and reliability testing results will be discussed.
{"title":"Heterogeneous Integration with Embedded Fine Interconnect","authors":"C. T. Chong, Lim Teck Guan, D. Ho, Han Yong, C. Choong, Sharon Lim Pei Siang, S. Bhattacharya","doi":"10.1109/ECTC32696.2021.00348","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00348","url":null,"abstract":"High density heterogeneous integration of ASIC and HBM2 through the use of embedded fine pitch interconnect (EFI) in face-to-face configuration using RDL 1st fan-out wafer packaging platform is demonstrated. The EFI configuration, thermal design consideration and heat dissipation for high power application, mechanical structural modeling for warpage control, wafer fabrication and assembly process integration and reliability testing results will be discussed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"23 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00112
Anna Prakash, K. Byrd, R. Sidhu, S. Elhalawaty, Nevil M. Wu, Hiroshi Okumura, Srinivas Erukula, Jason Lim
There has been a great interest in the use of low temperature soldering (LTS) for surface mount technology (SMT) in the past five years. Low temperature solder (LTS) technology improves the package warpage by reducing thermo-mechanical stress during SMT reflow. Several other benefits with LTS include environmental benefits, decreased carbon emissions, and lower electricity consumption. In this study, LTS technology has been evaluated on several electronic components such as, Integrated circuit (IC), memory, ASIC, and passives. Using several LTS formulations, Solder Joint Reliability (SJR) properties were characterized EOL as well as after reliability testing at components suppliers. Several different package types (i.e. QFN, LGA, CSP, WLCSP etc.), and surface finishes were used in this study. For some of the IC components, different types of packages were evaluated: land grid array (LGA) and quad flat no leads (QFN). Different paste formulations having (35–58 wt.% Bi content) were used in these evaluations and SAC305 was the POR/control leg used. Temperature cycle and other reliability data showed promising results with comparable data for both LTS and SAC legs. The goal in this paper is to document some of the challenges in components supply chain enabling and key learnings on the factors that modulate LTS solder joint reliability for various components during SMT process.
{"title":"Challenges and key learnings in enabling Low Temperature Solder (LTS) technology at packaging components supply base","authors":"Anna Prakash, K. Byrd, R. Sidhu, S. Elhalawaty, Nevil M. Wu, Hiroshi Okumura, Srinivas Erukula, Jason Lim","doi":"10.1109/ECTC32696.2021.00112","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00112","url":null,"abstract":"There has been a great interest in the use of low temperature soldering (LTS) for surface mount technology (SMT) in the past five years. Low temperature solder (LTS) technology improves the package warpage by reducing thermo-mechanical stress during SMT reflow. Several other benefits with LTS include environmental benefits, decreased carbon emissions, and lower electricity consumption. In this study, LTS technology has been evaluated on several electronic components such as, Integrated circuit (IC), memory, ASIC, and passives. Using several LTS formulations, Solder Joint Reliability (SJR) properties were characterized EOL as well as after reliability testing at components suppliers. Several different package types (i.e. QFN, LGA, CSP, WLCSP etc.), and surface finishes were used in this study. For some of the IC components, different types of packages were evaluated: land grid array (LGA) and quad flat no leads (QFN). Different paste formulations having (35–58 wt.% Bi content) were used in these evaluations and SAC305 was the POR/control leg used. Temperature cycle and other reliability data showed promising results with comparable data for both LTS and SAC legs. The goal in this paper is to document some of the challenges in components supply chain enabling and key learnings on the factors that modulate LTS solder joint reliability for various components during SMT process.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126487633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00150
Daniel Riegel, P. Gromala, B. Han, S. Rzepka
Miniaturization of components and higher operating loads lead to reduced lifetimes. Prognostics and Health Management (PHM) enables predictive maintenance of components whose lifetime is shorter than that of the system they are part of. The key to PHM lies in sensor data that correlates with component degradation. In this study, run-to-failure data sets have been generated using in-situ measurements of on-chip stress sensors. Physical failure analysis has provided the link between the data and remaining useful life.
{"title":"Data-Driven Remaining Useful Life Prediction of QFN Packages on Board Level with On-Chip Stress Sensors","authors":"Daniel Riegel, P. Gromala, B. Han, S. Rzepka","doi":"10.1109/ECTC32696.2021.00150","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00150","url":null,"abstract":"Miniaturization of components and higher operating loads lead to reduced lifetimes. Prognostics and Health Management (PHM) enables predictive maintenance of components whose lifetime is shorter than that of the system they are part of. The key to PHM lies in sensor data that correlates with component degradation. In this study, run-to-failure data sets have been generated using in-situ measurements of on-chip stress sensors. Physical failure analysis has provided the link between the data and remaining useful life.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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