Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00315
S. Nam, Younglyong Kim, Aeni Jang, I. Hwang, Sung-Pae Park, Su-chang Lee, Dae-woo Kim
Advanced package technology has been developed rapidly to meet a demand of the high end application such as AI and datacenter. 2.5D silicon interposer technology has been focused as the solution, for high end applications because of its heterogeneous device integration compatibility: high bandwidth memories (HBMs), logic devices or functional chiplets. In this study, a 2.5D structure package called Molded Interposer on Substrate (MIoS) with an extremely large silicon interposer (>2800mm2) on the $85times 85text{mm}^{2}$ body size assembled with 2-ASICs and 8-HBMs was demonstrated successfully for higher chip integration capability. Also, the key challenges of extremely large size 2.5D MIoS package such as warpage of the molded interposer (MIP) module and high level of reliability subjected to thermo-mechanical stress were investigated. MIP warpage was simulated by finite element method (FEM) and controlled the warpage difference between MIP and substrate below 50um at solder melting temperature. As a result, the number of 60K bumps obtained the good joint quality during reflow bonding process. The package reliability was evaluated under thermal cycle test (−55∼125°C) for optimizing the stress induced by the mismatch of thermal expansion (CTE) of components: substrate, underfill, ring frame materials and epoxy mold compound (EMC). The primary failure modes were underfill crack and EMC crack at the corner of devices at the early stage but, through a study on components material properties, package level reliability was improved.
{"title":"The Extremely Large 2.5D Molded Interposer on Substrate (MIoS) Package Integration - Warpage and Reliability","authors":"S. Nam, Younglyong Kim, Aeni Jang, I. Hwang, Sung-Pae Park, Su-chang Lee, Dae-woo Kim","doi":"10.1109/ECTC32696.2021.00315","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00315","url":null,"abstract":"Advanced package technology has been developed rapidly to meet a demand of the high end application such as AI and datacenter. 2.5D silicon interposer technology has been focused as the solution, for high end applications because of its heterogeneous device integration compatibility: high bandwidth memories (HBMs), logic devices or functional chiplets. In this study, a 2.5D structure package called Molded Interposer on Substrate (MIoS) with an extremely large silicon interposer (>2800mm2) on the $85times 85text{mm}^{2}$ body size assembled with 2-ASICs and 8-HBMs was demonstrated successfully for higher chip integration capability. Also, the key challenges of extremely large size 2.5D MIoS package such as warpage of the molded interposer (MIP) module and high level of reliability subjected to thermo-mechanical stress were investigated. MIP warpage was simulated by finite element method (FEM) and controlled the warpage difference between MIP and substrate below 50um at solder melting temperature. As a result, the number of 60K bumps obtained the good joint quality during reflow bonding process. The package reliability was evaluated under thermal cycle test (−55∼125°C) for optimizing the stress induced by the mismatch of thermal expansion (CTE) of components: substrate, underfill, ring frame materials and epoxy mold compound (EMC). The primary failure modes were underfill crack and EMC crack at the corner of devices at the early stage but, through a study on components material properties, package level reliability was improved.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131927905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00222
Keiji Matsumoto, M. Bergendahl, K. Sikka, S. Kohara, H. Mori, T. Hisada
The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology [1] consists of chips directly connected by a bridge chip though Cu pillars, enabling high speed and high band-width communication between CPUs, GPUs and memory chips. The bridge chip resides in a cavity machined in the laminate chip carrier. The remaining structure of the DBHi package is similar to a standard flip-chip package. In this study, we focus on the thermal characterization of the DBHi package using measurements and simulations. We determine how much heat generation is allowed for a bridge chip using a conventional cooling solution from the chip top side. The thermal measurements are conducted using a DBHi package with thermal test chips containing heaters and temperature sensors. The chips are heated by supplying power to the heaters and the temperatures on the chips are measured using resistance temperature devices. We then build a simulation model which is calibrated with the thermal measurement results by adjusting the heat transfer coefficient applied to the package lid top. The model comprises two chips, a bridge chip, interconnects between the chips and the bridge, interconnects between the two large chips and a laminate, a Thermal Interface Material (TIM) and a heat-spreader (a lid). Based on this simulation model, it is examined how much heat generation is allowed for a bridge chip when its maximum temperature is to remain below 75 °C (with an ambient = 40 °C). For example, it is simulated that when each chip generates 100 W (total 200 W for two chips), 26.5 W of heat generation is allowed for a bridge chip. We also consider potential cooling solutions from the laminate side.
{"title":"Thermal Analysis of DBHi (Direct Bonded Heterogeneous Integration) Si Bridge","authors":"Keiji Matsumoto, M. Bergendahl, K. Sikka, S. Kohara, H. Mori, T. Hisada","doi":"10.1109/ECTC32696.2021.00222","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00222","url":null,"abstract":"The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology [1] consists of chips directly connected by a bridge chip though Cu pillars, enabling high speed and high band-width communication between CPUs, GPUs and memory chips. The bridge chip resides in a cavity machined in the laminate chip carrier. The remaining structure of the DBHi package is similar to a standard flip-chip package. In this study, we focus on the thermal characterization of the DBHi package using measurements and simulations. We determine how much heat generation is allowed for a bridge chip using a conventional cooling solution from the chip top side. The thermal measurements are conducted using a DBHi package with thermal test chips containing heaters and temperature sensors. The chips are heated by supplying power to the heaters and the temperatures on the chips are measured using resistance temperature devices. We then build a simulation model which is calibrated with the thermal measurement results by adjusting the heat transfer coefficient applied to the package lid top. The model comprises two chips, a bridge chip, interconnects between the chips and the bridge, interconnects between the two large chips and a laminate, a Thermal Interface Material (TIM) and a heat-spreader (a lid). Based on this simulation model, it is examined how much heat generation is allowed for a bridge chip when its maximum temperature is to remain below 75 °C (with an ambient = 40 °C). For example, it is simulated that when each chip generates 100 W (total 200 W for two chips), 26.5 W of heat generation is allowed for a bridge chip. We also consider potential cooling solutions from the laminate side.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00164
O. Ahmed, Leif Hutchinson, P. Su, Tengfei Jiang
The ever-increasing performance demand on advanced semiconductor devices such as networking processors has been driving the continued growth of body size, complexity, and power consumption of these devices. For thermal management, new thermal interface materials may be needed and some of these materials require higher pressure to achieve the desired thermal performance. On the printed circuit board side, both layer count and thickness are increasing for new systems and a new generation of materials is also needed. All of these factors pose new challenges to solder joint reliability and the fatigue life models require fresh assessment and validation. In this work, we use finite element simulation to investigate and correlate the reliability performance of solder joints in near-product designs in multiple configurations. In the first configuration, the effects of heatsink loading are evaluated. Strain and stress distribution in the solder joints arrays will be analyzed. The results will be used to interpret real-life testing results from both configurations, one with heatsink and one without. Secondly, PCB materials from the same electrical performance group are evaluated. The same component is mounted on three PCB materials with identical layout and all assemblies are tested with the same temperature cycling test. Lifetime differences will be discussed and compared with simulation results. Lastly, effects of PCB thickness will be evaluated in a similar fashion where two thicknesses are tested and compared, again using the same component test vehicle and acceleration testing condition. Results from these studies will provide realistic assessment of solder joint reliability in some of the most challenging application conditions and will be important for improving field lifetime models. For component and system qualification, these data will also help identify important areas of focus to ensure qualification tests are properly executed.
{"title":"Effects of Heatsink Application and PCB Design Variations on BGA Solder Joint Reliability","authors":"O. Ahmed, Leif Hutchinson, P. Su, Tengfei Jiang","doi":"10.1109/ECTC32696.2021.00164","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00164","url":null,"abstract":"The ever-increasing performance demand on advanced semiconductor devices such as networking processors has been driving the continued growth of body size, complexity, and power consumption of these devices. For thermal management, new thermal interface materials may be needed and some of these materials require higher pressure to achieve the desired thermal performance. On the printed circuit board side, both layer count and thickness are increasing for new systems and a new generation of materials is also needed. All of these factors pose new challenges to solder joint reliability and the fatigue life models require fresh assessment and validation. In this work, we use finite element simulation to investigate and correlate the reliability performance of solder joints in near-product designs in multiple configurations. In the first configuration, the effects of heatsink loading are evaluated. Strain and stress distribution in the solder joints arrays will be analyzed. The results will be used to interpret real-life testing results from both configurations, one with heatsink and one without. Secondly, PCB materials from the same electrical performance group are evaluated. The same component is mounted on three PCB materials with identical layout and all assemblies are tested with the same temperature cycling test. Lifetime differences will be discussed and compared with simulation results. Lastly, effects of PCB thickness will be evaluated in a similar fashion where two thicknesses are tested and compared, again using the same component test vehicle and acceleration testing condition. Results from these studies will provide realistic assessment of solder joint reliability in some of the most challenging application conditions and will be important for improving field lifetime models. For component and system qualification, these data will also help identify important areas of focus to ensure qualification tests are properly executed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132068308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00305
Chiao-Chi Lin, Hung-Shuo Chang
Module-level weathering tests are essential to widen the applications of silver nanowires (AgNWs). In this work, electrical stress is applied to AgNWs in pseudo-module and weathering tests are conducted. The degradation of AgNW network under electrical stress depends on the environmental conditions such as UVA exposure, temperature, and humidity. Nanowire density is a crucial parameter of AgNW network to prolong lifespan of the AgNW transparent conductor (TC). The failure mechanism of AgNW network under weathering test with DC electrical stress includes localized Joule heating, electromigration and photo-induced chemical corrosion. Synergistic effect of DC electrical stress and UVA exposure at elevated temperature results in a narrow break line in the AgNW network perpendicular to the current flow. The conductivity breakdown is caused due to the propagation of the break line as weathering goes on. Under electrical stress, there is no electrical conductivity breakdown in the conditions of UVA exposure at low temperature (40°C in this study) and humid air, because the dominant mechanism of degradation is surface sulfidation of AgNWs. In addition, in a 66.4-day test, there is no degradation with the stressor of electrical stress alone in 40°C dark conditions. Outdoor field test results demonstrate the significance of daily thermal cycle and seasonal humidity. With electrical stress, the failure mechanism of outdoor test is the same as indoor accelerated weathering. Moreover, high humidity coupled with UV and high temperature in the outdoors significantly impair the capping agent of AgNWs, resulting in re-configured morphologies of silver. Systematical and long-term investigation of the outdoor field test of AgNW TCs will be conducted to gain more understanding to the electrical failure mechanism of AgNW network in the outdoor applications.
{"title":"Degradation of Silver Nanowire Transparent Conductors by Module-level Weathering under Electrical Stress","authors":"Chiao-Chi Lin, Hung-Shuo Chang","doi":"10.1109/ECTC32696.2021.00305","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00305","url":null,"abstract":"Module-level weathering tests are essential to widen the applications of silver nanowires (AgNWs). In this work, electrical stress is applied to AgNWs in pseudo-module and weathering tests are conducted. The degradation of AgNW network under electrical stress depends on the environmental conditions such as UVA exposure, temperature, and humidity. Nanowire density is a crucial parameter of AgNW network to prolong lifespan of the AgNW transparent conductor (TC). The failure mechanism of AgNW network under weathering test with DC electrical stress includes localized Joule heating, electromigration and photo-induced chemical corrosion. Synergistic effect of DC electrical stress and UVA exposure at elevated temperature results in a narrow break line in the AgNW network perpendicular to the current flow. The conductivity breakdown is caused due to the propagation of the break line as weathering goes on. Under electrical stress, there is no electrical conductivity breakdown in the conditions of UVA exposure at low temperature (40°C in this study) and humid air, because the dominant mechanism of degradation is surface sulfidation of AgNWs. In addition, in a 66.4-day test, there is no degradation with the stressor of electrical stress alone in 40°C dark conditions. Outdoor field test results demonstrate the significance of daily thermal cycle and seasonal humidity. With electrical stress, the failure mechanism of outdoor test is the same as indoor accelerated weathering. Moreover, high humidity coupled with UV and high temperature in the outdoors significantly impair the capping agent of AgNWs, resulting in re-configured morphologies of silver. Systematical and long-term investigation of the outdoor field test of AgNW TCs will be conducted to gain more understanding to the electrical failure mechanism of AgNW network in the outdoor applications.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131886220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00096
Takenori Kakutani, Yuya Suzuki, M. Koh, Shoya Sekiguchi, Satoko Matsumura, K. Oki, Shoko Mishima, N. Ishikawa, T. Ogata, Serhat Erdogan, Muhammad Ali, M. Kathaperumal, M. Swaminathan
This paper describes the development of a novel dry film-type dielectric material with low loss tangent (Df) and the demonstration of a low-loss filter substrate using the dielectric material for high-frequency transmission applications. This paper also presents the evaluation results of the small filter characteristics of the substrate in the 28 GHz and 39 GHz 5G millimeter-wave (mmWave) band. We have recently developed a dry film dielectric material with outstanding electrical properties and excellent mechanical properties (Material P). This new material is based on polyphenylene ether (PPE) that has extremely low Df. PPE is commonly known as a thermoplastic polymer, henceforth a new chemical design was applied to modify the polymer structure into a thermosetting polymer. The new dielectric material can be processed at a low temperature about 200°C and is compatible to the standard substrate manufacturing processes, such as semi additive process (SAP). Material characterization revealed that Dk/Df of Material P is 3.1 /0.0013 at 10 GHz, and glass transition temperature (Tg) is 200°C. In this work, RF filter performance of the Material P was characterized to demonstrate the benefit of the low loss material. As the reference, the performance of epoxy dielectric was additionally characterized and compared. Electrical characterization of the filter structures showed low transmission losses < 1.0 dB at 28 GHz and < 0.8 dB at 39 GHz with Material P, verifying applicability of the material for high frequency applications.
{"title":"Material Design and High Frequency Characterization of Novel Ultra-Low Loss Dielectric Material for 5G and 6G Applications","authors":"Takenori Kakutani, Yuya Suzuki, M. Koh, Shoya Sekiguchi, Satoko Matsumura, K. Oki, Shoko Mishima, N. Ishikawa, T. Ogata, Serhat Erdogan, Muhammad Ali, M. Kathaperumal, M. Swaminathan","doi":"10.1109/ECTC32696.2021.00096","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00096","url":null,"abstract":"This paper describes the development of a novel dry film-type dielectric material with low loss tangent (Df) and the demonstration of a low-loss filter substrate using the dielectric material for high-frequency transmission applications. This paper also presents the evaluation results of the small filter characteristics of the substrate in the 28 GHz and 39 GHz 5G millimeter-wave (mmWave) band. We have recently developed a dry film dielectric material with outstanding electrical properties and excellent mechanical properties (Material P). This new material is based on polyphenylene ether (PPE) that has extremely low Df. PPE is commonly known as a thermoplastic polymer, henceforth a new chemical design was applied to modify the polymer structure into a thermosetting polymer. The new dielectric material can be processed at a low temperature about 200°C and is compatible to the standard substrate manufacturing processes, such as semi additive process (SAP). Material characterization revealed that Dk/Df of Material P is 3.1 /0.0013 at 10 GHz, and glass transition temperature (Tg) is 200°C. In this work, RF filter performance of the Material P was characterized to demonstrate the benefit of the low loss material. As the reference, the performance of epoxy dielectric was additionally characterized and compared. Electrical characterization of the filter structures showed low transmission losses < 1.0 dB at 28 GHz and < 0.8 dB at 39 GHz with Material P, verifying applicability of the material for high frequency applications.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00174
Jacinta Aman Lim, Yun-Mook Park, Edil De Vera, Byung-Cheol Kim, B. Dunlap
The need for migrating to carrier sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. As the demand for PMICs, RF and other single die applications increases for Fan-Out Wafer Level Packaging (FOWLP) processing on mainstream carrier sizes, large Panel Level Processing to meet these demands become a natural progression to an already burgeoning market. However, not all products would benefit from migrating from 300mm/330mm carrier to large panel. If the total area of the panel is not fully utilized, it results in material waste and loss. While FOWLP has been established as one of the most versatile packaging technologies in the recent past and already accounts for over $1.2 billion USD due to its unique advantages, traditional 300mm round carrier used for processing FOWLP is still cost inhibitive. This paper will present the background of utilizing $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel size and show an example of leveraging from existing equipment for backend processing for cost considerations. We will also review the processing method for 6-sided die protection of a single die and how it translates to $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel processing. Comparisons between usable area of 300mm round carrier versus $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel, sweet spot recommendation for pricing per unit based on body size and Component Level Reliability (CLR) will be presented.
{"title":"600mm Fan-Out Panel Level Packaging (FOPLP) As A Scale Up Alternative to 300mm Fan-Out Wafer Level Packaging (FOWLP) with 6-Sided Die Protection","authors":"Jacinta Aman Lim, Yun-Mook Park, Edil De Vera, Byung-Cheol Kim, B. Dunlap","doi":"10.1109/ECTC32696.2021.00174","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00174","url":null,"abstract":"The need for migrating to carrier sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. As the demand for PMICs, RF and other single die applications increases for Fan-Out Wafer Level Packaging (FOWLP) processing on mainstream carrier sizes, large Panel Level Processing to meet these demands become a natural progression to an already burgeoning market. However, not all products would benefit from migrating from 300mm/330mm carrier to large panel. If the total area of the panel is not fully utilized, it results in material waste and loss. While FOWLP has been established as one of the most versatile packaging technologies in the recent past and already accounts for over $1.2 billion USD due to its unique advantages, traditional 300mm round carrier used for processing FOWLP is still cost inhibitive. This paper will present the background of utilizing $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel size and show an example of leveraging from existing equipment for backend processing for cost considerations. We will also review the processing method for 6-sided die protection of a single die and how it translates to $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel processing. Comparisons between usable area of 300mm round carrier versus $mathrm{600}text{mm}times mathrm{600}text{mm}$ square panel, sweet spot recommendation for pricing per unit based on body size and Component Level Reliability (CLR) will be presented.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00150
Daniel Riegel, P. Gromala, B. Han, S. Rzepka
Miniaturization of components and higher operating loads lead to reduced lifetimes. Prognostics and Health Management (PHM) enables predictive maintenance of components whose lifetime is shorter than that of the system they are part of. The key to PHM lies in sensor data that correlates with component degradation. In this study, run-to-failure data sets have been generated using in-situ measurements of on-chip stress sensors. Physical failure analysis has provided the link between the data and remaining useful life.
{"title":"Data-Driven Remaining Useful Life Prediction of QFN Packages on Board Level with On-Chip Stress Sensors","authors":"Daniel Riegel, P. Gromala, B. Han, S. Rzepka","doi":"10.1109/ECTC32696.2021.00150","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00150","url":null,"abstract":"Miniaturization of components and higher operating loads lead to reduced lifetimes. Prognostics and Health Management (PHM) enables predictive maintenance of components whose lifetime is shorter than that of the system they are part of. The key to PHM lies in sensor data that correlates with component degradation. In this study, run-to-failure data sets have been generated using in-situ measurements of on-chip stress sensors. Physical failure analysis has provided the link between the data and remaining useful life.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Next-generation high-performance computing (HPC) platform requires to run at higher speed with higher power consumption levels. Integrated voltage regulators (IVR) with a conversion ratio of 12 V to 1 V can help to reduce the power distribution network (PDN) impedance, increase the voltage conversion efficiency, and increase the regulation bandwidth. In this work, we present a new package embedded inductor array for multi-phase IVRs with a DC resistance as low as $mathrm{22}.mathrm{8} mathrm{m}Omega$. Inductors with three magnetic materials are demonstrated. With one material a small signal inductance as high as 475 nH is obtained, suitable for 12 V to 1 V conversion at 2 MHz. Another material gives an inductance of 192 nH suitable for 12 V to 1 V IVRs at 5 MHz. Each inductor occupies less than 6.25 mm2 and are built with $mathrm{400} mu mathrm{m}$ thick metal polymer composite magnetic sheets. The metric effective AC resistance per unit inductance or $R_{acx}$ is used to predict the inductor performance.
下一代高性能计算(HPC)平台对运行速度和功耗的要求越来越高。IVR (Integrated voltage regulators)集成电压调节器，转换比为12v ～ 1v，可以降低PDN (power distribution network)阻抗，提高电压转换效率，增加调节带宽。在这项工作中，我们提出了一种新的封装嵌入式电感阵列，用于多相ivr，其直流电阻低至$mathrm{22}.mathrm{8} mathrm{m}Omega$。演示了三种磁性材料的电感器。用一种材料可获得高达475 nH的小信号电感，适用于在2mhz下进行12v到1v的转换。另一种材料的电感为192nh，适用于12v至1v的ivr，频率为5mhz。每个电感占地小于6.25平方毫米，并建立与$mathrm{400} mu mathrm{m}$厚金属聚合物复合磁性片。单位电感或$R_{acx}$的度量有效交流电阻用于预测电感的性能。
{"title":"Demonstration of a High-Inductance, High-Density, and Low DC Resistance Compact Embedded Toroidal Inductor for IVR","authors":"Claudio Alvarez, Prahalad Murali, M. Swaminathan, Yusuke Oishi, Junichi Takashiro, Ryo Nagatsuka, Naoki Watanabe","doi":"10.1109/ECTC32696.2021.00209","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00209","url":null,"abstract":"Next-generation high-performance computing (HPC) platform requires to run at higher speed with higher power consumption levels. Integrated voltage regulators (IVR) with a conversion ratio of 12 V to 1 V can help to reduce the power distribution network (PDN) impedance, increase the voltage conversion efficiency, and increase the regulation bandwidth. In this work, we present a new package embedded inductor array for multi-phase IVRs with a DC resistance as low as $mathrm{22}.mathrm{8} mathrm{m}Omega$. Inductors with three magnetic materials are demonstrated. With one material a small signal inductance as high as 475 nH is obtained, suitable for 12 V to 1 V conversion at 2 MHz. Another material gives an inductance of 192 nH suitable for 12 V to 1 V IVRs at 5 MHz. Each inductor occupies less than 6.25 mm2 and are built with $mathrm{400} mu mathrm{m}$ thick metal polymer composite magnetic sheets. The metric effective AC resistance per unit inductance or $R_{acx}$ is used to predict the inductor performance.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114887392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00282
Pan Liu, Liangtao Li, Z. Zeng, Guoqi Zhang, Pengfei Liu, Jon Qingchun Zhang, Jing Zhang
Ultrasonic wire bonding is one of the critical challenges for power semiconductor manufacturing process, especially for silicon carbide (SiC) power devices. Packaging-related strain on the dies is one of the limiting factors for SiC devices scaling towards mass-production. Furthermore, due to the high current demand for SiC power device packaging, thick bond wires are often needed, which brings major challenges for the ultrasonic wire bonding process. Thus, computational simulation methods are under development to assist the wire bonding process. This paper presents a simulation method that can quickly narrow the process window for thick bond wires on SiC power devices beforehand. A process model was created to adapt process parameters of bonding force and power. This model aims to simulate the bond deformation for a discretized bonding area. Wire deformation and equivalent plastic strain were then examined and compared. The model was further validated through experiments. Experimental validation of the wire bonding model reveals a suitable deformation of bond wires, which helps to improve thick wire bonding reliability for power electronics packaging.
{"title":"Ultrasonic Thick Wire Bonding Process Simulation and Validation for Silicon Carbide Power Devices","authors":"Pan Liu, Liangtao Li, Z. Zeng, Guoqi Zhang, Pengfei Liu, Jon Qingchun Zhang, Jing Zhang","doi":"10.1109/ECTC32696.2021.00282","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00282","url":null,"abstract":"Ultrasonic wire bonding is one of the critical challenges for power semiconductor manufacturing process, especially for silicon carbide (SiC) power devices. Packaging-related strain on the dies is one of the limiting factors for SiC devices scaling towards mass-production. Furthermore, due to the high current demand for SiC power device packaging, thick bond wires are often needed, which brings major challenges for the ultrasonic wire bonding process. Thus, computational simulation methods are under development to assist the wire bonding process. This paper presents a simulation method that can quickly narrow the process window for thick bond wires on SiC power devices beforehand. A process model was created to adapt process parameters of bonding force and power. This model aims to simulate the bond deformation for a discretized bonding area. Wire deformation and equivalent plastic strain were then examined and compared. The model was further validated through experiments. Experimental validation of the wire bonding model reveals a suitable deformation of bond wires, which helps to improve thick wire bonding reliability for power electronics packaging.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115016641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：