Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00310
Daiki Yukimori, Mei Kunito, N. Ishikawa, A. Sekiguchi, T. Ogata
In this study, we investigated the design of photosensitive materials with a wide depth of focus (DOF) for use in fine pitch redistribution layers. First, we developed a photosensitive material having a DOF exceeding 4.0 µm with 0.8-µm line/space (L/S) patterns and that having a DOF of 4.0 µm with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, at a numerical aperture (NA) of 0.5. Second, we simulated the DOF to match the experimental DOF using lithography simulation software (PROLITH). Subsequently, we simulated the DOF at an NA of 0.24 and obtained a $mathrm{10}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{8}-mu mathrm{m}$ L/S patterns and a $mathrm{6}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns of the photosensitive material. For a detailed insight of the performance at the NA of 0.24, we conducted an aerial image simulation; we also simulated the impact of three dissolution parameters-$-mathrm{R}_{text{max}}, mathrm{R}_{text{min}}$, and development time—on the DOF. For the $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, we found that precise $mathrm{R}_{text{min}}$ control is essential for a wide DOF. In fact, for an $mathrm{R}_{text{max}}$ ranging from 150 to 1000 nm/s, a precise $mathrm{R}_{text{min}}$ control of less than 0.4 nm/s is required for a $mathrm{7}.mathrm{0}-mu mathrm{m}$ DOF.
{"title":"Study of i-Line Photosensitive Materials with a Wide Depth of Focus for Fine Pitch Redistribution Layers","authors":"Daiki Yukimori, Mei Kunito, N. Ishikawa, A. Sekiguchi, T. Ogata","doi":"10.1109/ECTC32696.2021.00310","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00310","url":null,"abstract":"In this study, we investigated the design of photosensitive materials with a wide depth of focus (DOF) for use in fine pitch redistribution layers. First, we developed a photosensitive material having a DOF exceeding 4.0 µm with 0.8-µm line/space (L/S) patterns and that having a DOF of 4.0 µm with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, at a numerical aperture (NA) of 0.5. Second, we simulated the DOF to match the experimental DOF using lithography simulation software (PROLITH). Subsequently, we simulated the DOF at an NA of 0.24 and obtained a $mathrm{10}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{8}-mu mathrm{m}$ L/S patterns and a $mathrm{6}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns of the photosensitive material. For a detailed insight of the performance at the NA of 0.24, we conducted an aerial image simulation; we also simulated the impact of three dissolution parameters-$-mathrm{R}_{text{max}}, mathrm{R}_{text{min}}$, and development time—on the DOF. For the $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, we found that precise $mathrm{R}_{text{min}}$ control is essential for a wide DOF. In fact, for an $mathrm{R}_{text{max}}$ ranging from 150 to 1000 nm/s, a precise $mathrm{R}_{text{min}}$ control of less than 0.4 nm/s is required for a $mathrm{7}.mathrm{0}-mu mathrm{m}$ DOF.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122043145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a simple method of extracting dielectric material is proposed and copper surface roughness is taken into consideration. The measured results from W-band to D-band are shown to verify the proposed method of extracting complex permittivity of dielectrics. Besides, to validate the proposed transmission line technique, the full sets of complex S-parameters with an appropriate “through-reflect-line” (TRL) calibration pattern are measured as well. It also allows accurate determination of the dielectric constant and loss of thin sheet substrate materials. A great consistency between transmission line technique without calibration and TRL calibration method represents that systematic errors are small. In addition, different samples within the same set of packaging are measured and used to extract dielectric constant and loss tangent, which agree well with each other.
{"title":"Extraction of Complex Permittivity of Dielectrics on Package from W-band to D-band","authors":"Yi-Ting Lin, H. Kuo, Po-I Wu, Ming-Fong Jhong, Po-Chih Pan, Chung-Yuan Liu, Chen-Chao Wang, Tzong-Lin Wu","doi":"10.1109/ECTC32696.2021.00100","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00100","url":null,"abstract":"In this paper, a simple method of extracting dielectric material is proposed and copper surface roughness is taken into consideration. The measured results from W-band to D-band are shown to verify the proposed method of extracting complex permittivity of dielectrics. Besides, to validate the proposed transmission line technique, the full sets of complex S-parameters with an appropriate “through-reflect-line” (TRL) calibration pattern are measured as well. It also allows accurate determination of the dielectric constant and loss of thin sheet substrate materials. A great consistency between transmission line technique without calibration and TRL calibration method represents that systematic errors are small. In addition, different samples within the same set of packaging are measured and used to extract dielectric constant and loss tangent, which agree well with each other.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00326
Thomas Workman, L. Mirkarimi, J. Theil, G. Fountain, K.M. Bang, Bongsub Lee, C. Uzoh, D. Suwito, Guilian Gao, P. Mrozek
Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at $< mathrm{35} mu mathrm{m}$ pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of $2 mumathrm{m}$ pad on $4 mumathrm{m}$ pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The $2 mumathrm{m}$ bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.
随着半导体行业规划下一代封装，需要高带宽架构来实现改进的计算性能需求，混合键合正变得越来越重要。$< mathrm{35} mu mathrm{m}$级焊料互连的可扩展性挑战推动了混合键合技术的采用，这是一种具有增强可扩展性的技术。直接键合互连(DBI®)技术最初是为晶圆到晶圆(W2W)应用而开发的，现已扩展到晶圆到晶圆(D2W)，成为DBI®Ultra。本文讨论了一种新型晶圆混合键合试验车的试验结果，该试验车采用$2 mumathrm{m}$衬垫在$4 mumathrm{m}$节上的互连设计。8毫米× 12毫米的芯片包含菊花链测试结构，从126,000到1,600,000个链接。采用常规的隐形切割方法对元件晶片进行单晶化，然后在带架上进行加工，制备D2W键合。$2 mumathrm{m}$键合垫要求在拾取和放置工具内的亚微米对准精度为100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.
{"title":"Die to Wafer Hybrid Bonding and Fine Pitch Considerations","authors":"Thomas Workman, L. Mirkarimi, J. Theil, G. Fountain, K.M. Bang, Bongsub Lee, C. Uzoh, D. Suwito, Guilian Gao, P. Mrozek","doi":"10.1109/ECTC32696.2021.00326","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00326","url":null,"abstract":"Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at $< mathrm{35} mu mathrm{m}$ pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of $2 mumathrm{m}$ pad on $4 mumathrm{m}$ pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The $2 mumathrm{m}$ bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00165
Choongpyo Jeon, Youngsung Choi, K. Rhew, Jinsoo Bae, Yeungjung Cho, S. Pae
Solid state drive (SSD) is widely used for modern computing systems. As design of systems becomes more complex, concern for thermal fatigue lifetime has enlarged by increasing thermo-mechanical stress. Thermal cycling test (TCT) is the most common and important reliability item to determine solder joint reliability. The differences between the TCT conditions at component manufacturer's sites and the user environment, however, can cause a change in fatigue lifetime and failure location because of the difference in mechanical load condition such as housing, connector, screw and so on. For that reason, a proper test method is required reflecting various environmental and field conditions. This paper proposes a novel TCT method that is designed in considering the mounted condition of M.2 next generation form factor (NGFF) SSD. The reliability assessment was conducted in two temperature range and loading conditions, and the test results were analyzed on a SSD level test equipment and a test program. Test result show acceleration relationship is verified by temperature acceleration. Test jig reflecting real use environment was manufactured to verify the differences between the loading conditions. In the case of mounting SSD to test jig, Weibull characteristic parameters were degraded. Test results show shape parameter is decreased from 6.25 to 2.02, and 10 percent life is also decreased 60.7 percent with SSD mounting condition. Failure location was changed from solder on NAND side to solder between DRAM and controller side according to the loading condition. This implies that it is completely different reliability assessment depending on whether the jig is applied or not. Failure analysis was conducted by cross section analysis method. Finite element analysis (FEA) was conducted to understand the failure location and stress level changes caused by test conditions. These results are verified by strain measurement of each location. The strain rate of the point of DRAM and controller side was increased by approximately 20 percent due to applying test jig, and the increase in strain rate leads to an initial lifetime deterioration. This work provides the results of the impact of loading conditions under TCT of M.2 SSD. In conclusion, the cause of reliability characteristics degradation and failure location change derived from the difference in loading conditions of M.2 SSD is investigated, and more accurate modeling and evaluation methodology for predicting product level reliability characteristics are introduced. Thus, SSD level reliability test design reflecting a condition mounted on end-products is needed to verify more accurate reliability prediction.
{"title":"A Systematic Study and Lifetime Modeling on the Board Level Reliability of SSD after Temperature Cycling Test","authors":"Choongpyo Jeon, Youngsung Choi, K. Rhew, Jinsoo Bae, Yeungjung Cho, S. Pae","doi":"10.1109/ECTC32696.2021.00165","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00165","url":null,"abstract":"Solid state drive (SSD) is widely used for modern computing systems. As design of systems becomes more complex, concern for thermal fatigue lifetime has enlarged by increasing thermo-mechanical stress. Thermal cycling test (TCT) is the most common and important reliability item to determine solder joint reliability. The differences between the TCT conditions at component manufacturer's sites and the user environment, however, can cause a change in fatigue lifetime and failure location because of the difference in mechanical load condition such as housing, connector, screw and so on. For that reason, a proper test method is required reflecting various environmental and field conditions. This paper proposes a novel TCT method that is designed in considering the mounted condition of M.2 next generation form factor (NGFF) SSD. The reliability assessment was conducted in two temperature range and loading conditions, and the test results were analyzed on a SSD level test equipment and a test program. Test result show acceleration relationship is verified by temperature acceleration. Test jig reflecting real use environment was manufactured to verify the differences between the loading conditions. In the case of mounting SSD to test jig, Weibull characteristic parameters were degraded. Test results show shape parameter is decreased from 6.25 to 2.02, and 10 percent life is also decreased 60.7 percent with SSD mounting condition. Failure location was changed from solder on NAND side to solder between DRAM and controller side according to the loading condition. This implies that it is completely different reliability assessment depending on whether the jig is applied or not. Failure analysis was conducted by cross section analysis method. Finite element analysis (FEA) was conducted to understand the failure location and stress level changes caused by test conditions. These results are verified by strain measurement of each location. The strain rate of the point of DRAM and controller side was increased by approximately 20 percent due to applying test jig, and the increase in strain rate leads to an initial lifetime deterioration. This work provides the results of the impact of loading conditions under TCT of M.2 SSD. In conclusion, the cause of reliability characteristics degradation and failure location change derived from the difference in loading conditions of M.2 SSD is investigated, and more accurate modeling and evaluation methodology for predicting product level reliability characteristics are introduced. Thus, SSD level reliability test design reflecting a condition mounted on end-products is needed to verify more accurate reliability prediction.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00220
Valeriy Khaldarov, Dongji Xie, J. Lee, A. Shalumov
In this paper, a methodology is developed to test the durability of microelectronics subjected to vibrations at the board level. This type of analysis plays a critical role in assessing the overall reliability of the printed circuit assemblies used in harsh environmental conditions such as automotive applications which include vibration and temperature cycling. Such requirements can arise due to the general trend of mounting power electronics out of the relatively benign and protected traditional passenger compartment to the much harsher under the hood environment of engines and transmissions. Harsh environmental conditions can cause not only mechanical failures in device housings such as electronic control units used in the automotive applications but also create electrical failures in the printed circuit assemblies mounted inside the housing due to bending and printed circuit board deformation. These electrical failures may result from various failure modes such as circuit board cracking, board trace cracking, solder interconnection cracking, pad cratering, via failures, and component cracks. As a result, an initiative is being undertaken in updating the EIA/JEDEC JESD22-B103B standard which currently defines some vibration test parameters on the component level without specifying an appropriate test vehicle. In order to provide more meaningful test results data, the overall goal will be to place the emphasis on the board level by developing corresponding test methods which may include various levels of sinusoidal and random vibrations along with possible temperature cycling tests for automotive as well as other applications. Some preliminary testing has been carried out by different laboratories of the JESD22 working group participants. However due to varying capabilities of each testing laboratory the main challenge is to provide consistent results interpretation and comparison through simulation analysis which will be presented in this study.
{"title":"New Methodologies for Evaluating Microelectronics Subject to Board-level Vibrations","authors":"Valeriy Khaldarov, Dongji Xie, J. Lee, A. Shalumov","doi":"10.1109/ECTC32696.2021.00220","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00220","url":null,"abstract":"In this paper, a methodology is developed to test the durability of microelectronics subjected to vibrations at the board level. This type of analysis plays a critical role in assessing the overall reliability of the printed circuit assemblies used in harsh environmental conditions such as automotive applications which include vibration and temperature cycling. Such requirements can arise due to the general trend of mounting power electronics out of the relatively benign and protected traditional passenger compartment to the much harsher under the hood environment of engines and transmissions. Harsh environmental conditions can cause not only mechanical failures in device housings such as electronic control units used in the automotive applications but also create electrical failures in the printed circuit assemblies mounted inside the housing due to bending and printed circuit board deformation. These electrical failures may result from various failure modes such as circuit board cracking, board trace cracking, solder interconnection cracking, pad cratering, via failures, and component cracks. As a result, an initiative is being undertaken in updating the EIA/JEDEC JESD22-B103B standard which currently defines some vibration test parameters on the component level without specifying an appropriate test vehicle. In order to provide more meaningful test results data, the overall goal will be to place the emphasis on the board level by developing corresponding test methods which may include various levels of sinusoidal and random vibrations along with possible temperature cycling tests for automotive as well as other applications. Some preliminary testing has been carried out by different laboratories of the JESD22 working group participants. However due to varying capabilities of each testing laboratory the main challenge is to provide consistent results interpretation and comparison through simulation analysis which will be presented in this study.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124070715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00163
K. Shie, Po-Ning Hsu, Yu-Jin Li, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen
Because Cu-Cu bonding is the key technique in 3D IC packaging, its reliabilities will become issues in the future. In this study, Cu-Cu joints with underfill was fabricated by using instant bonding process, in which bonding conditions were under 31∼90 MPa at 300 °C for 10∼30 s. Several samples underwent two reliability tests: temperature cycling test (TCT) and electromigration (EM) test. These samples passed 1000 cycles TCT, and the measured EM life time was least 3 times longer than that of solder joints with similar dimension. Failure mechanisms of reliability tests were examined by cross-section images and finite element analysis. In TCT, cracks were formed at bonding interface because it is relative weak compared to the neighboring structures. For EM tests, voids were formed at passivation opening of joints with current crowding. The current study provides a fundamental understanding in the reliabilities of Cu/organic dielectric hybrid bonding structures.
{"title":"Electromigration and Temperature Cycling Tests of Cu-Cu Joints Fabricated by Instant Copper Direct Bonding","authors":"K. Shie, Po-Ning Hsu, Yu-Jin Li, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen","doi":"10.1109/ECTC32696.2021.00163","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00163","url":null,"abstract":"Because Cu-Cu bonding is the key technique in 3D IC packaging, its reliabilities will become issues in the future. In this study, Cu-Cu joints with underfill was fabricated by using instant bonding process, in which bonding conditions were under 31∼90 MPa at 300 °C for 10∼30 s. Several samples underwent two reliability tests: temperature cycling test (TCT) and electromigration (EM) test. These samples passed 1000 cycles TCT, and the measured EM life time was least 3 times longer than that of solder joints with similar dimension. Failure mechanisms of reliability tests were examined by cross-section images and finite element analysis. In TCT, cracks were formed at bonding interface because it is relative weak compared to the neighboring structures. For EM tests, voids were formed at passivation opening of joints with current crowding. The current study provides a fundamental understanding in the reliabilities of Cu/organic dielectric hybrid bonding structures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125749438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00333
Huaneng Su, Cheng-Che Tsou, Auger Horng
In this article, the polyimide formation at high pressure for advanced assembly technology is reported for the first time. Polyimides are formed in a pneumatic oven for evaluation of voids and cycle times. For comparison and production evaluation, the polyimides were fabricated by curing photo-definable aqueous developers with different recipes and batches of wafers, respectively. For the recipes in the pneumatic oven, instead of the multistep thermal cycles, the ramp-up time and curing time could be reduced drastically to enhance the production throughput. Furthermore, as shown in optical microscope (OM) results, no void was found for the pneumatic oven samples, and lots of voids were detected for the normal oven ones. This innovation enables manufacturers to reduce 36% of process cycle time. The polyimide cyclization rate was estimated from the signal strength ratio by using Fourier-transform infrared spectroscopy (FTIR). The thermal stability by using a thermogravimetric analyzer (TGA) and the glass transition temperature by thermomechanical analysis (TMA) was analyzed to clarify the properties of the polyimides for these recipes. The results show no obvious difference is observed between pneumatic cured polyimides and normal-oven cured ones. Mechanical strength and outgassing were enhanced for the pneumatic-oven samples and no oxidation was found after pneumatic curing due to the well-controlled oxygen content of the oven.
{"title":"Effect of Pneumatic Curing on Cycle Time Reduction and Void Suppression of Polyimide Wafer Coating","authors":"Huaneng Su, Cheng-Che Tsou, Auger Horng","doi":"10.1109/ECTC32696.2021.00333","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00333","url":null,"abstract":"In this article, the polyimide formation at high pressure for advanced assembly technology is reported for the first time. Polyimides are formed in a pneumatic oven for evaluation of voids and cycle times. For comparison and production evaluation, the polyimides were fabricated by curing photo-definable aqueous developers with different recipes and batches of wafers, respectively. For the recipes in the pneumatic oven, instead of the multistep thermal cycles, the ramp-up time and curing time could be reduced drastically to enhance the production throughput. Furthermore, as shown in optical microscope (OM) results, no void was found for the pneumatic oven samples, and lots of voids were detected for the normal oven ones. This innovation enables manufacturers to reduce 36% of process cycle time. The polyimide cyclization rate was estimated from the signal strength ratio by using Fourier-transform infrared spectroscopy (FTIR). The thermal stability by using a thermogravimetric analyzer (TGA) and the glass transition temperature by thermomechanical analysis (TMA) was analyzed to clarify the properties of the polyimides for these recipes. The results show no obvious difference is observed between pneumatic cured polyimides and normal-oven cured ones. Mechanical strength and outgassing were enhanced for the pneumatic-oven samples and no oxidation was found after pneumatic curing due to the well-controlled oxygen content of the oven.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00300
Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen
Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.
{"title":"Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters","authors":"Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen","doi":"10.1109/ECTC32696.2021.00300","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00300","url":null,"abstract":"Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126147743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00050
Lim Teck Guan, Eva Wai Leong Ching, Jong Ming Ching, Loh Woon Leng, D. Wee, S. Bhattacharya
A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC (PIC) are described here. These two platforms are capable to support high-speed integration and scalable design of the next generation Optical Engine. The integration of the PIC on the FOWLP is achieved by a simple novel solution. An additional section of the Si substrate is designed at the end of the PIC to protect the optical I/Os during the FOWLP embedding process. For the Through Si-Interposer, besides providing the EIC and PIC, it include the passive alignment feature for the fibre to the PIC assembly.
{"title":"FOWLP and Si-Interposer for High-Speed Photonic Packaging","authors":"Lim Teck Guan, Eva Wai Leong Ching, Jong Ming Ching, Loh Woon Leng, D. Wee, S. Bhattacharya","doi":"10.1109/ECTC32696.2021.00050","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00050","url":null,"abstract":"A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC (PIC) are described here. These two platforms are capable to support high-speed integration and scalable design of the next generation Optical Engine. The integration of the PIC on the FOWLP is achieved by a simple novel solution. An additional section of the Si substrate is designed at the end of the PIC to protect the optical I/Os during the FOWLP embedding process. For the Through Si-Interposer, besides providing the EIC and PIC, it include the passive alignment feature for the fibre to the PIC assembly.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129482207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00277
Juno Kim, K. Lim, S. Hahn, Mingu Lee, D. Rhee
A new characterization method for interfacial adhesion between die to die hybrid bonding interface at chip level is developed to evaluate and analyze the adhesion strength. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3DIC Heterogeneous. However, there is no proven methodology or guideline to characterize the die level hybrid bonding strength which is very much dependent on the surface treatment process parameters, the physical and chemical characteristics of the bonding interfaces and particles and so on. To improve the quality and reliability of the die level hybrid bonding interface, it is crucial to identify well defined characterization methodology, especially for the thin die case which is no more applicable by using conventionally used die shear test method. In this paper, the authors developed novel characterization method of die level hybrid bonded interface strength by applying the single cantilever method using thin die with a thickness of $100 mumathrm{m}$. To optimize the test specimen design and testing condition, the finite element analysis (FEA) is performed. Using the optimized methodology, a series of experiments for characterizing the die to die bonding strength are conducted at various load-point lengths, bonding lengths and annealing temperatures. Based on the FEA and experimental data, the limitations and prospects of the developed characterization method are discussed in detail.
{"title":"Novel Characterization Method of Chip Level Hybrid Bonding Strength","authors":"Juno Kim, K. Lim, S. Hahn, Mingu Lee, D. Rhee","doi":"10.1109/ECTC32696.2021.00277","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00277","url":null,"abstract":"A new characterization method for interfacial adhesion between die to die hybrid bonding interface at chip level is developed to evaluate and analyze the adhesion strength. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3DIC Heterogeneous. However, there is no proven methodology or guideline to characterize the die level hybrid bonding strength which is very much dependent on the surface treatment process parameters, the physical and chemical characteristics of the bonding interfaces and particles and so on. To improve the quality and reliability of the die level hybrid bonding interface, it is crucial to identify well defined characterization methodology, especially for the thin die case which is no more applicable by using conventionally used die shear test method. In this paper, the authors developed novel characterization method of die level hybrid bonded interface strength by applying the single cantilever method using thin die with a thickness of $100 mumathrm{m}$. To optimize the test specimen design and testing condition, the finite element analysis (FEA) is performed. Using the optimized methodology, a series of experiments for characterizing the die to die bonding strength are conducted at various load-point lengths, bonding lengths and annealing temperatures. Based on the FEA and experimental data, the limitations and prospects of the developed characterization method are discussed in detail.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128509414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：