Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00017
Y. Susumago, T. Odashima, M. Ichikawa, Hiroki Hanaoka, H. Kino, Tetsu Tanaka, T. Fukushima
This paper deals with a flexible 3D-IC system fabrication methodology. Mini-LEDs and 3D-IC chiplets divided from a large 3D-IC with Cu-TSVs are embedded in an elastomer PDMS based on die-first FOWLP for heterogeneously integrating them into Smart Skin Display as a biomedical/wearable FHE (flexible hybrid electronics). We address a serious die-shift issue for the tiny chips in die-first FOWLP by using a new anchoring layer technique to drastically reduce the shift within $2.7 mumathrm{m}$ including assembly positioning errors. The mechanical/electrical properties of the flexible array of 3D-IC chiplets are characterized before and after repeated bending with a curvature radius of 10 mm. In addition, stress neutral axes are designed to stably endure bending cycle applicable to the biomedical/wearable FHE with multi-level metallization.
本文讨论了一种灵活的3D-IC系统制造方法。mini - led和3D-IC芯片从带有cu - tsv的大型3D-IC中分离出来，嵌入基于模首FOWLP的弹性体PDMS中，用于将它们作为生物医学/可穿戴FHE(柔性混合电子产品)异构集成到智能皮肤显示中。我们通过使用一种新的锚定层技术，解决了模具优先级FOWLP中微小芯片的严重模移问题，将模移大幅度减少在$2.7 mu mathm {m}$内，包括装配定位误差。在曲率半径为10 mm的情况下，对3D-IC芯片柔性阵列的力学/电学性能进行了表征。此外，应力中性轴的设计可以稳定地承受弯曲循环，适用于多层次金属化的生物医学/可穿戴FHE。
{"title":"FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin Display","authors":"Y. Susumago, T. Odashima, M. Ichikawa, Hiroki Hanaoka, H. Kino, Tetsu Tanaka, T. Fukushima","doi":"10.1109/ECTC32696.2021.00017","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00017","url":null,"abstract":"This paper deals with a flexible 3D-IC system fabrication methodology. Mini-LEDs and 3D-IC chiplets divided from a large 3D-IC with Cu-TSVs are embedded in an elastomer PDMS based on die-first FOWLP for heterogeneously integrating them into Smart Skin Display as a biomedical/wearable FHE (flexible hybrid electronics). We address a serious die-shift issue for the tiny chips in die-first FOWLP by using a new anchoring layer technique to drastically reduce the shift within $2.7 mumathrm{m}$ including assembly positioning errors. The mechanical/electrical properties of the flexible array of 3D-IC chiplets are characterized before and after repeated bending with a curvature radius of 10 mm. In addition, stress neutral axes are designed to stably endure bending cycle applicable to the biomedical/wearable FHE with multi-level metallization.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124402014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00197
S. Krause, R. Andersson, M. Bylund, V. Marknäs, A. Saleem, Elisa Passalaqua, Shafiq Kabir, V. Desmaris
A physics-based model is presented that captures the electrical high-frequency behavior of low-dimensional nanostructures used in emerging technologies such as the ultra-high-density capacitor. Derived from transmission line theory the analytical expression provides a frequency-dependent admittance of a lossy nanostructure, which can be numerically integrated over arbitrary areas comprising the nanostructure. Edge effects, a distributed nature of resistivity or dimensions of the nanostructure comprising the device can be taken into consideration and make it a powerful tool for designing future integrated circuits. The model predictions show an excellent match with hardware measurements up to 3 GHz on state-of-the-art carbon nanofiber based MIM-capacitors with capacitance densities up to 500 nF/mm2 at $mathrm{6} mu mathrm{m}$ device height.
提出了一种基于物理的模型，用于捕获用于新兴技术(如超高密度电容器)的低维纳米结构的电高频行为。由传输线理论导出的解析表达式提供了损耗纳米结构的频率相关导纳，可以在包含纳米结构的任意区域上进行数值积分。可以考虑边缘效应、电阻率的分布性质或组成器件的纳米结构的尺寸，使其成为设计未来集成电路的有力工具。模型预测显示，在最先进的基于碳纳米纤维的mim电容器上，在$ mathm {6} mu mathm {m}$器件高度上，电容密度高达500 nF/mm2，硬件测量高达3 GHz，与模型预测非常匹配。
{"title":"High-frequency electrical circuit model for integrated capacitors utilizing lossy nanostructures","authors":"S. Krause, R. Andersson, M. Bylund, V. Marknäs, A. Saleem, Elisa Passalaqua, Shafiq Kabir, V. Desmaris","doi":"10.1109/ECTC32696.2021.00197","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00197","url":null,"abstract":"A physics-based model is presented that captures the electrical high-frequency behavior of low-dimensional nanostructures used in emerging technologies such as the ultra-high-density capacitor. Derived from transmission line theory the analytical expression provides a frequency-dependent admittance of a lossy nanostructure, which can be numerically integrated over arbitrary areas comprising the nanostructure. Edge effects, a distributed nature of resistivity or dimensions of the nanostructure comprising the device can be taken into consideration and make it a powerful tool for designing future integrated circuits. The model predictions show an excellent match with hardware measurements up to 3 GHz on state-of-the-art carbon nanofiber based MIM-capacitors with capacitance densities up to 500 nF/mm2 at $mathrm{6} mu mathrm{m}$ device height.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114787531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00274
Heeseok Lee, Jisoo Hwang, Henry H. Kwon, Junso Pak
The impact of non-zero warpage on signal delivery characteristics is presented by analyzing transmission line on curved plane defined in cylindrical coordinate system. Authors will present a compact finite-difference frequency-domain method for quasi-TEM mode (C-FDFD-QT) with cylindrical coordinate system, which is a promising method to determine the characteristic impedance with efficiently reduced size of computational matrix by using quasi-TEM approximation. In summary, the non-zero warpage of large-size substrate constructing large size FC-BGA results in the increase of characteristic impedance, which has been quantitatively studied by using C-FDTD-QT. The characteristic impedance of stripline on curved plane is larger than that of stripline on the plane whose warpage is zero.
{"title":"Impact of warpage on signal delivery with large size FC-PBGA package","authors":"Heeseok Lee, Jisoo Hwang, Henry H. Kwon, Junso Pak","doi":"10.1109/ECTC32696.2021.00274","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00274","url":null,"abstract":"The impact of non-zero warpage on signal delivery characteristics is presented by analyzing transmission line on curved plane defined in cylindrical coordinate system. Authors will present a compact finite-difference frequency-domain method for quasi-TEM mode (C-FDFD-QT) with cylindrical coordinate system, which is a promising method to determine the characteristic impedance with efficiently reduced size of computational matrix by using quasi-TEM approximation. In summary, the non-zero warpage of large-size substrate constructing large size FC-BGA results in the increase of characteristic impedance, which has been quantitatively studied by using C-FDTD-QT. The characteristic impedance of stripline on curved plane is larger than that of stripline on the plane whose warpage is zero.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114376221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00308
Dong-hwan Kim, Aesun Oh, Eunyoung Park, Kyung-Hyun Kim, Sung-Jae Jeon, Hyun-Cheol Bae
In this study, a 1700V/58A SiC MOSFET was used as the TO-247 module instead of the existing Si TO-247 module to analyze the thermal and electrical characteristics of a high-power module. The TO-247 module was manufactured to measure the electrical characteristics under thermal cycle testing (−40 to 125°C). The substrates used in the fabrication were standard TO-247 substrates, AlN DBC with high thermal conductivity, and Si3N4 AMB with high mechanical properties. The PbSn preform of the conventional solder base and a highly reliable Ag sintering paste were used as the bonding materials. For interconnection, wire bonding, which is most used in modules, and Cu clips attached using heterogeneous bonding materials were used in the TO-247 module. A total of 100 cycles were carried out, and Trr and RDS(on) were measured every 50 cycles to assess the electrical characteristics. The thermal analysis of the maximum temperature difference between the substrates, bonding materials, and interconnections was performed by adding a Cu clip bonding. The electrical properties were measured during the thermal cycling. all samples performed better than the 1700V/58A SiC MOSFET datasheet and operated normally after 100 cycles. Additionally, the maximum temperature difference between the Al wire and Cu clip bonding was not significant in the standard TO-247 module. However, using Cu clip bonding is more effective in reducing temperature when high heat is generated using substrates with low thermal conductivity.
本研究采用1700V/58A SiC MOSFET代替现有的Si to -247模块作为to -247模块，分析大功率模块的热电特性。to -247模块用于测量热循环测试(- 40至125°C)下的电气特性。采用标准的TO-247衬底、高导热系数的AlN DBC和高机械性能的Si3N4 AMB作为衬底。采用传统焊料基的PbSn预制体和高可靠的银烧结浆料作为粘结材料。为了实现互连，TO-247模块采用了模块中最常用的线键合和异质键合材料连接的Cu夹。共进行100次循环，每50次循环测量Trr和RDS(on)，以评估电特性。通过添加铜夹键合，对衬底、键合材料和互连之间的最大温差进行了热分析。在热循环过程中测量了电学性能。所有样品的性能都优于1700V/58A SiC MOSFET数据表，并且在100次循环后正常工作。此外，在标准的TO-247模块中，Al线和Cu夹接之间的最大温差并不显著。然而，当使用导热系数低的衬底产生高热量时，使用铜夹键合更有效地降低温度。
{"title":"Thermal and electrical reliability analysis of TO-247 for bonding method, substrate structure and heat dissipation bonding material","authors":"Dong-hwan Kim, Aesun Oh, Eunyoung Park, Kyung-Hyun Kim, Sung-Jae Jeon, Hyun-Cheol Bae","doi":"10.1109/ECTC32696.2021.00308","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00308","url":null,"abstract":"In this study, a 1700V/58A SiC MOSFET was used as the TO-247 module instead of the existing Si TO-247 module to analyze the thermal and electrical characteristics of a high-power module. The TO-247 module was manufactured to measure the electrical characteristics under thermal cycle testing (−40 to 125°C). The substrates used in the fabrication were standard TO-247 substrates, AlN DBC with high thermal conductivity, and Si3N4 AMB with high mechanical properties. The PbSn preform of the conventional solder base and a highly reliable Ag sintering paste were used as the bonding materials. For interconnection, wire bonding, which is most used in modules, and Cu clips attached using heterogeneous bonding materials were used in the TO-247 module. A total of 100 cycles were carried out, and Trr and RDS(on) were measured every 50 cycles to assess the electrical characteristics. The thermal analysis of the maximum temperature difference between the substrates, bonding materials, and interconnections was performed by adding a Cu clip bonding. The electrical properties were measured during the thermal cycling. all samples performed better than the 1700V/58A SiC MOSFET datasheet and operated normally after 100 cycles. Additionally, the maximum temperature difference between the Al wire and Cu clip bonding was not significant in the standard TO-247 module. However, using Cu clip bonding is more effective in reducing temperature when high heat is generated using substrates with low thermal conductivity.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00310
Daiki Yukimori, Mei Kunito, N. Ishikawa, A. Sekiguchi, T. Ogata
In this study, we investigated the design of photosensitive materials with a wide depth of focus (DOF) for use in fine pitch redistribution layers. First, we developed a photosensitive material having a DOF exceeding 4.0 µm with 0.8-µm line/space (L/S) patterns and that having a DOF of 4.0 µm with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, at a numerical aperture (NA) of 0.5. Second, we simulated the DOF to match the experimental DOF using lithography simulation software (PROLITH). Subsequently, we simulated the DOF at an NA of 0.24 and obtained a $mathrm{10}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{8}-mu mathrm{m}$ L/S patterns and a $mathrm{6}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns of the photosensitive material. For a detailed insight of the performance at the NA of 0.24, we conducted an aerial image simulation; we also simulated the impact of three dissolution parameters-$-mathrm{R}_{text{max}}, mathrm{R}_{text{min}}$, and development time—on the DOF. For the $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, we found that precise $mathrm{R}_{text{min}}$ control is essential for a wide DOF. In fact, for an $mathrm{R}_{text{max}}$ ranging from 150 to 1000 nm/s, a precise $mathrm{R}_{text{min}}$ control of less than 0.4 nm/s is required for a $mathrm{7}.mathrm{0}-mu mathrm{m}$ DOF.
{"title":"Study of i-Line Photosensitive Materials with a Wide Depth of Focus for Fine Pitch Redistribution Layers","authors":"Daiki Yukimori, Mei Kunito, N. Ishikawa, A. Sekiguchi, T. Ogata","doi":"10.1109/ECTC32696.2021.00310","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00310","url":null,"abstract":"In this study, we investigated the design of photosensitive materials with a wide depth of focus (DOF) for use in fine pitch redistribution layers. First, we developed a photosensitive material having a DOF exceeding 4.0 µm with 0.8-µm line/space (L/S) patterns and that having a DOF of 4.0 µm with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, at a numerical aperture (NA) of 0.5. Second, we simulated the DOF to match the experimental DOF using lithography simulation software (PROLITH). Subsequently, we simulated the DOF at an NA of 0.24 and obtained a $mathrm{10}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{8}-mu mathrm{m}$ L/S patterns and a $mathrm{6}.mathrm{8}-mu mathrm{m}$ DOF with $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns of the photosensitive material. For a detailed insight of the performance at the NA of 0.24, we conducted an aerial image simulation; we also simulated the impact of three dissolution parameters-$-mathrm{R}_{text{max}}, mathrm{R}_{text{min}}$, and development time—on the DOF. For the $mathrm{0}.mathrm{7}-mu mathrm{m}$ L/S patterns, we found that precise $mathrm{R}_{text{min}}$ control is essential for a wide DOF. In fact, for an $mathrm{R}_{text{max}}$ ranging from 150 to 1000 nm/s, a precise $mathrm{R}_{text{min}}$ control of less than 0.4 nm/s is required for a $mathrm{7}.mathrm{0}-mu mathrm{m}$ DOF.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122043145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a simple method of extracting dielectric material is proposed and copper surface roughness is taken into consideration. The measured results from W-band to D-band are shown to verify the proposed method of extracting complex permittivity of dielectrics. Besides, to validate the proposed transmission line technique, the full sets of complex S-parameters with an appropriate “through-reflect-line” (TRL) calibration pattern are measured as well. It also allows accurate determination of the dielectric constant and loss of thin sheet substrate materials. A great consistency between transmission line technique without calibration and TRL calibration method represents that systematic errors are small. In addition, different samples within the same set of packaging are measured and used to extract dielectric constant and loss tangent, which agree well with each other.
{"title":"Extraction of Complex Permittivity of Dielectrics on Package from W-band to D-band","authors":"Yi-Ting Lin, H. Kuo, Po-I Wu, Ming-Fong Jhong, Po-Chih Pan, Chung-Yuan Liu, Chen-Chao Wang, Tzong-Lin Wu","doi":"10.1109/ECTC32696.2021.00100","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00100","url":null,"abstract":"In this paper, a simple method of extracting dielectric material is proposed and copper surface roughness is taken into consideration. The measured results from W-band to D-band are shown to verify the proposed method of extracting complex permittivity of dielectrics. Besides, to validate the proposed transmission line technique, the full sets of complex S-parameters with an appropriate “through-reflect-line” (TRL) calibration pattern are measured as well. It also allows accurate determination of the dielectric constant and loss of thin sheet substrate materials. A great consistency between transmission line technique without calibration and TRL calibration method represents that systematic errors are small. In addition, different samples within the same set of packaging are measured and used to extract dielectric constant and loss tangent, which agree well with each other.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00326
Thomas Workman, L. Mirkarimi, J. Theil, G. Fountain, K.M. Bang, Bongsub Lee, C. Uzoh, D. Suwito, Guilian Gao, P. Mrozek
Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at $< mathrm{35} mu mathrm{m}$ pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of $2 mumathrm{m}$ pad on $4 mumathrm{m}$ pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The $2 mumathrm{m}$ bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.
随着半导体行业规划下一代封装，需要高带宽架构来实现改进的计算性能需求，混合键合正变得越来越重要。$< mathrm{35} mu mathrm{m}$级焊料互连的可扩展性挑战推动了混合键合技术的采用，这是一种具有增强可扩展性的技术。直接键合互连(DBI®)技术最初是为晶圆到晶圆(W2W)应用而开发的，现已扩展到晶圆到晶圆(D2W)，成为DBI®Ultra。本文讨论了一种新型晶圆混合键合试验车的试验结果，该试验车采用$2 mumathrm{m}$衬垫在$4 mumathrm{m}$节上的互连设计。8毫米× 12毫米的芯片包含菊花链测试结构，从126,000到1,600,000个链接。采用常规的隐形切割方法对元件晶片进行单晶化，然后在带架上进行加工，制备D2W键合。$2 mumathrm{m}$键合垫要求在拾取和放置工具内的亚微米对准精度为100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.
{"title":"Die to Wafer Hybrid Bonding and Fine Pitch Considerations","authors":"Thomas Workman, L. Mirkarimi, J. Theil, G. Fountain, K.M. Bang, Bongsub Lee, C. Uzoh, D. Suwito, Guilian Gao, P. Mrozek","doi":"10.1109/ECTC32696.2021.00326","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00326","url":null,"abstract":"Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at $< mathrm{35} mu mathrm{m}$ pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of $2 mumathrm{m}$ pad on $4 mumathrm{m}$ pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The $2 mumathrm{m}$ bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of $+/- 3 mumathrm{m} (3 sigma)$. The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a $10 mumathrm{m}$ pad on $40 mumathrm{m}$ pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00165
Choongpyo Jeon, Youngsung Choi, K. Rhew, Jinsoo Bae, Yeungjung Cho, S. Pae
Solid state drive (SSD) is widely used for modern computing systems. As design of systems becomes more complex, concern for thermal fatigue lifetime has enlarged by increasing thermo-mechanical stress. Thermal cycling test (TCT) is the most common and important reliability item to determine solder joint reliability. The differences between the TCT conditions at component manufacturer's sites and the user environment, however, can cause a change in fatigue lifetime and failure location because of the difference in mechanical load condition such as housing, connector, screw and so on. For that reason, a proper test method is required reflecting various environmental and field conditions. This paper proposes a novel TCT method that is designed in considering the mounted condition of M.2 next generation form factor (NGFF) SSD. The reliability assessment was conducted in two temperature range and loading conditions, and the test results were analyzed on a SSD level test equipment and a test program. Test result show acceleration relationship is verified by temperature acceleration. Test jig reflecting real use environment was manufactured to verify the differences between the loading conditions. In the case of mounting SSD to test jig, Weibull characteristic parameters were degraded. Test results show shape parameter is decreased from 6.25 to 2.02, and 10 percent life is also decreased 60.7 percent with SSD mounting condition. Failure location was changed from solder on NAND side to solder between DRAM and controller side according to the loading condition. This implies that it is completely different reliability assessment depending on whether the jig is applied or not. Failure analysis was conducted by cross section analysis method. Finite element analysis (FEA) was conducted to understand the failure location and stress level changes caused by test conditions. These results are verified by strain measurement of each location. The strain rate of the point of DRAM and controller side was increased by approximately 20 percent due to applying test jig, and the increase in strain rate leads to an initial lifetime deterioration. This work provides the results of the impact of loading conditions under TCT of M.2 SSD. In conclusion, the cause of reliability characteristics degradation and failure location change derived from the difference in loading conditions of M.2 SSD is investigated, and more accurate modeling and evaluation methodology for predicting product level reliability characteristics are introduced. Thus, SSD level reliability test design reflecting a condition mounted on end-products is needed to verify more accurate reliability prediction.
{"title":"A Systematic Study and Lifetime Modeling on the Board Level Reliability of SSD after Temperature Cycling Test","authors":"Choongpyo Jeon, Youngsung Choi, K. Rhew, Jinsoo Bae, Yeungjung Cho, S. Pae","doi":"10.1109/ECTC32696.2021.00165","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00165","url":null,"abstract":"Solid state drive (SSD) is widely used for modern computing systems. As design of systems becomes more complex, concern for thermal fatigue lifetime has enlarged by increasing thermo-mechanical stress. Thermal cycling test (TCT) is the most common and important reliability item to determine solder joint reliability. The differences between the TCT conditions at component manufacturer's sites and the user environment, however, can cause a change in fatigue lifetime and failure location because of the difference in mechanical load condition such as housing, connector, screw and so on. For that reason, a proper test method is required reflecting various environmental and field conditions. This paper proposes a novel TCT method that is designed in considering the mounted condition of M.2 next generation form factor (NGFF) SSD. The reliability assessment was conducted in two temperature range and loading conditions, and the test results were analyzed on a SSD level test equipment and a test program. Test result show acceleration relationship is verified by temperature acceleration. Test jig reflecting real use environment was manufactured to verify the differences between the loading conditions. In the case of mounting SSD to test jig, Weibull characteristic parameters were degraded. Test results show shape parameter is decreased from 6.25 to 2.02, and 10 percent life is also decreased 60.7 percent with SSD mounting condition. Failure location was changed from solder on NAND side to solder between DRAM and controller side according to the loading condition. This implies that it is completely different reliability assessment depending on whether the jig is applied or not. Failure analysis was conducted by cross section analysis method. Finite element analysis (FEA) was conducted to understand the failure location and stress level changes caused by test conditions. These results are verified by strain measurement of each location. The strain rate of the point of DRAM and controller side was increased by approximately 20 percent due to applying test jig, and the increase in strain rate leads to an initial lifetime deterioration. This work provides the results of the impact of loading conditions under TCT of M.2 SSD. In conclusion, the cause of reliability characteristics degradation and failure location change derived from the difference in loading conditions of M.2 SSD is investigated, and more accurate modeling and evaluation methodology for predicting product level reliability characteristics are introduced. Thus, SSD level reliability test design reflecting a condition mounted on end-products is needed to verify more accurate reliability prediction.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00220
Valeriy Khaldarov, Dongji Xie, J. Lee, A. Shalumov
In this paper, a methodology is developed to test the durability of microelectronics subjected to vibrations at the board level. This type of analysis plays a critical role in assessing the overall reliability of the printed circuit assemblies used in harsh environmental conditions such as automotive applications which include vibration and temperature cycling. Such requirements can arise due to the general trend of mounting power electronics out of the relatively benign and protected traditional passenger compartment to the much harsher under the hood environment of engines and transmissions. Harsh environmental conditions can cause not only mechanical failures in device housings such as electronic control units used in the automotive applications but also create electrical failures in the printed circuit assemblies mounted inside the housing due to bending and printed circuit board deformation. These electrical failures may result from various failure modes such as circuit board cracking, board trace cracking, solder interconnection cracking, pad cratering, via failures, and component cracks. As a result, an initiative is being undertaken in updating the EIA/JEDEC JESD22-B103B standard which currently defines some vibration test parameters on the component level without specifying an appropriate test vehicle. In order to provide more meaningful test results data, the overall goal will be to place the emphasis on the board level by developing corresponding test methods which may include various levels of sinusoidal and random vibrations along with possible temperature cycling tests for automotive as well as other applications. Some preliminary testing has been carried out by different laboratories of the JESD22 working group participants. However due to varying capabilities of each testing laboratory the main challenge is to provide consistent results interpretation and comparison through simulation analysis which will be presented in this study.
{"title":"New Methodologies for Evaluating Microelectronics Subject to Board-level Vibrations","authors":"Valeriy Khaldarov, Dongji Xie, J. Lee, A. Shalumov","doi":"10.1109/ECTC32696.2021.00220","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00220","url":null,"abstract":"In this paper, a methodology is developed to test the durability of microelectronics subjected to vibrations at the board level. This type of analysis plays a critical role in assessing the overall reliability of the printed circuit assemblies used in harsh environmental conditions such as automotive applications which include vibration and temperature cycling. Such requirements can arise due to the general trend of mounting power electronics out of the relatively benign and protected traditional passenger compartment to the much harsher under the hood environment of engines and transmissions. Harsh environmental conditions can cause not only mechanical failures in device housings such as electronic control units used in the automotive applications but also create electrical failures in the printed circuit assemblies mounted inside the housing due to bending and printed circuit board deformation. These electrical failures may result from various failure modes such as circuit board cracking, board trace cracking, solder interconnection cracking, pad cratering, via failures, and component cracks. As a result, an initiative is being undertaken in updating the EIA/JEDEC JESD22-B103B standard which currently defines some vibration test parameters on the component level without specifying an appropriate test vehicle. In order to provide more meaningful test results data, the overall goal will be to place the emphasis on the board level by developing corresponding test methods which may include various levels of sinusoidal and random vibrations along with possible temperature cycling tests for automotive as well as other applications. Some preliminary testing has been carried out by different laboratories of the JESD22 working group participants. However due to varying capabilities of each testing laboratory the main challenge is to provide consistent results interpretation and comparison through simulation analysis which will be presented in this study.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124070715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00163
K. Shie, Po-Ning Hsu, Yu-Jin Li, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen
Because Cu-Cu bonding is the key technique in 3D IC packaging, its reliabilities will become issues in the future. In this study, Cu-Cu joints with underfill was fabricated by using instant bonding process, in which bonding conditions were under 31∼90 MPa at 300 °C for 10∼30 s. Several samples underwent two reliability tests: temperature cycling test (TCT) and electromigration (EM) test. These samples passed 1000 cycles TCT, and the measured EM life time was least 3 times longer than that of solder joints with similar dimension. Failure mechanisms of reliability tests were examined by cross-section images and finite element analysis. In TCT, cracks were formed at bonding interface because it is relative weak compared to the neighboring structures. For EM tests, voids were formed at passivation opening of joints with current crowding. The current study provides a fundamental understanding in the reliabilities of Cu/organic dielectric hybrid bonding structures.
{"title":"Electromigration and Temperature Cycling Tests of Cu-Cu Joints Fabricated by Instant Copper Direct Bonding","authors":"K. Shie, Po-Ning Hsu, Yu-Jin Li, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen","doi":"10.1109/ECTC32696.2021.00163","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00163","url":null,"abstract":"Because Cu-Cu bonding is the key technique in 3D IC packaging, its reliabilities will become issues in the future. In this study, Cu-Cu joints with underfill was fabricated by using instant bonding process, in which bonding conditions were under 31∼90 MPa at 300 °C for 10∼30 s. Several samples underwent two reliability tests: temperature cycling test (TCT) and electromigration (EM) test. These samples passed 1000 cycles TCT, and the measured EM life time was least 3 times longer than that of solder joints with similar dimension. Failure mechanisms of reliability tests were examined by cross-section images and finite element analysis. In TCT, cracks were formed at bonding interface because it is relative weak compared to the neighboring structures. For EM tests, voids were formed at passivation opening of joints with current crowding. The current study provides a fundamental understanding in the reliabilities of Cu/organic dielectric hybrid bonding structures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125749438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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