Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00257
Guangqi Ouyang, Grace Whang, Emily MacInnis, S. Iyer
To improve the flexibility of Li-ion batteries for powering wearables, we develop a simple battery interconnection method on FlexTrate™ to fabricate a thin-film flexible Li-ion battery matrix by using ionic liquid electrolyte, commercial lithium iron phosphate (LFP) cathode, and Li-metal anode. The mechanical fatigue process of the Li-ion cathode materials during is analyzed. The thin-film battery achieves 1.33 mAh/cm2 energy density at C/10 charging/discharging rate after 1000 times bending cycles at 5 mm bending radius.
{"title":"Fabrication of Flexible Ionic-Liquid Thin Film Battery Matrix on FlexTrate™ for Powering Wearable Devices","authors":"Guangqi Ouyang, Grace Whang, Emily MacInnis, S. Iyer","doi":"10.1109/ECTC32696.2021.00257","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00257","url":null,"abstract":"To improve the flexibility of Li-ion batteries for powering wearables, we develop a simple battery interconnection method on FlexTrate™ to fabricate a thin-film flexible Li-ion battery matrix by using ionic liquid electrolyte, commercial lithium iron phosphate (LFP) cathode, and Li-metal anode. The mechanical fatigue process of the Li-ion cathode materials during is analyzed. The thin-film battery achieves 1.33 mAh/cm2 energy density at C/10 charging/discharging rate after 1000 times bending cycles at 5 mm bending radius.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00324
Junghwa Kim, James Jeong, Heejung Choi, Jisoo Hwang, J. Pak, Heeseok Lee
This paper suggests a unique silicon capacitor shape to provide a very competitive package form-factor with limited height condition. To locate a discrete capacitor on the BGA side of package, some solder balls must be depopulated to secure capacitor mounting space. Also to implement silicon based multi terminal capacitor with fine pitch bumped format, a conventional capillary underfill dispensing keep out zone should be considered. The removed solder balls may affect the system PDN with the decreased power connection or overall X-Y dimension expansion with the increased SOC functionality. To find an optimized shape and size against various BGA arrangement option, it is very important to have a successful product solution. A comparative study of various design concept of normal rectangular and polygonal shape of capacitor on BGA side with respect to area usage efficiency, maximum ball usage, and power integrity performance enhancement for high-density small form-factor package is described in this paper. The number of depopulated solder balls will be increased according to the use of multiple capacitors with rectangular shape. But, it can be optimized with one big polygonal shape and multiterminal of silicon capacitor. Interposer POP package for mobile device will be used as a target package type and the latest structure of substrate and ball pitch will be used for the study to reflect a realistic scenario.
{"title":"High-Density Small Form-Factor Package with Polygon-Shaped Capacitor Based on Silicon Technology","authors":"Junghwa Kim, James Jeong, Heejung Choi, Jisoo Hwang, J. Pak, Heeseok Lee","doi":"10.1109/ECTC32696.2021.00324","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00324","url":null,"abstract":"This paper suggests a unique silicon capacitor shape to provide a very competitive package form-factor with limited height condition. To locate a discrete capacitor on the BGA side of package, some solder balls must be depopulated to secure capacitor mounting space. Also to implement silicon based multi terminal capacitor with fine pitch bumped format, a conventional capillary underfill dispensing keep out zone should be considered. The removed solder balls may affect the system PDN with the decreased power connection or overall X-Y dimension expansion with the increased SOC functionality. To find an optimized shape and size against various BGA arrangement option, it is very important to have a successful product solution. A comparative study of various design concept of normal rectangular and polygonal shape of capacitor on BGA side with respect to area usage efficiency, maximum ball usage, and power integrity performance enhancement for high-density small form-factor package is described in this paper. The number of depopulated solder balls will be increased according to the use of multiple capacitors with rectangular shape. But, it can be optimized with one big polygonal shape and multiterminal of silicon capacitor. Interposer POP package for mobile device will be used as a target package type and the latest structure of substrate and ball pitch will be used for the study to reflect a realistic scenario.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130091223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00270
Yu-Chang Hsieh, Pao-Nan Lee, Chen-Chao Wang
Inter-digital and hairpin mmWave diplexer design and simulation based on two types technology: fan-out structure and build-up substrate for n257/n258 and n260 bands in 5G new radio (NR) are demonstrated in this paper. Fan-out structure has advantage of thin profile and smaller process variation. However, high loss dielectric material is a big concern that will increase the loss, especially in mm-wave band. On the other hand, conventional packaging substrate is believed to have smaller insertion loss due to various low loss material options, but the disadvantage is large process tolerance that probably results in significant RF performance variation. The objective of this paper is to study the pros and cons of conventional packaging substrate and advanced fan-out substrate from electrical point of view.
{"title":"Design and Simulation of mm-Wave Diplexer on Substrate and Fan-Out Structure","authors":"Yu-Chang Hsieh, Pao-Nan Lee, Chen-Chao Wang","doi":"10.1109/ECTC32696.2021.00270","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00270","url":null,"abstract":"Inter-digital and hairpin mmWave diplexer design and simulation based on two types technology: fan-out structure and build-up substrate for n257/n258 and n260 bands in 5G new radio (NR) are demonstrated in this paper. Fan-out structure has advantage of thin profile and smaller process variation. However, high loss dielectric material is a big concern that will increase the loss, especially in mm-wave band. On the other hand, conventional packaging substrate is believed to have smaller insertion loss due to various low loss material options, but the disadvantage is large process tolerance that probably results in significant RF performance variation. The objective of this paper is to study the pros and cons of conventional packaging substrate and advanced fan-out substrate from electrical point of view.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130102022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00206
Taeyun Kim, Chanmin Jo, S. Moon
This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.
{"title":"Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications","authors":"Taeyun Kim, Chanmin Jo, S. Moon","doi":"10.1109/ECTC32696.2021.00206","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00206","url":null,"abstract":"This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00092
K. Agawa, Tokihiko Mori, R. Ninomiya, M. Takizawa, Takayasu Sakurai
An IoT edge platform, where desired IoT nodes are realized selecting and connecting several single-function printed circuit boards (PCBs) such as a sensor, microprocessor, and power supply unit with anisotropic conductive rubber (ACR) connectors, is demonstrated. The PCBs are called “leaf PCBs” and their dimensions are typically $mathrm{2} text{cm}times mathrm{2} text{cm}$. Small rubber connectors are employed to connect these PCBs so that soldering is unnecessary and removable and replaceable structure is realized for customizability of IoT nodes. A wire connection mechanism is also developed to connect wires between leaf PCBs and external devices such as motors and sensors. It is smaller than conventional terminal blocks. To investigate important performance of the proposed connection schemes, temperature cycle tests for ACR connectors and retention strength tests for wire connection mechanisms are carried out.
{"title":"Novel Connector Mechanism Using Anisotropic Conductive Rubber for Trillion-Node Engine as an IoT Edge Platform","authors":"K. Agawa, Tokihiko Mori, R. Ninomiya, M. Takizawa, Takayasu Sakurai","doi":"10.1109/ECTC32696.2021.00092","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00092","url":null,"abstract":"An IoT edge platform, where desired IoT nodes are realized selecting and connecting several single-function printed circuit boards (PCBs) such as a sensor, microprocessor, and power supply unit with anisotropic conductive rubber (ACR) connectors, is demonstrated. The PCBs are called “leaf PCBs” and their dimensions are typically $mathrm{2} text{cm}times mathrm{2} text{cm}$. Small rubber connectors are employed to connect these PCBs so that soldering is unnecessary and removable and replaceable structure is realized for customizability of IoT nodes. A wire connection mechanism is also developed to connect wires between leaf PCBs and external devices such as motors and sensors. It is smaller than conventional terminal blocks. To investigate important performance of the proposed connection schemes, temperature cycle tests for ACR connectors and retention strength tests for wire connection mechanisms are carried out.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00060
M. Mariappan, K. Mori, M. Koyanagi, T. Fukushima
° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barrier/seed layers or Cu electroplating (EP). The WNi protection layer was also checked for (i) its platability of Cu by both EL and EP methods (the void-free formation of Cu-TSVs by direct Cu-EPing over WNi layer), (ii) its barrier performance against Cu diffusion (from the absence of Cu singal in both WNi and Si region of Auger electron depth profile), (iii) its adhession nature (intactness of film after the tape-peel test), and (iv) its endurance during Cu-CMP (chemical mechanical polishing). All the results confimed that PVD formed WNi not only protects the M1 metal layer from the EL or EP bath, but also forms a very good barrier-cum-seed layer in the Cu-TSVs.
°研究了物理气相沉积(PVD)在M1(金属级1)上形成的WNi薄膜，该薄膜在通过-最后通过- si -孔(TSV)工艺暴露后，在化学(EL)镀阻挡层/种子层或镀铜(EP)期间保护M1金属的能力。WNi保护层还通过EL和EP方法(通过直接Cu-EP在WNi层上形成无空洞的Cu- tsv)， (ii)其对Cu扩散的阻挡性能(从俄歇电子深度剖面的WNi和Si区域中缺乏Cu信号)，(iii)其附着力(胶带剥离测试后薄膜的完整性)，以及(iv)其在Cu- cmp(化学机械抛光)过程中的耐久性。这些结果证实了PVD形成的WNi不仅可以保护M1金属层免受EL或EP浴的伤害，而且可以在cu - tsv中形成很好的阻挡和种子层。
{"title":"A TSV-Last Approach for 3D-IC Integration and Packaging using WNi Platable Barrier Layer","authors":"M. Mariappan, K. Mori, M. Koyanagi, T. Fukushima","doi":"10.1109/ECTC32696.2021.00060","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00060","url":null,"abstract":"° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barrier/seed layers or Cu electroplating (EP). The WNi protection layer was also checked for (i) its platability of Cu by both EL and EP methods (the void-free formation of Cu-TSVs by direct Cu-EPing over WNi layer), (ii) its barrier performance against Cu diffusion (from the absence of Cu singal in both WNi and Si region of Auger electron depth profile), (iii) its adhession nature (intactness of film after the tape-peel test), and (iv) its endurance during Cu-CMP (chemical mechanical polishing). All the results confimed that PVD formed WNi not only protects the M1 metal layer from the EL or EP bath, but also forms a very good barrier-cum-seed layer in the Cu-TSVs.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122371187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00054
P. Zhao, Hong Yu Li, J. Tao, Y. Lim, W. Seit, L. Guidoni, C. S. Tan
In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of −0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.
{"title":"Heterogenous Integration of Silicon Ion Trap and Glass Interposer for Scalable Quantum Computing Enabled by TSV, Micro-bumps and RDL","authors":"P. Zhao, Hong Yu Li, J. Tao, Y. Lim, W. Seit, L. Guidoni, C. S. Tan","doi":"10.1109/ECTC32696.2021.00054","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00054","url":null,"abstract":"In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of −0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130572723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00312
Junbo Yang, Yangyang Lai, K. Pan, Jiefeng Xu, Travis Mikjaniec, S. Cain, Seungbae Park
All electronic packages will induce excess heat during usage and heat dissipation methods were developed to remove spare heat from the die in order to improve reliability. Thermal interface materials (TIMs) are one of the key solutions to decrease the thermal resistance between the power device and heat sink. There are a wide variety of TIM material types in electronic packages. Thermal grease is a thermally conductive chemical with high thermal conductivity and commonly used for high-power packages. Phase change materials (PCMs) which are epoxy-based polymer with some thermally conductive fillers will soften with heat and change state from solid to semi-solid and semi-liquid. Compare to thermal grease, PCMs are easy to assemble and no need to dry-out and reduced the voids, pump-out, or delamination. In this study, PCMs and thermal grease during thermal cycling and power cycling were studied. For power cycling, heaters were built inside the die and corresponding thermal sensors were designed to spread all over the die to monitor the thermal resistance changes which reflect temperature changes through the cycling. Wind speed and loading pressure were set as working conditions. According to the resistance of each heater, adjust current to keep total power a constant. After cycling, TIM material behaviors were analyzed. The performance of PCMs and thermal grease under thermal cycling and power cycling and the effect of the degradation of these TIMs are studied and discussed. Based on experiment results, PCMs has better performance in thermal cycle test but thermal grease is more stable than PCMs in power cycle test.
{"title":"A comparison study of TIM degradation of phase change material and thermal grease","authors":"Junbo Yang, Yangyang Lai, K. Pan, Jiefeng Xu, Travis Mikjaniec, S. Cain, Seungbae Park","doi":"10.1109/ECTC32696.2021.00312","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00312","url":null,"abstract":"All electronic packages will induce excess heat during usage and heat dissipation methods were developed to remove spare heat from the die in order to improve reliability. Thermal interface materials (TIMs) are one of the key solutions to decrease the thermal resistance between the power device and heat sink. There are a wide variety of TIM material types in electronic packages. Thermal grease is a thermally conductive chemical with high thermal conductivity and commonly used for high-power packages. Phase change materials (PCMs) which are epoxy-based polymer with some thermally conductive fillers will soften with heat and change state from solid to semi-solid and semi-liquid. Compare to thermal grease, PCMs are easy to assemble and no need to dry-out and reduced the voids, pump-out, or delamination. In this study, PCMs and thermal grease during thermal cycling and power cycling were studied. For power cycling, heaters were built inside the die and corresponding thermal sensors were designed to spread all over the die to monitor the thermal resistance changes which reflect temperature changes through the cycling. Wind speed and loading pressure were set as working conditions. According to the resistance of each heater, adjust current to keep total power a constant. After cycling, TIM material behaviors were analyzed. The performance of PCMs and thermal grease under thermal cycling and power cycling and the effect of the degradation of these TIMs are studied and discussed. Based on experiment results, PCMs has better performance in thermal cycle test but thermal grease is more stable than PCMs in power cycle test.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00086
Huang Chen, Xiuyu Shi, Jin Wang, Yang Hu, Qian Wang, Jian Cai
High density, fine pitch wafer level bonding technology is necessary for heterogeneous integration. However, underfill would be a challenging when bonding pitch decreases. Hybrid bonding technology with metal-to-metal and passivation-to-passivation bonding simultaneously was considered as a feasible solution. In this work, a hybrid bonding scheme with asymmetric embedded Cu-Sn/Cu bumps structure was investigated. Photosensitive BCB used as passivation materials was coated on only one side of bonding pairs. This asymmetric structure allows for precise alignment. BCB curing and Cu-Sn Solid-liquid-diffusion bonding were both achieved under the temperature of 250°C. The thickness of BCB and metal was concisely designed considering the volume shrinking of polymer during bonding process. To achieve void free hybrid bonding interface, efforts were mainly paid to some key aspects. Surface pre-treatment were firstly introduced to ensure no oxidation and residual polymer on the surface of bumps before bonding. A combination of plasma and formic gas treatment were adopted. Furthermore, considering coefficients of thermal expansion (CTE) mismatch of BCB and embedded bumps, a compatible bonding process with well-matched temperature and stress was proposed and optimized to get a void-free bonding interface under the guidance of independent variable test result. Bonding interface microstructure was observed and mechanical test, electrical test of Kelvin and daisy-chain structure were performed to evaluate bonding quality, also reliability test which included HTST and TCT had been carried out. The results confirmed that embedded bump hybrid bonding would be a convincing technology for future 3D integration.
高密度、细间距晶圆级键合技术是实现异质集成的必要条件。然而，当粘接间距减小时，下填料将是一个挑战。同时采用金属-金属和钝化-钝化键合的杂化键合技术是可行的解决方案。本文研究了不对称嵌入Cu- sn /Cu凸点结构的杂化键合方案。作为钝化材料的光敏BCB仅涂覆在键对的一侧。这种非对称结构允许精确对准。在250℃的温度下，实现了BCB固化和Cu-Sn固-液-扩散键合。考虑到聚合物在粘接过程中的体积收缩，对BCB和金属的厚度进行了简明的设计。为实现无空隙杂化键合界面，重点从几个关键方面进行了研究。首先介绍了表面预处理，以确保在粘合前凸点表面无氧化和残留聚合物。采用等离子体和甲醛气相结合的处理方法。在自变量试验结果的指导下，考虑BCB热膨胀系数(CTE)与嵌入凸点的失配，提出并优化了温度与应力匹配良好的兼容键合工艺，得到无空洞的键合界面。观察粘接界面微观结构，进行力学试验、Kelvin试验和菊链结构电学试验评价粘接质量，并进行HTST和TCT可靠性试验。结果证实，嵌入式凹凸混合键合将是未来3D集成的一种令人信服的技术。
{"title":"Development of Hybrid Bonding Process for Embedded Bump with Cu-Sn/BCB Structure","authors":"Huang Chen, Xiuyu Shi, Jin Wang, Yang Hu, Qian Wang, Jian Cai","doi":"10.1109/ECTC32696.2021.00086","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00086","url":null,"abstract":"High density, fine pitch wafer level bonding technology is necessary for heterogeneous integration. However, underfill would be a challenging when bonding pitch decreases. Hybrid bonding technology with metal-to-metal and passivation-to-passivation bonding simultaneously was considered as a feasible solution. In this work, a hybrid bonding scheme with asymmetric embedded Cu-Sn/Cu bumps structure was investigated. Photosensitive BCB used as passivation materials was coated on only one side of bonding pairs. This asymmetric structure allows for precise alignment. BCB curing and Cu-Sn Solid-liquid-diffusion bonding were both achieved under the temperature of 250°C. The thickness of BCB and metal was concisely designed considering the volume shrinking of polymer during bonding process. To achieve void free hybrid bonding interface, efforts were mainly paid to some key aspects. Surface pre-treatment were firstly introduced to ensure no oxidation and residual polymer on the surface of bumps before bonding. A combination of plasma and formic gas treatment were adopted. Furthermore, considering coefficients of thermal expansion (CTE) mismatch of BCB and embedded bumps, a compatible bonding process with well-matched temperature and stress was proposed and optimized to get a void-free bonding interface under the guidance of independent variable test result. Bonding interface microstructure was observed and mechanical test, electrical test of Kelvin and daisy-chain structure were performed to evaluate bonding quality, also reliability test which included HTST and TCT had been carried out. The results confirmed that embedded bump hybrid bonding would be a convincing technology for future 3D integration.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00063
M. D. Rotaru, Li Kangrong
Wide and slow bus interfaces such as High Bandwidth Memory (HBM) and Advanced Interface Bus (AIB) are the main drivers behind the development and implementation of technologies such as Embedded Multi-die Interconnect Bridge (EMIB) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies can create very dense interconnect structures using back end of line (BEOL) approaches used to interconnect chiplets and to form functional system in package applications. With recent improvements in fabrication and process technologies organic based high density redistribution layer approaches such HD-FOWLP have become popular alternatives to EMIB and CoWoS. Redistribution layers with $2text{um}times 2text{um}$ cross section and 2um space between adjacent lines or $1text{um}times 1text{um}$ cross section with a minimum spacing of 1um have become achievable with the current fabrication technology. In this work the electrical design challenges in organic based fine RDL packages have been studied via simulation and electrical measurements.
{"title":"Electrical design challenges in High Bandwidth Memory and Advanced Interface Bus interfaces on HD-FOWLP technology","authors":"M. D. Rotaru, Li Kangrong","doi":"10.1109/ECTC32696.2021.00063","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00063","url":null,"abstract":"Wide and slow bus interfaces such as High Bandwidth Memory (HBM) and Advanced Interface Bus (AIB) are the main drivers behind the development and implementation of technologies such as Embedded Multi-die Interconnect Bridge (EMIB) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies can create very dense interconnect structures using back end of line (BEOL) approaches used to interconnect chiplets and to form functional system in package applications. With recent improvements in fabrication and process technologies organic based high density redistribution layer approaches such HD-FOWLP have become popular alternatives to EMIB and CoWoS. Redistribution layers with $2text{um}times 2text{um}$ cross section and 2um space between adjacent lines or $1text{um}times 1text{um}$ cross section with a minimum spacing of 1um have become achievable with the current fabrication technology. In this work the electrical design challenges in organic based fine RDL packages have been studied via simulation and electrical measurements.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128823741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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