Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00092
K. Agawa, Tokihiko Mori, R. Ninomiya, M. Takizawa, Takayasu Sakurai
An IoT edge platform, where desired IoT nodes are realized selecting and connecting several single-function printed circuit boards (PCBs) such as a sensor, microprocessor, and power supply unit with anisotropic conductive rubber (ACR) connectors, is demonstrated. The PCBs are called “leaf PCBs” and their dimensions are typically $mathrm{2} text{cm}times mathrm{2} text{cm}$. Small rubber connectors are employed to connect these PCBs so that soldering is unnecessary and removable and replaceable structure is realized for customizability of IoT nodes. A wire connection mechanism is also developed to connect wires between leaf PCBs and external devices such as motors and sensors. It is smaller than conventional terminal blocks. To investigate important performance of the proposed connection schemes, temperature cycle tests for ACR connectors and retention strength tests for wire connection mechanisms are carried out.
{"title":"Novel Connector Mechanism Using Anisotropic Conductive Rubber for Trillion-Node Engine as an IoT Edge Platform","authors":"K. Agawa, Tokihiko Mori, R. Ninomiya, M. Takizawa, Takayasu Sakurai","doi":"10.1109/ECTC32696.2021.00092","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00092","url":null,"abstract":"An IoT edge platform, where desired IoT nodes are realized selecting and connecting several single-function printed circuit boards (PCBs) such as a sensor, microprocessor, and power supply unit with anisotropic conductive rubber (ACR) connectors, is demonstrated. The PCBs are called “leaf PCBs” and their dimensions are typically $mathrm{2} text{cm}times mathrm{2} text{cm}$. Small rubber connectors are employed to connect these PCBs so that soldering is unnecessary and removable and replaceable structure is realized for customizability of IoT nodes. A wire connection mechanism is also developed to connect wires between leaf PCBs and external devices such as motors and sensors. It is smaller than conventional terminal blocks. To investigate important performance of the proposed connection schemes, temperature cycle tests for ACR connectors and retention strength tests for wire connection mechanisms are carried out.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00060
M. Mariappan, K. Mori, M. Koyanagi, T. Fukushima
° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barrier/seed layers or Cu electroplating (EP). The WNi protection layer was also checked for (i) its platability of Cu by both EL and EP methods (the void-free formation of Cu-TSVs by direct Cu-EPing over WNi layer), (ii) its barrier performance against Cu diffusion (from the absence of Cu singal in both WNi and Si region of Auger electron depth profile), (iii) its adhession nature (intactness of film after the tape-peel test), and (iv) its endurance during Cu-CMP (chemical mechanical polishing). All the results confimed that PVD formed WNi not only protects the M1 metal layer from the EL or EP bath, but also forms a very good barrier-cum-seed layer in the Cu-TSVs.
°研究了物理气相沉积(PVD)在M1(金属级1)上形成的WNi薄膜，该薄膜在通过-最后通过- si -孔(TSV)工艺暴露后，在化学(EL)镀阻挡层/种子层或镀铜(EP)期间保护M1金属的能力。WNi保护层还通过EL和EP方法(通过直接Cu-EP在WNi层上形成无空洞的Cu- tsv)， (ii)其对Cu扩散的阻挡性能(从俄歇电子深度剖面的WNi和Si区域中缺乏Cu信号)，(iii)其附着力(胶带剥离测试后薄膜的完整性)，以及(iv)其在Cu- cmp(化学机械抛光)过程中的耐久性。这些结果证实了PVD形成的WNi不仅可以保护M1金属层免受EL或EP浴的伤害，而且可以在cu - tsv中形成很好的阻挡和种子层。
{"title":"A TSV-Last Approach for 3D-IC Integration and Packaging using WNi Platable Barrier Layer","authors":"M. Mariappan, K. Mori, M. Koyanagi, T. Fukushima","doi":"10.1109/ECTC32696.2021.00060","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00060","url":null,"abstract":"° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barrier/seed layers or Cu electroplating (EP). The WNi protection layer was also checked for (i) its platability of Cu by both EL and EP methods (the void-free formation of Cu-TSVs by direct Cu-EPing over WNi layer), (ii) its barrier performance against Cu diffusion (from the absence of Cu singal in both WNi and Si region of Auger electron depth profile), (iii) its adhession nature (intactness of film after the tape-peel test), and (iv) its endurance during Cu-CMP (chemical mechanical polishing). All the results confimed that PVD formed WNi not only protects the M1 metal layer from the EL or EP bath, but also forms a very good barrier-cum-seed layer in the Cu-TSVs.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122371187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00054
P. Zhao, Hong Yu Li, J. Tao, Y. Lim, W. Seit, L. Guidoni, C. S. Tan
In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of −0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.
{"title":"Heterogenous Integration of Silicon Ion Trap and Glass Interposer for Scalable Quantum Computing Enabled by TSV, Micro-bumps and RDL","authors":"P. Zhao, Hong Yu Li, J. Tao, Y. Lim, W. Seit, L. Guidoni, C. S. Tan","doi":"10.1109/ECTC32696.2021.00054","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00054","url":null,"abstract":"In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of −0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130572723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00312
Junbo Yang, Yangyang Lai, K. Pan, Jiefeng Xu, Travis Mikjaniec, S. Cain, Seungbae Park
All electronic packages will induce excess heat during usage and heat dissipation methods were developed to remove spare heat from the die in order to improve reliability. Thermal interface materials (TIMs) are one of the key solutions to decrease the thermal resistance between the power device and heat sink. There are a wide variety of TIM material types in electronic packages. Thermal grease is a thermally conductive chemical with high thermal conductivity and commonly used for high-power packages. Phase change materials (PCMs) which are epoxy-based polymer with some thermally conductive fillers will soften with heat and change state from solid to semi-solid and semi-liquid. Compare to thermal grease, PCMs are easy to assemble and no need to dry-out and reduced the voids, pump-out, or delamination. In this study, PCMs and thermal grease during thermal cycling and power cycling were studied. For power cycling, heaters were built inside the die and corresponding thermal sensors were designed to spread all over the die to monitor the thermal resistance changes which reflect temperature changes through the cycling. Wind speed and loading pressure were set as working conditions. According to the resistance of each heater, adjust current to keep total power a constant. After cycling, TIM material behaviors were analyzed. The performance of PCMs and thermal grease under thermal cycling and power cycling and the effect of the degradation of these TIMs are studied and discussed. Based on experiment results, PCMs has better performance in thermal cycle test but thermal grease is more stable than PCMs in power cycle test.
{"title":"A comparison study of TIM degradation of phase change material and thermal grease","authors":"Junbo Yang, Yangyang Lai, K. Pan, Jiefeng Xu, Travis Mikjaniec, S. Cain, Seungbae Park","doi":"10.1109/ECTC32696.2021.00312","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00312","url":null,"abstract":"All electronic packages will induce excess heat during usage and heat dissipation methods were developed to remove spare heat from the die in order to improve reliability. Thermal interface materials (TIMs) are one of the key solutions to decrease the thermal resistance between the power device and heat sink. There are a wide variety of TIM material types in electronic packages. Thermal grease is a thermally conductive chemical with high thermal conductivity and commonly used for high-power packages. Phase change materials (PCMs) which are epoxy-based polymer with some thermally conductive fillers will soften with heat and change state from solid to semi-solid and semi-liquid. Compare to thermal grease, PCMs are easy to assemble and no need to dry-out and reduced the voids, pump-out, or delamination. In this study, PCMs and thermal grease during thermal cycling and power cycling were studied. For power cycling, heaters were built inside the die and corresponding thermal sensors were designed to spread all over the die to monitor the thermal resistance changes which reflect temperature changes through the cycling. Wind speed and loading pressure were set as working conditions. According to the resistance of each heater, adjust current to keep total power a constant. After cycling, TIM material behaviors were analyzed. The performance of PCMs and thermal grease under thermal cycling and power cycling and the effect of the degradation of these TIMs are studied and discussed. Based on experiment results, PCMs has better performance in thermal cycle test but thermal grease is more stable than PCMs in power cycle test.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00086
Huang Chen, Xiuyu Shi, Jin Wang, Yang Hu, Qian Wang, Jian Cai
High density, fine pitch wafer level bonding technology is necessary for heterogeneous integration. However, underfill would be a challenging when bonding pitch decreases. Hybrid bonding technology with metal-to-metal and passivation-to-passivation bonding simultaneously was considered as a feasible solution. In this work, a hybrid bonding scheme with asymmetric embedded Cu-Sn/Cu bumps structure was investigated. Photosensitive BCB used as passivation materials was coated on only one side of bonding pairs. This asymmetric structure allows for precise alignment. BCB curing and Cu-Sn Solid-liquid-diffusion bonding were both achieved under the temperature of 250°C. The thickness of BCB and metal was concisely designed considering the volume shrinking of polymer during bonding process. To achieve void free hybrid bonding interface, efforts were mainly paid to some key aspects. Surface pre-treatment were firstly introduced to ensure no oxidation and residual polymer on the surface of bumps before bonding. A combination of plasma and formic gas treatment were adopted. Furthermore, considering coefficients of thermal expansion (CTE) mismatch of BCB and embedded bumps, a compatible bonding process with well-matched temperature and stress was proposed and optimized to get a void-free bonding interface under the guidance of independent variable test result. Bonding interface microstructure was observed and mechanical test, electrical test of Kelvin and daisy-chain structure were performed to evaluate bonding quality, also reliability test which included HTST and TCT had been carried out. The results confirmed that embedded bump hybrid bonding would be a convincing technology for future 3D integration.
高密度、细间距晶圆级键合技术是实现异质集成的必要条件。然而，当粘接间距减小时，下填料将是一个挑战。同时采用金属-金属和钝化-钝化键合的杂化键合技术是可行的解决方案。本文研究了不对称嵌入Cu- sn /Cu凸点结构的杂化键合方案。作为钝化材料的光敏BCB仅涂覆在键对的一侧。这种非对称结构允许精确对准。在250℃的温度下，实现了BCB固化和Cu-Sn固-液-扩散键合。考虑到聚合物在粘接过程中的体积收缩，对BCB和金属的厚度进行了简明的设计。为实现无空隙杂化键合界面，重点从几个关键方面进行了研究。首先介绍了表面预处理，以确保在粘合前凸点表面无氧化和残留聚合物。采用等离子体和甲醛气相结合的处理方法。在自变量试验结果的指导下，考虑BCB热膨胀系数(CTE)与嵌入凸点的失配，提出并优化了温度与应力匹配良好的兼容键合工艺，得到无空洞的键合界面。观察粘接界面微观结构，进行力学试验、Kelvin试验和菊链结构电学试验评价粘接质量，并进行HTST和TCT可靠性试验。结果证实，嵌入式凹凸混合键合将是未来3D集成的一种令人信服的技术。
{"title":"Development of Hybrid Bonding Process for Embedded Bump with Cu-Sn/BCB Structure","authors":"Huang Chen, Xiuyu Shi, Jin Wang, Yang Hu, Qian Wang, Jian Cai","doi":"10.1109/ECTC32696.2021.00086","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00086","url":null,"abstract":"High density, fine pitch wafer level bonding technology is necessary for heterogeneous integration. However, underfill would be a challenging when bonding pitch decreases. Hybrid bonding technology with metal-to-metal and passivation-to-passivation bonding simultaneously was considered as a feasible solution. In this work, a hybrid bonding scheme with asymmetric embedded Cu-Sn/Cu bumps structure was investigated. Photosensitive BCB used as passivation materials was coated on only one side of bonding pairs. This asymmetric structure allows for precise alignment. BCB curing and Cu-Sn Solid-liquid-diffusion bonding were both achieved under the temperature of 250°C. The thickness of BCB and metal was concisely designed considering the volume shrinking of polymer during bonding process. To achieve void free hybrid bonding interface, efforts were mainly paid to some key aspects. Surface pre-treatment were firstly introduced to ensure no oxidation and residual polymer on the surface of bumps before bonding. A combination of plasma and formic gas treatment were adopted. Furthermore, considering coefficients of thermal expansion (CTE) mismatch of BCB and embedded bumps, a compatible bonding process with well-matched temperature and stress was proposed and optimized to get a void-free bonding interface under the guidance of independent variable test result. Bonding interface microstructure was observed and mechanical test, electrical test of Kelvin and daisy-chain structure were performed to evaluate bonding quality, also reliability test which included HTST and TCT had been carried out. The results confirmed that embedded bump hybrid bonding would be a convincing technology for future 3D integration.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00063
M. D. Rotaru, Li Kangrong
Wide and slow bus interfaces such as High Bandwidth Memory (HBM) and Advanced Interface Bus (AIB) are the main drivers behind the development and implementation of technologies such as Embedded Multi-die Interconnect Bridge (EMIB) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies can create very dense interconnect structures using back end of line (BEOL) approaches used to interconnect chiplets and to form functional system in package applications. With recent improvements in fabrication and process technologies organic based high density redistribution layer approaches such HD-FOWLP have become popular alternatives to EMIB and CoWoS. Redistribution layers with $2text{um}times 2text{um}$ cross section and 2um space between adjacent lines or $1text{um}times 1text{um}$ cross section with a minimum spacing of 1um have become achievable with the current fabrication technology. In this work the electrical design challenges in organic based fine RDL packages have been studied via simulation and electrical measurements.
{"title":"Electrical design challenges in High Bandwidth Memory and Advanced Interface Bus interfaces on HD-FOWLP technology","authors":"M. D. Rotaru, Li Kangrong","doi":"10.1109/ECTC32696.2021.00063","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00063","url":null,"abstract":"Wide and slow bus interfaces such as High Bandwidth Memory (HBM) and Advanced Interface Bus (AIB) are the main drivers behind the development and implementation of technologies such as Embedded Multi-die Interconnect Bridge (EMIB) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies can create very dense interconnect structures using back end of line (BEOL) approaches used to interconnect chiplets and to form functional system in package applications. With recent improvements in fabrication and process technologies organic based high density redistribution layer approaches such HD-FOWLP have become popular alternatives to EMIB and CoWoS. Redistribution layers with $2text{um}times 2text{um}$ cross section and 2um space between adjacent lines or $1text{um}times 1text{um}$ cross section with a minimum spacing of 1um have become achievable with the current fabrication technology. In this work the electrical design challenges in organic based fine RDL packages have been studied via simulation and electrical measurements.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128823741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00161
Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala
The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5 mu mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 mu mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2 mu mathrm{m}$.
随着对高带宽互连需求的不断增长，对高io密度封装再分配层(RDL)的需求也随之增加。这就需要缩小RDL的关键尺寸以及微通孔。将微通孔缩小到5 mu math {m}$直径以下存在许多挑战。主要的挑战是聚合物电介质中过孔的热机械可靠性。各种聚合物电介质的可靠性建模和设计是实现机械可靠性的关键。本文提出了一种微通孔失效预测模型。讨论了孔口几何形状(孔口角度和高度)以及材料性能(cte和弹性模量)对孔口破坏的影响。并将建模结果与实验结果进行了对比，验证了模型的准确性。利用该模型，确定了传统的通孔几何形状在通孔直径$2 mu mathm {m}$处达到工程极限。在这个尺寸以下，很难在聚合物中实现可靠的过孔，因为它们不能经受1000次热循环。在建模研究的基础上，提出了一种提高过孔可靠性的新方法，该方法低于工程极限$2 mu mathm {m}$。
{"title":"Reliability Modeling of Micro-vias in High-Density Redistribution Layers","authors":"Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala","doi":"10.1109/ECTC32696.2021.00161","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00161","url":null,"abstract":"The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5 mu mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 mu mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2 mu mathrm{m}$.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125475521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00075
K. Sakuma, Dishit P. Parekh, M. Belyansky, Juan-Manuel Gomez, S. Skordas, D. Mcherron, I. de Sousa, Marc-Antoine K. Phaneuf, Martin M Desrochers, Ming Li, Y. Cheung, Siu Cheung So, S. Kwok, Chun Ho Fan, Siu Wing Lau
In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1 mumathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed < 0.38 nm RMS and < 0.30 nm $mathrm{R}_{mathrm{a}}$. Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2 mumathrm{m}$, which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760 mumathrm{m}$. Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.
{"title":"Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous Integration","authors":"K. Sakuma, Dishit P. Parekh, M. Belyansky, Juan-Manuel Gomez, S. Skordas, D. Mcherron, I. de Sousa, Marc-Antoine K. Phaneuf, Martin M Desrochers, Ming Li, Y. Cheung, Siu Cheung So, S. Kwok, Chun Ho Fan, Siu Wing Lau","doi":"10.1109/ECTC32696.2021.00075","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00075","url":null,"abstract":"In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1 mumathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed < 0.38 nm RMS and < 0.30 nm $mathrm{R}_{mathrm{a}}$. Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2 mumathrm{m}$, which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760 mumathrm{m}$. Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00030
Chen-Chao Wang, Chih-Yi Huang, K. Chang, Youle Lin
In recent years, because the needs of 5G mobile communications, artificial intelligence, self-driving cars, and high-speed networks product are highly increasing, more and more IC design companies have invested in a lots of computing and high-performance computing device development. At present, the package type used in such high-performance computing product mass production is 2.5D IC package with ultra-high density I/O, which is special for packaging of IC products such as AI, high performance GPU, and high-speed networking devices. Compared to the traditional Flip Chip BGA (FCBGA) package on the market, the 2.5D package has a unique silicon interposer, and there are ASIC chip and HBM chips on the silicon interposer. Between the ASIC chip and the HBM chips, a lot of high-speed signal lines and thousands of small vias are connected. In addition to the signal line between the ASIC chip and the HBM chip, the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Because of the existing of TSV, the production yield of the silicon interposer is not easy to increase. Considering productivity and cost, some OSAT (Outsourced Semiconductor Assembly and Test) companies hence [1]–[5] proposed some TSV-free packaging structures, such as FOCoS (Fan-out Chip on Substrate). According to different process, there are Chip First FOCoS and Chip last FOCoS, which are suitable for different applications and production costs [6]. The research and discussion in this paper, there are package design with the structure of FOCoS for an actual high-performance computing IC device with two ASIC chips. In the process of this actual project, the SiP-id (System-in-Package Intelligent Design) design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL. Compared with the traditional design platform, it was greatly pull-in design cycle time. The design time and the accuracy of the design are improved obviously. In addition, this paper also delivers a lot of self-developed programs to link the design and validation tools from different vendors.
近年来，由于5G移动通信、人工智能、自动驾驶汽车、高速网络产品的需求高度增长，越来越多的IC设计公司投入了大量的计算和高性能计算设备的开发。目前，用于此类高性能计算产品量产的封装类型为超高密度I/O的2.5D IC封装，专门用于AI、高性能GPU、高速网络设备等IC产品的封装。与市场上传统的倒装BGA (FCBGA)封装相比，2.5D封装具有独特的硅中间层，并且在硅中间层上有ASIC芯片和HBM芯片。在ASIC芯片和HBM芯片之间，连接着许多高速信号线和成千上万的小过孔。除了ASIC芯片和HBM芯片之间的信号线外，硅中间层还有一个重要的结构——tsv (Through silicon Via)，作为ASIC芯片或HBM芯片与封装基板之间的连接。由于TSV的存在，硅中间层的成品率不易提高。考虑到生产力和成本，一些OSAT(外包半导体组装和测试)公司因此[1]-[5]提出了一些无tsv的封装结构，如FOCoS(基板上的扇形芯片)。根据不同的工艺，有芯片优先foco和芯片后foco，适用于不同的应用和生产成本。在本文的研究和讨论中，针对一个实际的高性能计算集成电路器件，采用foco结构进行了封装设计。在实际项目过程中，采用SiP-id (System-in-Package Intelligent Design)设计平台完成Si interposer MEOL (Middle End of Line)、Fan-Out RDL等超高密度I/O的布线。与传统的设计平台相比，大大缩短了设计周期。设计时间和设计精度明显提高。此外，本文还提供了许多自行开发的程序来连接来自不同供应商的设计和验证工具。
{"title":"A New Semiconductor Package Design Flow and Platform Applied on High Density Fan-out Chip","authors":"Chen-Chao Wang, Chih-Yi Huang, K. Chang, Youle Lin","doi":"10.1109/ECTC32696.2021.00030","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00030","url":null,"abstract":"In recent years, because the needs of 5G mobile communications, artificial intelligence, self-driving cars, and high-speed networks product are highly increasing, more and more IC design companies have invested in a lots of computing and high-performance computing device development. At present, the package type used in such high-performance computing product mass production is 2.5D IC package with ultra-high density I/O, which is special for packaging of IC products such as AI, high performance GPU, and high-speed networking devices. Compared to the traditional Flip Chip BGA (FCBGA) package on the market, the 2.5D package has a unique silicon interposer, and there are ASIC chip and HBM chips on the silicon interposer. Between the ASIC chip and the HBM chips, a lot of high-speed signal lines and thousands of small vias are connected. In addition to the signal line between the ASIC chip and the HBM chip, the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Because of the existing of TSV, the production yield of the silicon interposer is not easy to increase. Considering productivity and cost, some OSAT (Outsourced Semiconductor Assembly and Test) companies hence [1]–[5] proposed some TSV-free packaging structures, such as FOCoS (Fan-out Chip on Substrate). According to different process, there are Chip First FOCoS and Chip last FOCoS, which are suitable for different applications and production costs [6]. The research and discussion in this paper, there are package design with the structure of FOCoS for an actual high-performance computing IC device with two ASIC chips. In the process of this actual project, the SiP-id (System-in-Package Intelligent Design) design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL. Compared with the traditional design platform, it was greatly pull-in design cycle time. The design time and the accuracy of the design are improved obviously. In addition, this paper also delivers a lot of self-developed programs to link the design and validation tools from different vendors.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00136
Alexandre La Grappe, Evert Visker, A. Redolfi, Lan Peng, Karthik Muga, David Huls, S. Vanhaelemeersch, A. Lauwers, J. Ackaert
Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enabling low cost of ownership has led to new process techniques. Wafer level lamination using dry film resist (DFR) has emerged as a favorable option for such applications. In this paper, a unique application of temporary DFR to overcome deep Si trenches will be presented. The integration scheme offers novel possibilities for wafer singulation in addition to resolving the issues with conventional spin-coating. An example of this approach will be presented in detail. This unique integration flow can lead to new applications that would otherwise not be feasible in technological areas such as sensor, microfluidics and MEMS.
{"title":"A novel integration scheme for wafer singulation and selective processing using temporary dry film resist","authors":"Alexandre La Grappe, Evert Visker, A. Redolfi, Lan Peng, Karthik Muga, David Huls, S. Vanhaelemeersch, A. Lauwers, J. Ackaert","doi":"10.1109/ECTC32696.2021.00136","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00136","url":null,"abstract":"Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enabling low cost of ownership has led to new process techniques. Wafer level lamination using dry film resist (DFR) has emerged as a favorable option for such applications. In this paper, a unique application of temporary DFR to overcome deep Si trenches will be presented. The integration scheme offers novel possibilities for wafer singulation in addition to resolving the issues with conventional spin-coating. An example of this approach will be presented in detail. This unique integration flow can lead to new applications that would otherwise not be feasible in technological areas such as sensor, microfluidics and MEMS.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126755117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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