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2021 IEEE 71st Electronic Components and Technology Conference (ECTC)最新文献

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Extreme High Aspect Ratio RDL Patterning with Low Temperature Curable Polyimide using Double Patterning Technology 低温固化聚酰亚胺双模技术的超高纵横比RDL模
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00254
Atsushi Nakamura, T. Koizumi, Naoki Sato, Toshihide Aoshima, Michihiro Ogawa, Daisuke Asakawa, Yuki Sakamoto, H. Noguchi
In this paper, extreme high aspect ratio RDL patterning technologies using double patterning technology and low temperature curable polyimide is demonstrated. The extreme high aspect ratio patterning is realized by combination of 1st and 2nd patterning before curing, and was used to successfully form both trench and via patterns, as well as combination of via and trench. The aspect ratio was measured by cross-sectional observation of the resulting pattern using an electron microscope, and was found to be over 8 after curing. Finally, a PI film was formed using the double patterning technology, and a single curing step was applied to obtain a permanent film, with reliability evaluation performed using biased HAST and HTS test. Furthermore, the elongation at break and modulus were measured through stress-strain curve. The results of biased HAST and HTS, as well as mechanical property measurements, are promising. The PI permanent film formed by double patterning and obtained by single curing is homogenized, passes the reliability evaluation, and can be applied to actual devices.
本文介绍了利用双模技术和低温固化聚酰亚胺的超高纵横比RDL模化技术。通过固化前的第一次和第二次图案组合实现了超高纵横比的图案,并成功地形成了沟槽和通孔图案,以及通孔和沟槽的组合。利用电子显微镜对所得到的图案进行横断面观察来测量纵横比,发现固化后纵横比大于8。最后,采用双模技术形成PI膜,采用单一固化步骤获得永久膜,并采用偏置HAST和HTS测试进行可靠性评估。通过应力-应变曲线测量了断裂伸长率和模量。偏置HAST和HTS的结果以及力学性能测量都是有希望的。经双图像化、单固化得到的PI永膜均质化,通过了可靠性评估,可应用于实际器件。
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引用次数: 0
Extraordinarily enhanced sintering performance of pressureless sinterable Cu nanoparticle paste for achieving robust die-attach bonding by using reducing hybrid solvent 采用还原性杂化溶剂,显著提高了无压烧结铜纳米颗粒浆料的烧结性能,实现了牢固的模附键合
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00104
Hai-Jun Huang, Min-bo Zhou, Xin-Ping Zhang
Hybrid solvents with reducing property, composed of diethylene glycol (DEG) and glycerol (G), are developed for use as carrier solvent of the Cu nanoparticle paste, which has been employed successfully to achieve die-attach bonding through a pressureless low-temperature sintering process, with sintered joints having shear strength of 72 MPa, the highest reported thus far. The amount of residual solvent in high temperature range (150–250 °C) determined by boiling point of carrier solvents is directly related to the ratio of unbonded areas in the sintered Cu paste matrix. Solvents with the reducing property, which is crucial to decomposition of Cu lactate during sintering process, are indispensable for forming highly dense Cu bulks as the reinforcing phase in the sintered matrix. Finite element simulations of the influence of unbonded areas (defects) in the sintered Cu paste matrix on thermal cycling performance of the joints show that equivalent total strain increases with unbonded area, but shear stress behaves in the opposite way. For sintered joints using DEG+G formulated Cu paste, the dwell time of high temperature storage (HTS) at 250°C has limited effect on joints' strength. The Cu NP paste stored in the fridge at −5°C and −40°C for 6 months still retains the capability of pressureless low-temperature sintering, which meets the requirement of the industry application, concerning with transportation, storage and handling of Cu paste.
采用二甘醇(DEG)和甘油(G)组成的具有还原性的杂化溶剂作为铜纳米颗粒浆料的载体溶剂,通过无压低温烧结工艺成功实现了模贴结合,烧结后的接头抗剪强度达到72 MPa,为目前报道的最高。由载体溶剂沸点测定的高温范围(150 ~ 250℃)内残余溶剂的量与烧结Cu膏体基体中未键合区比例直接相关。具有还原性的溶剂是烧结过程中乳酸铜分解的关键,在烧结基体中形成高密度的Cu体作为增强相是必不可少的。对烧结铜膏体基体中非粘结区(缺陷)对接头热循环性能影响的有限元模拟表明,等效总应变随非粘结区增大而增大,而剪切应力则相反。对于采用DEG+G配方Cu膏体烧结的接头,250℃高温保存时间对接头强度的影响有限。在- 5°C和- 40°C的冰箱中存放6个月的铜NP膏体,仍然保持了无压低温烧结的能力,满足了铜膏体运输、储存和处理的工业应用要求。
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引用次数: 1
Study of the adhesion of a sintered Ag joint on a Cu substrate using laser shocks. Influence of aging 激光冲击烧结银接头在铜基体上的粘附性研究。老化的影响
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00106
X. Milhet, T. de Rességuier, L. Signor, Etienne Barraud, Kokouvi Happy N'Tsouaglo, Hadi Bahsoum, J. Baillargeat
Silver pastes sintering is a potential candidate for die bonding in power electronic modules which are built by stacking up layers of various materials having different coefficients of thermal expansion. Consequently, in operating conditions, thermal stresses (tensile or compressive) develop at the interfaces between the layers. Moreover, during aging, the initial interface is expected to evolve, mostly due to diffusion of atomic species between adjacent layers. In this study, original laser-shock experiments, involving tensile stresses near the interface, are performed to investigate the influence of aging on the adhesive strength of sintered silver joints onto copper.
银糊烧结是一种潜在的候选材料,用于电力电子模块的模具键合,该模块是由具有不同热膨胀系数的各种材料层堆叠而成的。因此,在操作条件下,热应力(拉伸或压缩)在层之间的界面上产生。此外,在时效过程中,初始界面预计会发生演化,这主要是由于相邻层之间原子物质的扩散。在本研究中,采用原始激光冲击实验,包括界面附近的拉应力,研究时效对烧结银接头与铜的结合强度的影响。
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引用次数: 0
Co-Design of Chip-Package-Antenna in Fan-out Package for Practical 77 GHz Automotive Radar 实用77 GHz汽车雷达扇出封装芯片天线协同设计
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00191
Chuanming Zhu, Yinglu Wan, Zongming Duan, Yuefei Dai
This paper presents a co-design of chip-package-antenna in fan-out package for automotive radar. Many packaged chips are directly soldered onto the feeding network of planar antenna array. However, the interconnections and associated radiation interferences are seldom considered. Thus co-design of chip-package-antenna is necessary since the radiation pattern is seriously affected by the packaged chip and feeding network, especially at millimetre-wave frequency. In this work, the used antenna is a planar 12-element series-fed linear antenna array. Based on Dolph-Chebyshev magnitude distribution, the desired radiation pattern is firstly synthesized by tapering each patch width. Then the transition of chip-package-board is proposed and realized by properly designing redistribution layer (RDL) in fan-out package and the GCPW line on PCB. After chip is flip-chipped onto antenna, the side lobe level (SLL) of the whole chip-package-antenna gets worse. By redesigning the width and distances of between elements, the SLL can be improved. The results show that the proposed method of chip-package-antenna paves the way to practical automotive radar application.
提出了一种车用雷达扇出封装中芯片封装天线的协同设计方法。许多封装芯片是直接焊接在平面天线阵馈电网络上的。然而,互连和相关的辐射干扰很少被考虑。由于封装芯片和馈电网络对天线的辐射方向图影响很大,尤其是毫米波频段的辐射方向图,因此采用芯片-封装天线协同设计是必要的。在这项工作中,使用的天线是平面12元串联馈电线性天线阵列。基于道尔夫-切比雪夫星等分布,首先将每个贴片宽度变细,合成所需的辐射方向图。然后通过合理设计扇出封装中的再分配层(RDL)和PCB上的GCPW线,提出并实现了芯片封装板的过渡。芯片倒装到天线上后,整个芯片封装天线的旁瓣电平(SLL)变差。通过重新设计元素之间的宽度和距离,可以改善SLL。结果表明,所提出的芯片封装天线方法为汽车雷达的实际应用铺平了道路。
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引用次数: 0
Two-step fabrication process for die-to-die and die-to-wafer Cu-Cu bonds 两步制程的模对模和模对晶片的Cu-Cu键
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00043
J. Ong, K. Shie, K. Tu, Chih Chen
The scale of joints shrinks continuously due to super small and extremely fast computing devices consent to Moore's Law. Copper-to-copper direct bonding appears to be one of a solution to the limitation of scaling down into sub-micron scale. Moreover, bonding quality such as mechanical strength and electrical properties in copper bonding becoming an important topic. In this study, we examine the relationship of the bonding time and temperature on the bonding strength and bump resistance in Cu-Cu bonds with highly <111> oriented nanotwinned copper. In addition, the Cu-Cu joints were subjected to a post annealing process at the bonding strength after the second step annealing at 300 °C under 47MPa for 1 hour in vacuum ambient. The bonding strength increases 3–4 folds after the post annealing. Some of the open Cu-Cu joints became connected after the post-annealing process.
由于超小、超快的计算设备符合摩尔定律,关节的规模不断缩小。铜-铜直接键合似乎是解决缩小到亚微米尺度限制的一种解决方案。此外,铜键合中的机械强度和电性能等键合质量也成为一个重要的课题。在这项研究中,我们研究了键合时间和温度对高取向纳米孪晶铜的Cu-Cu键的键合强度和抗碰撞性能的关系。另外,在真空环境下,在300℃、47MPa条件下进行第二步退火1小时后,对Cu-Cu接头进行结合强度的后退火处理。退火后的结合强度提高了3-4倍。部分开口的Cu-Cu接头在退火后重新连接。
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引用次数: 3
The Study of Packaging Substrate Effect in FCBGA by Laser Assisted Bonding 激光辅助键合FCBGA封装衬底效应研究
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00110
Yu Lung Huang, Joe Huang, C. M. Huang, K. Yu, Tank Luo, W. Hong, Taishin Ren
In order to support the high growth of Artificial Intelligence, Internet of Things, Industrial IOT, Cloud Service and 5G, the IC (Server/Router/Switch) needs higher/faster performance to collect, store, commute and transmit a mass of data. Therefore, the I/O (input/output) density of IC will increase with the silicon nodes < 5 nm, fine pitch $mutext{bump}$, and fine line width/space substrate. However, the solder reflow of IC faces two problems of the chip damages (silicon nodes: current leakage, highly electromigration; ELK (extremely low-k): current leakage, crack) and solder high stress (solder: wicking, IMC (intermetallic compound)) due to highly thermal budget of MR (mass reflow). In this paper, LAB (laser assisted bonding) will replace MR (mass reflow) to solve these problems. In this study, a test vehicle with the size of $55^{ast}55 text{mm}2$ FCBGA (flip chip ball grid array) was built. Two types (A and B) of substrate were applied to the FCBGA, with the differences between the solder mask (thickness, surface brightness/roughness) and substrate mass. LAB uses a semiconductor laser with wavelength of 980 nm, and the area of laser beam is 91.5% of the substrate area. The study is divided into three parts. For the first part, the surface temperature of die without substrate is higher than that of die with substrate at the same parameters about 187.2 °C. The result shows that the substrate has the function of heat storage. In addition, for the surface temperature of die with substrate, the result shows that all solders melt at 2.82 sec, and the surface temperature of the center of die is 22.8 °C lower than the four corners of it. Then the delta temperature between the surface temperature of the center of die and bump is 48.3 °C. The result shows that the overall temperature of die with substrate is not uniform. Next, for substrate effect, the surface temperature of die and B substrate is lower than that of die and A substrate based on the following reasons: for the solder mask, (a) the surface brightness of B substrate is 11% higher than that of A substrate result in an increase of the reflected light; (b) the roughness of B substrate is 26% lower than that of A substrate result in an increase of the reflected light; (c) the thickness of B substrate is 23% lower than that of A Substrate result in a reduction of Absorbed light; for substrate mass (d) the weight of B substrate is 10% higher than that of A substrate. Finally, the assembled FCBGA packages by LAB passed reliability tests: MSL4 pre-conditioning with uHAST 168 hours, TCT B 1000 thermal cycles and HTST 1000 hours. Details of the results are presented and discussed in the paper. In summary, we have developed the parameter set to solve it in different substrates and predicted the melting time of solder and temperature profile of die surface. Therefore, LAB (laser assisted bonding) can successfully solve the problems MR encounters. The full descriptions of the development results will
为了支持人工智能、物联网、工业物联网、云服务和5G的高速增长,IC(服务器/路由器/交换机)需要更高/更快的性能来收集、存储、交换和传输大量数据。因此,集成电路的I/O(输入/输出)密度将随着硅节点< 5 nm、细间距$mutext{bump}$和细线宽/空间衬底而增加。然而,集成电路的焊料回流面临芯片损伤(硅节点)的两个问题:漏电流、高电迁移;ELK(极低k):漏电流,裂纹)和焊料高应力(焊料:吸丝,IMC(金属间化合物))由于MR(质量回流)的高热预算。在本文中,激光辅助键合(LAB)将取代质量回流(MR)来解决这些问题。本研究构建了尺寸为$55^{ast}55 text{mm}2$ FCBGA(倒装芯片球栅阵列)的实验车。将两种类型的衬底(A和B)应用于FCBGA,其阻焊层(厚度、表面亮度/粗糙度)和衬底质量之间存在差异。LAB采用波长为980 nm的半导体激光器,激光束面积为衬底面积的91.5%。本研究分为三个部分。对于第一部分,在相同参数下,无衬底的模具表面温度高于有衬底的模具表面温度,约为187.2℃。结果表明,该衬底具有储热功能。此外,对于有衬底的模具表面温度,结果表明,所有焊料在2.82秒熔化,模具中心表面温度比模具四角低22.8℃。模具中心表面温度与凸块表面温度的差值为48.3℃。结果表明,模具与衬底的整体温度不均匀。其次,对于衬底效应,由于以下原因,模具和B衬底的表面温度低于模具和A衬底的表面温度:对于阻焊片,(A) B衬底的表面亮度比A衬底高11%,导致反射光增加;(b) b基板的粗糙度比A基板的粗糙度低26%,导致反射光增加;(c) B衬底的厚度比A衬底的厚度低23%,导致吸收光减少;对于衬底质量(d), B衬底的重量比A衬底的重量高10%。最后,通过LAB组装的FCBGA封装通过了可靠性测试:MSL4预处理uHAST 168小时,TCT B 1000热循环,HTST 1000小时。文中详细介绍了实验结果并进行了讨论。综上所述,我们开发了在不同衬底下求解该问题的参数集,并预测了焊料的熔化时间和模具表面的温度分布。因此,LAB(激光辅助键合)可以成功地解决MR遇到的问题。本研究将讨论开发结果的完整描述。
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引用次数: 1
FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin Display 基于fowlp的柔性混合电子与3D-IC芯片用于智能皮肤显示
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00017
Y. Susumago, T. Odashima, M. Ichikawa, Hiroki Hanaoka, H. Kino, Tetsu Tanaka, T. Fukushima
This paper deals with a flexible 3D-IC system fabrication methodology. Mini-LEDs and 3D-IC chiplets divided from a large 3D-IC with Cu-TSVs are embedded in an elastomer PDMS based on die-first FOWLP for heterogeneously integrating them into Smart Skin Display as a biomedical/wearable FHE (flexible hybrid electronics). We address a serious die-shift issue for the tiny chips in die-first FOWLP by using a new anchoring layer technique to drastically reduce the shift within $2.7 mumathrm{m}$ including assembly positioning errors. The mechanical/electrical properties of the flexible array of 3D-IC chiplets are characterized before and after repeated bending with a curvature radius of 10 mm. In addition, stress neutral axes are designed to stably endure bending cycle applicable to the biomedical/wearable FHE with multi-level metallization.
本文讨论了一种灵活的3D-IC系统制造方法。mini - led和3D-IC芯片从带有cu - tsv的大型3D-IC中分离出来,嵌入基于模首FOWLP的弹性体PDMS中,用于将它们作为生物医学/可穿戴FHE(柔性混合电子产品)异构集成到智能皮肤显示中。我们通过使用一种新的锚定层技术,解决了模具优先级FOWLP中微小芯片的严重模移问题,将模移大幅度减少在$2.7 mu mathm {m}$内,包括装配定位误差。在曲率半径为10 mm的情况下,对3D-IC芯片柔性阵列的力学/电学性能进行了表征。此外,应力中性轴的设计可以稳定地承受弯曲循环,适用于多层次金属化的生物医学/可穿戴FHE。
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引用次数: 4
High-frequency electrical circuit model for integrated capacitors utilizing lossy nanostructures 利用损耗纳米结构集成电容器的高频电路模型
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00197
S. Krause, R. Andersson, M. Bylund, V. Marknäs, A. Saleem, Elisa Passalaqua, Shafiq Kabir, V. Desmaris
A physics-based model is presented that captures the electrical high-frequency behavior of low-dimensional nanostructures used in emerging technologies such as the ultra-high-density capacitor. Derived from transmission line theory the analytical expression provides a frequency-dependent admittance of a lossy nanostructure, which can be numerically integrated over arbitrary areas comprising the nanostructure. Edge effects, a distributed nature of resistivity or dimensions of the nanostructure comprising the device can be taken into consideration and make it a powerful tool for designing future integrated circuits. The model predictions show an excellent match with hardware measurements up to 3 GHz on state-of-the-art carbon nanofiber based MIM-capacitors with capacitance densities up to 500 nF/mm2 at $mathrm{6} mu mathrm{m}$ device height.
提出了一种基于物理的模型,用于捕获用于新兴技术(如超高密度电容器)的低维纳米结构的电高频行为。由传输线理论导出的解析表达式提供了损耗纳米结构的频率相关导纳,可以在包含纳米结构的任意区域上进行数值积分。可以考虑边缘效应、电阻率的分布性质或组成器件的纳米结构的尺寸,使其成为设计未来集成电路的有力工具。模型预测显示,在最先进的基于碳纳米纤维的mim电容器上,在$ mathm {6} mu mathm {m}$器件高度上,电容密度高达500 nF/mm2,硬件测量高达3 GHz,与模型预测非常匹配。
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引用次数: 0
Impact of warpage on signal delivery with large size FC-PBGA package 翘曲对大尺寸FC-PBGA封装信号传输的影响
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00274
Heeseok Lee, Jisoo Hwang, Henry H. Kwon, Junso Pak
The impact of non-zero warpage on signal delivery characteristics is presented by analyzing transmission line on curved plane defined in cylindrical coordinate system. Authors will present a compact finite-difference frequency-domain method for quasi-TEM mode (C-FDFD-QT) with cylindrical coordinate system, which is a promising method to determine the characteristic impedance with efficiently reduced size of computational matrix by using quasi-TEM approximation. In summary, the non-zero warpage of large-size substrate constructing large size FC-BGA results in the increase of characteristic impedance, which has been quantitatively studied by using C-FDTD-QT. The characteristic impedance of stripline on curved plane is larger than that of stripline on the plane whose warpage is zero.
通过分析以柱坐标系定义的曲面上的传输线,给出了非零翘曲对信号传输特性的影响。本文提出了一种圆柱坐标系下准瞬变电磁法(C-FDFD-QT)的紧凑有限差分频域方法,该方法利用准瞬变电磁法近似有效地减小了计算矩阵的尺寸,是一种很有前途的确定特征阻抗的方法。综上所述,构建大尺寸FC-BGA的大尺寸衬底的非零翘曲会导致特性阻抗的增加,这已经通过C-FDTD-QT进行了定量研究。曲线平面上带状线的特性阻抗大于翘曲为零平面上带状线的特性阻抗。
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引用次数: 0
Thermal and electrical reliability analysis of TO-247 for bonding method, substrate structure and heat dissipation bonding material TO-247的粘接方法、衬底结构和散热粘接材料的热电可靠性分析
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00308
Dong-hwan Kim, Aesun Oh, Eunyoung Park, Kyung-Hyun Kim, Sung-Jae Jeon, Hyun-Cheol Bae
In this study, a 1700V/58A SiC MOSFET was used as the TO-247 module instead of the existing Si TO-247 module to analyze the thermal and electrical characteristics of a high-power module. The TO-247 module was manufactured to measure the electrical characteristics under thermal cycle testing (−40 to 125°C). The substrates used in the fabrication were standard TO-247 substrates, AlN DBC with high thermal conductivity, and Si3N4 AMB with high mechanical properties. The PbSn preform of the conventional solder base and a highly reliable Ag sintering paste were used as the bonding materials. For interconnection, wire bonding, which is most used in modules, and Cu clips attached using heterogeneous bonding materials were used in the TO-247 module. A total of 100 cycles were carried out, and Trr and RDS(on) were measured every 50 cycles to assess the electrical characteristics. The thermal analysis of the maximum temperature difference between the substrates, bonding materials, and interconnections was performed by adding a Cu clip bonding. The electrical properties were measured during the thermal cycling. all samples performed better than the 1700V/58A SiC MOSFET datasheet and operated normally after 100 cycles. Additionally, the maximum temperature difference between the Al wire and Cu clip bonding was not significant in the standard TO-247 module. However, using Cu clip bonding is more effective in reducing temperature when high heat is generated using substrates with low thermal conductivity.
本研究采用1700V/58A SiC MOSFET代替现有的Si to -247模块作为to -247模块,分析大功率模块的热电特性。to -247模块用于测量热循环测试(- 40至125°C)下的电气特性。采用标准的TO-247衬底、高导热系数的AlN DBC和高机械性能的Si3N4 AMB作为衬底。采用传统焊料基的PbSn预制体和高可靠的银烧结浆料作为粘结材料。为了实现互连,TO-247模块采用了模块中最常用的线键合和异质键合材料连接的Cu夹。共进行100次循环,每50次循环测量Trr和RDS(on),以评估电特性。通过添加铜夹键合,对衬底、键合材料和互连之间的最大温差进行了热分析。在热循环过程中测量了电学性能。所有样品的性能都优于1700V/58A SiC MOSFET数据表,并且在100次循环后正常工作。此外,在标准的TO-247模块中,Al线和Cu夹接之间的最大温差并不显著。然而,当使用导热系数低的衬底产生高热量时,使用铜夹键合更有效地降低温度。
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引用次数: 3
期刊
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
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