Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00254
Atsushi Nakamura, T. Koizumi, Naoki Sato, Toshihide Aoshima, Michihiro Ogawa, Daisuke Asakawa, Yuki Sakamoto, H. Noguchi
In this paper, extreme high aspect ratio RDL patterning technologies using double patterning technology and low temperature curable polyimide is demonstrated. The extreme high aspect ratio patterning is realized by combination of 1st and 2nd patterning before curing, and was used to successfully form both trench and via patterns, as well as combination of via and trench. The aspect ratio was measured by cross-sectional observation of the resulting pattern using an electron microscope, and was found to be over 8 after curing. Finally, a PI film was formed using the double patterning technology, and a single curing step was applied to obtain a permanent film, with reliability evaluation performed using biased HAST and HTS test. Furthermore, the elongation at break and modulus were measured through stress-strain curve. The results of biased HAST and HTS, as well as mechanical property measurements, are promising. The PI permanent film formed by double patterning and obtained by single curing is homogenized, passes the reliability evaluation, and can be applied to actual devices.
{"title":"Extreme High Aspect Ratio RDL Patterning with Low Temperature Curable Polyimide using Double Patterning Technology","authors":"Atsushi Nakamura, T. Koizumi, Naoki Sato, Toshihide Aoshima, Michihiro Ogawa, Daisuke Asakawa, Yuki Sakamoto, H. Noguchi","doi":"10.1109/ECTC32696.2021.00254","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00254","url":null,"abstract":"In this paper, extreme high aspect ratio RDL patterning technologies using double patterning technology and low temperature curable polyimide is demonstrated. The extreme high aspect ratio patterning is realized by combination of 1st and 2nd patterning before curing, and was used to successfully form both trench and via patterns, as well as combination of via and trench. The aspect ratio was measured by cross-sectional observation of the resulting pattern using an electron microscope, and was found to be over 8 after curing. Finally, a PI film was formed using the double patterning technology, and a single curing step was applied to obtain a permanent film, with reliability evaluation performed using biased HAST and HTS test. Furthermore, the elongation at break and modulus were measured through stress-strain curve. The results of biased HAST and HTS, as well as mechanical property measurements, are promising. The PI permanent film formed by double patterning and obtained by single curing is homogenized, passes the reliability evaluation, and can be applied to actual devices.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116335522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00104
Hai-Jun Huang, Min-bo Zhou, Xin-Ping Zhang
Hybrid solvents with reducing property, composed of diethylene glycol (DEG) and glycerol (G), are developed for use as carrier solvent of the Cu nanoparticle paste, which has been employed successfully to achieve die-attach bonding through a pressureless low-temperature sintering process, with sintered joints having shear strength of 72 MPa, the highest reported thus far. The amount of residual solvent in high temperature range (150–250 °C) determined by boiling point of carrier solvents is directly related to the ratio of unbonded areas in the sintered Cu paste matrix. Solvents with the reducing property, which is crucial to decomposition of Cu lactate during sintering process, are indispensable for forming highly dense Cu bulks as the reinforcing phase in the sintered matrix. Finite element simulations of the influence of unbonded areas (defects) in the sintered Cu paste matrix on thermal cycling performance of the joints show that equivalent total strain increases with unbonded area, but shear stress behaves in the opposite way. For sintered joints using DEG+G formulated Cu paste, the dwell time of high temperature storage (HTS) at 250°C has limited effect on joints' strength. The Cu NP paste stored in the fridge at −5°C and −40°C for 6 months still retains the capability of pressureless low-temperature sintering, which meets the requirement of the industry application, concerning with transportation, storage and handling of Cu paste.
{"title":"Extraordinarily enhanced sintering performance of pressureless sinterable Cu nanoparticle paste for achieving robust die-attach bonding by using reducing hybrid solvent","authors":"Hai-Jun Huang, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ECTC32696.2021.00104","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00104","url":null,"abstract":"Hybrid solvents with reducing property, composed of diethylene glycol (DEG) and glycerol (G), are developed for use as carrier solvent of the Cu nanoparticle paste, which has been employed successfully to achieve die-attach bonding through a pressureless low-temperature sintering process, with sintered joints having shear strength of 72 MPa, the highest reported thus far. The amount of residual solvent in high temperature range (150–250 °C) determined by boiling point of carrier solvents is directly related to the ratio of unbonded areas in the sintered Cu paste matrix. Solvents with the reducing property, which is crucial to decomposition of Cu lactate during sintering process, are indispensable for forming highly dense Cu bulks as the reinforcing phase in the sintered matrix. Finite element simulations of the influence of unbonded areas (defects) in the sintered Cu paste matrix on thermal cycling performance of the joints show that equivalent total strain increases with unbonded area, but shear stress behaves in the opposite way. For sintered joints using DEG+G formulated Cu paste, the dwell time of high temperature storage (HTS) at 250°C has limited effect on joints' strength. The Cu NP paste stored in the fridge at −5°C and −40°C for 6 months still retains the capability of pressureless low-temperature sintering, which meets the requirement of the industry application, concerning with transportation, storage and handling of Cu paste.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00106
X. Milhet, T. de Rességuier, L. Signor, Etienne Barraud, Kokouvi Happy N'Tsouaglo, Hadi Bahsoum, J. Baillargeat
Silver pastes sintering is a potential candidate for die bonding in power electronic modules which are built by stacking up layers of various materials having different coefficients of thermal expansion. Consequently, in operating conditions, thermal stresses (tensile or compressive) develop at the interfaces between the layers. Moreover, during aging, the initial interface is expected to evolve, mostly due to diffusion of atomic species between adjacent layers. In this study, original laser-shock experiments, involving tensile stresses near the interface, are performed to investigate the influence of aging on the adhesive strength of sintered silver joints onto copper.
{"title":"Study of the adhesion of a sintered Ag joint on a Cu substrate using laser shocks. Influence of aging","authors":"X. Milhet, T. de Rességuier, L. Signor, Etienne Barraud, Kokouvi Happy N'Tsouaglo, Hadi Bahsoum, J. Baillargeat","doi":"10.1109/ECTC32696.2021.00106","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00106","url":null,"abstract":"Silver pastes sintering is a potential candidate for die bonding in power electronic modules which are built by stacking up layers of various materials having different coefficients of thermal expansion. Consequently, in operating conditions, thermal stresses (tensile or compressive) develop at the interfaces between the layers. Moreover, during aging, the initial interface is expected to evolve, mostly due to diffusion of atomic species between adjacent layers. In this study, original laser-shock experiments, involving tensile stresses near the interface, are performed to investigate the influence of aging on the adhesive strength of sintered silver joints onto copper.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00191
Chuanming Zhu, Yinglu Wan, Zongming Duan, Yuefei Dai
This paper presents a co-design of chip-package-antenna in fan-out package for automotive radar. Many packaged chips are directly soldered onto the feeding network of planar antenna array. However, the interconnections and associated radiation interferences are seldom considered. Thus co-design of chip-package-antenna is necessary since the radiation pattern is seriously affected by the packaged chip and feeding network, especially at millimetre-wave frequency. In this work, the used antenna is a planar 12-element series-fed linear antenna array. Based on Dolph-Chebyshev magnitude distribution, the desired radiation pattern is firstly synthesized by tapering each patch width. Then the transition of chip-package-board is proposed and realized by properly designing redistribution layer (RDL) in fan-out package and the GCPW line on PCB. After chip is flip-chipped onto antenna, the side lobe level (SLL) of the whole chip-package-antenna gets worse. By redesigning the width and distances of between elements, the SLL can be improved. The results show that the proposed method of chip-package-antenna paves the way to practical automotive radar application.
{"title":"Co-Design of Chip-Package-Antenna in Fan-out Package for Practical 77 GHz Automotive Radar","authors":"Chuanming Zhu, Yinglu Wan, Zongming Duan, Yuefei Dai","doi":"10.1109/ECTC32696.2021.00191","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00191","url":null,"abstract":"This paper presents a co-design of chip-package-antenna in fan-out package for automotive radar. Many packaged chips are directly soldered onto the feeding network of planar antenna array. However, the interconnections and associated radiation interferences are seldom considered. Thus co-design of chip-package-antenna is necessary since the radiation pattern is seriously affected by the packaged chip and feeding network, especially at millimetre-wave frequency. In this work, the used antenna is a planar 12-element series-fed linear antenna array. Based on Dolph-Chebyshev magnitude distribution, the desired radiation pattern is firstly synthesized by tapering each patch width. Then the transition of chip-package-board is proposed and realized by properly designing redistribution layer (RDL) in fan-out package and the GCPW line on PCB. After chip is flip-chipped onto antenna, the side lobe level (SLL) of the whole chip-package-antenna gets worse. By redesigning the width and distances of between elements, the SLL can be improved. The results show that the proposed method of chip-package-antenna paves the way to practical automotive radar application.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"36 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00043
J. Ong, K. Shie, K. Tu, Chih Chen
The scale of joints shrinks continuously due to super small and extremely fast computing devices consent to Moore's Law. Copper-to-copper direct bonding appears to be one of a solution to the limitation of scaling down into sub-micron scale. Moreover, bonding quality such as mechanical strength and electrical properties in copper bonding becoming an important topic. In this study, we examine the relationship of the bonding time and temperature on the bonding strength and bump resistance in Cu-Cu bonds with highly <111> oriented nanotwinned copper. In addition, the Cu-Cu joints were subjected to a post annealing process at the bonding strength after the second step annealing at 300 °C under 47MPa for 1 hour in vacuum ambient. The bonding strength increases 3–4 folds after the post annealing. Some of the open Cu-Cu joints became connected after the post-annealing process.
{"title":"Two-step fabrication process for die-to-die and die-to-wafer Cu-Cu bonds","authors":"J. Ong, K. Shie, K. Tu, Chih Chen","doi":"10.1109/ECTC32696.2021.00043","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00043","url":null,"abstract":"The scale of joints shrinks continuously due to super small and extremely fast computing devices consent to Moore's Law. Copper-to-copper direct bonding appears to be one of a solution to the limitation of scaling down into sub-micron scale. Moreover, bonding quality such as mechanical strength and electrical properties in copper bonding becoming an important topic. In this study, we examine the relationship of the bonding time and temperature on the bonding strength and bump resistance in Cu-Cu bonds with highly <111> oriented nanotwinned copper. In addition, the Cu-Cu joints were subjected to a post annealing process at the bonding strength after the second step annealing at 300 °C under 47MPa for 1 hour in vacuum ambient. The bonding strength increases 3–4 folds after the post annealing. Some of the open Cu-Cu joints became connected after the post-annealing process.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00110
Yu Lung Huang, Joe Huang, C. M. Huang, K. Yu, Tank Luo, W. Hong, Taishin Ren
In order to support the high growth of Artificial Intelligence, Internet of Things, Industrial IOT, Cloud Service and 5G, the IC (Server/Router/Switch) needs higher/faster performance to collect, store, commute and transmit a mass of data. Therefore, the I/O (input/output) density of IC will increase with the silicon nodes < 5 nm, fine pitch $mutext{bump}$, and fine line width/space substrate. However, the solder reflow of IC faces two problems of the chip damages (silicon nodes: current leakage, highly electromigration; ELK (extremely low-k): current leakage, crack) and solder high stress (solder: wicking, IMC (intermetallic compound)) due to highly thermal budget of MR (mass reflow). In this paper, LAB (laser assisted bonding) will replace MR (mass reflow) to solve these problems. In this study, a test vehicle with the size of $55^{ast}55 text{mm}2$ FCBGA (flip chip ball grid array) was built. Two types (A and B) of substrate were applied to the FCBGA, with the differences between the solder mask (thickness, surface brightness/roughness) and substrate mass. LAB uses a semiconductor laser with wavelength of 980 nm, and the area of laser beam is 91.5% of the substrate area. The study is divided into three parts. For the first part, the surface temperature of die without substrate is higher than that of die with substrate at the same parameters about 187.2 °C. The result shows that the substrate has the function of heat storage. In addition, for the surface temperature of die with substrate, the result shows that all solders melt at 2.82 sec, and the surface temperature of the center of die is 22.8 °C lower than the four corners of it. Then the delta temperature between the surface temperature of the center of die and bump is 48.3 °C. The result shows that the overall temperature of die with substrate is not uniform. Next, for substrate effect, the surface temperature of die and B substrate is lower than that of die and A substrate based on the following reasons: for the solder mask, (a) the surface brightness of B substrate is 11% higher than that of A substrate result in an increase of the reflected light; (b) the roughness of B substrate is 26% lower than that of A substrate result in an increase of the reflected light; (c) the thickness of B substrate is 23% lower than that of A Substrate result in a reduction of Absorbed light; for substrate mass (d) the weight of B substrate is 10% higher than that of A substrate. Finally, the assembled FCBGA packages by LAB passed reliability tests: MSL4 pre-conditioning with uHAST 168 hours, TCT B 1000 thermal cycles and HTST 1000 hours. Details of the results are presented and discussed in the paper. In summary, we have developed the parameter set to solve it in different substrates and predicted the melting time of solder and temperature profile of die surface. Therefore, LAB (laser assisted bonding) can successfully solve the problems MR encounters. The full descriptions of the development results will
{"title":"The Study of Packaging Substrate Effect in FCBGA by Laser Assisted Bonding","authors":"Yu Lung Huang, Joe Huang, C. M. Huang, K. Yu, Tank Luo, W. Hong, Taishin Ren","doi":"10.1109/ECTC32696.2021.00110","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00110","url":null,"abstract":"In order to support the high growth of Artificial Intelligence, Internet of Things, Industrial IOT, Cloud Service and 5G, the IC (Server/Router/Switch) needs higher/faster performance to collect, store, commute and transmit a mass of data. Therefore, the I/O (input/output) density of IC will increase with the silicon nodes < 5 nm, fine pitch $mutext{bump}$, and fine line width/space substrate. However, the solder reflow of IC faces two problems of the chip damages (silicon nodes: current leakage, highly electromigration; ELK (extremely low-k): current leakage, crack) and solder high stress (solder: wicking, IMC (intermetallic compound)) due to highly thermal budget of MR (mass reflow). In this paper, LAB (laser assisted bonding) will replace MR (mass reflow) to solve these problems. In this study, a test vehicle with the size of $55^{ast}55 text{mm}2$ FCBGA (flip chip ball grid array) was built. Two types (A and B) of substrate were applied to the FCBGA, with the differences between the solder mask (thickness, surface brightness/roughness) and substrate mass. LAB uses a semiconductor laser with wavelength of 980 nm, and the area of laser beam is 91.5% of the substrate area. The study is divided into three parts. For the first part, the surface temperature of die without substrate is higher than that of die with substrate at the same parameters about 187.2 °C. The result shows that the substrate has the function of heat storage. In addition, for the surface temperature of die with substrate, the result shows that all solders melt at 2.82 sec, and the surface temperature of the center of die is 22.8 °C lower than the four corners of it. Then the delta temperature between the surface temperature of the center of die and bump is 48.3 °C. The result shows that the overall temperature of die with substrate is not uniform. Next, for substrate effect, the surface temperature of die and B substrate is lower than that of die and A substrate based on the following reasons: for the solder mask, (a) the surface brightness of B substrate is 11% higher than that of A substrate result in an increase of the reflected light; (b) the roughness of B substrate is 26% lower than that of A substrate result in an increase of the reflected light; (c) the thickness of B substrate is 23% lower than that of A Substrate result in a reduction of Absorbed light; for substrate mass (d) the weight of B substrate is 10% higher than that of A substrate. Finally, the assembled FCBGA packages by LAB passed reliability tests: MSL4 pre-conditioning with uHAST 168 hours, TCT B 1000 thermal cycles and HTST 1000 hours. Details of the results are presented and discussed in the paper. In summary, we have developed the parameter set to solve it in different substrates and predicted the melting time of solder and temperature profile of die surface. Therefore, LAB (laser assisted bonding) can successfully solve the problems MR encounters. The full descriptions of the development results will ","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128922603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00042
T. Thomas, P. Brooks, F. Michalik, W. Cho
Improving adhesion between copper and lamination resin is one of the biggest challenges in micro-electronic manufacturing, such as IC substrate. Bonding enhancement process by surface roughening is predominant use method, due to providing the highest possible mechanical interlocking. In this process typically $mathrm{1}-mathrm{2} mumathrm{m}$ of copper need to be removed for reliable adhesion of dielectrics to the copper surface. Follow rapid development of electronics industry, where fine $mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$ and good signal propagation at higher speed are required. The conventional approach to ensure good adhesion of the conductor to the dielectrics by increasing surface roughness to achieve adhesion is no longer applicable. This work demonstrates the development of a novel surface treatment method of copper which can meet all the challenges of IC substate manufacturing for high speed function. The developed surface treatment system adopted subsequent treatment of organic coating so called “adhesion promoter (AP)” on top of copper surface to provide the strongest possible bond strength via chemical adhesion. As a result, significant improvement of adhesion of conductor to dielectrics can be obtained at ultra-low copper surface roughness.
{"title":"Next generation of adhesion enhancement system for high speed substrate manufacturing","authors":"T. Thomas, P. Brooks, F. Michalik, W. Cho","doi":"10.1109/ECTC32696.2021.00042","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00042","url":null,"abstract":"Improving adhesion between copper and lamination resin is one of the biggest challenges in micro-electronic manufacturing, such as IC substrate. Bonding enhancement process by surface roughening is predominant use method, due to providing the highest possible mechanical interlocking. In this process typically $mathrm{1}-mathrm{2} mumathrm{m}$ of copper need to be removed for reliable adhesion of dielectrics to the copper surface. Follow rapid development of electronics industry, where fine $mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$ and good signal propagation at higher speed are required. The conventional approach to ensure good adhesion of the conductor to the dielectrics by increasing surface roughness to achieve adhesion is no longer applicable. This work demonstrates the development of a novel surface treatment method of copper which can meet all the challenges of IC substate manufacturing for high speed function. The developed surface treatment system adopted subsequent treatment of organic coating so called “adhesion promoter (AP)” on top of copper surface to provide the strongest possible bond strength via chemical adhesion. As a result, significant improvement of adhesion of conductor to dielectrics can be obtained at ultra-low copper surface roughness.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115422224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00211
Jung-Man Son, S. Moon, Seungki Nam, Wook Kim
In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.
{"title":"PI/SI consideration for enabling 3D IC design","authors":"Jung-Man Son, S. Moon, Seungki Nam, Wook Kim","doi":"10.1109/ECTC32696.2021.00211","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00211","url":null,"abstract":"In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115514507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00285
Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im
In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.
{"title":"Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance","authors":"Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im","doi":"10.1109/ECTC32696.2021.00285","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00285","url":null,"abstract":"In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00363
C. Selvanayagam, P. Duong, Brett Wilkerson, N. Raghavan
An inverse design framework incorporating a physics-based surrogate model and global optimization is proposed to assist in the design of low warpage ultra-thin packages by adjusting the metal densities over substrate subsections and layers. The surrogate model is derived from two finite element analysis (FEA) models. The first one describes the relationship between the metal density in the substrate layer to the coefficient of thermal expansion (CTE) while the second one describes the relationship between in-plane CTE variation of the substrate to the warpage profile. Results from these two FEA models are used to train separate artificial neural networks (ANN). When these ANNs are run sequentially, the surrogate model can accurately determine the warpage profile for any set of metal densities. Three global optimization algorithms, Particle Swarm Optimization (PSO), Genetic Algorithm (GA) and Cross Entropy (CE) were then evaluated using this surrogate model. Three case studies consisting of different warpage profiles (original and 20% reduced warpage) and constraints to the optimization search space (±20% or ±50% change to metal density) were then evaluated using these algorithms. For all three cases, the three algorithms converged to similar solutions, indicating that indeed the global minimum has been attained and determined. However, GA took a significantly longer time to converge than PSO and CE. Based on these results, PSO and CE are recommended to be suitable algorithms to carry out inverse design for this type of problem.
{"title":"Comparison of Global Optimization Algorithms for Inverse Design of Substrate Metal Density for Low Warpage Design in Ultra-Thin Packages","authors":"C. Selvanayagam, P. Duong, Brett Wilkerson, N. Raghavan","doi":"10.1109/ECTC32696.2021.00363","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00363","url":null,"abstract":"An inverse design framework incorporating a physics-based surrogate model and global optimization is proposed to assist in the design of low warpage ultra-thin packages by adjusting the metal densities over substrate subsections and layers. The surrogate model is derived from two finite element analysis (FEA) models. The first one describes the relationship between the metal density in the substrate layer to the coefficient of thermal expansion (CTE) while the second one describes the relationship between in-plane CTE variation of the substrate to the warpage profile. Results from these two FEA models are used to train separate artificial neural networks (ANN). When these ANNs are run sequentially, the surrogate model can accurately determine the warpage profile for any set of metal densities. Three global optimization algorithms, Particle Swarm Optimization (PSO), Genetic Algorithm (GA) and Cross Entropy (CE) were then evaluated using this surrogate model. Three case studies consisting of different warpage profiles (original and 20% reduced warpage) and constraints to the optimization search space (±20% or ±50% change to metal density) were then evaluated using these algorithms. For all three cases, the three algorithms converged to similar solutions, indicating that indeed the global minimum has been attained and determined. However, GA took a significantly longer time to converge than PSO and CE. Based on these results, PSO and CE are recommended to be suitable algorithms to carry out inverse design for this type of problem.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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