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2021 IEEE 71st Electronic Components and Technology Conference (ECTC)最新文献

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Low Cost Grounding Integration for Surface Ion Trap 表面离子阱的低成本接地集成
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00259
Hongyu Li, W. Seit, Hwang Gilho, P. Zhao, J. Tao, C. S. Tan
Si substrate provide the integration platform for surface ion trap device fabrication. Grounding metal for the surface ion trap is necessary because of high RF voltage ($> 100mathrm{V}$) applied and lower RF loss required within functionality. High resistivity Si substrate with floating metal grounding and low-grade Si substrate with connected grounding metal were integrated with surface ion trap. Ion trap resonance curves were observed at 47.1 MHz frequency for ion trap devices with different grounding metal. The curves have similar resonant power.
硅衬底为表面离子阱器件的制造提供了集成平台。由于施加的高射频电压($> 100 mathm {V}$)和功能内所需的低射频损耗,表面离子阱的接地金属是必要的。采用表面离子阱将高电阻率硅衬底与浮金属接地和低品位硅衬底与接接地金属相结合。在47.1 MHz频率下观察了不同接地金属离子阱器件的谐振曲线。曲线具有相似的谐振功率。
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引用次数: 0
Automated Void Detection in TSVs from 2D X-Ray Scans using Supervised Learning with 3D X-Ray Scans 自动空洞检测tsv从2D x射线扫描使用监督学习与3D x射线扫描
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00143
R. Pahwa, S. Gopalakrishnan, Huang Su, Ong Ee Ping, Haiwen Dai, D. Wee, Ren Qin, V. S. Rao
Yield improvement is a critical component of semiconductor manufacturing. It is done by collecting, analyzing, identifying the causes of defects, and then coming up with a practical solution to resolve the root causes. Semiconductor components such as Through Silicon Vias (TSVs) and other package interconnects are getting smaller and smaller with the ongoing miniaturization progress in the industry. Detecting defects in these buried interconnects is becoming both more difficult and more important. We collect both 2D and 3D X-Ray scans of defective TSVs containing defects such as voids. We label the data in 3D and perform registration between 2D and 3D scans. We use this registration information to locate the TSVs and void defects in these 2D X-ray scans which would be difficult to label manually as these voids look very fuzzy in 2D scans. Thereafter we use a state-of-the-art deep-learning segmentation network to train models to identify foreground (TSV, void defects) from the background. We show that our model can accurately identify the TSVs and their voids in images where it is impossible to locate the defects manually. We report a dice score of 0.87 for TSV segmentation and a dice score of 0.67 for void detection. The dice score for voids demonstrates the capability of our models to detect these difficult buried defects in 2D directly.
良率的提高是半导体制造的关键组成部分。它是通过收集、分析、确定缺陷的原因,然后提出解决根本原因的实际解决方案来完成的。半导体元件,如硅通孔(tsv)和其他封装互连正变得越来越小,随着工业的不断小型化的进展。在这些隐藏的互连中检测缺陷变得越来越困难和重要。我们收集含有缺陷(如空洞)的缺陷tsv的二维和三维x射线扫描。我们在3D中标记数据,并在2D和3D扫描之间进行配准。我们使用这些配准信息来定位这些二维x射线扫描中的tsv和空洞缺陷,这些缺陷很难手工标记,因为这些空洞在二维扫描中看起来非常模糊。然后,我们使用最先进的深度学习分割网络来训练模型,以从背景中识别前景(TSV,空洞缺陷)。我们表明,我们的模型可以准确地识别图像中不可能手动定位缺陷的tsv及其空洞。我们报告了TSV分割的骰子得分为0.87,空洞检测的骰子得分为0.67。空洞的骰子分数证明了我们的模型在2D中直接检测这些困难的隐藏缺陷的能力。
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引用次数: 3
Investigation of Aromatic Voltage Stabilizers for Enhancing High Voltage Stability of Epoxy for Power Electronics 芳香稳压器提高电力电子用环氧树脂高压稳定性的研究
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00367
Jiaxiong Li, K. Mohanalingam, Omkar Gupte, Zhijian Sun, K. Moon, C. Wong
Drive train electrification in automotive industry has become the general trend in recent years. As crucial components in the encapsulation and isolation of future wide-bandgap semiconductor-based power cards, epoxy resin and its composites face great challenges from the high voltage operation. This work provides an exploration into employing a group of polycyclic aromatic hydrocarbon molecules with varied number of aromatic rings, namely naphthalene, anthracene and pyrene, as voltage stabilizers in epoxy resin. The conjugated $pi$ system can be excited by the incoming high energy electrons, thus absorbing their kinetic energy which endangers the polymer integrity. The UV-Vis spectra of the compounds were recorded to illustrate the energy absorbing behavior, and the effects of these additives on epoxy curing, glass transition temperature and dielectric properties are presented. In the study, pyrene was found to enhance the breakdown voltage of the epoxy film.
近年来,汽车传动系统电气化已成为汽车工业发展的大趋势。环氧树脂及其复合材料作为未来宽带隙半导体电源卡封装和隔离的关键部件,面临着高压工作带来的巨大挑战。本研究探索了采用萘、蒽和芘等具有不同环数的多环芳烃分子作为环氧树脂的电压稳定剂。共轭$pi$系统会被进入的高能电子激发,从而吸收它们的动能,从而危及聚合物的完整性。记录了化合物的紫外可见光谱以说明其吸能行为,并给出了这些添加剂对环氧树脂固化、玻璃化转变温度和介电性能的影响。在研究中发现,芘可以提高环氧膜的击穿电压。
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引用次数: 0
Effect of Bismuth Content on the Mechanical Cyclic Properties of SAC+Bi Lead Free Solders 铋含量对SAC+Bi无铅钎料循环力学性能的影响
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00284
M. A. Haq, M. A. Hoque, J. Suhling, P. Lall
During the transition from tin-lead solders to lead-free solders, Sn-Ag-Cu (SAC) alloys have become the most widely used lead free alloys for the various levels of interconnects in an electronic package. To improve the thermal cycling reliability of SAC alloys, new doped $text{SAC} +mathrm{X}$ alloys have been developed, were X = Bismuth is often added to provide enhanced strength and improved aging resistance. Our prior work has shown that the use of $text{SAC}+text{Bi}$ solders can improve the reliability of the electronic package. However, there have been only limited studies regarding the cyclic mechanical properties of lead free SAC solder alloys with added bismuth content. In this paper, the authors have quantified the evolution of the properties of $text{SAC} +text{Bi}$ lead free solder joints subjected to isothermal mechanical cycling. Various levels of bismuth content have been studied including 1%, 2%, and 3%, and the results have been compared to previous studies performed on SAC305. Cylindrical solder specimens were prepared and reflowed with a reflow profile similar to that utilized in industry SMT joints. The formed samples were then mechanically cycled at room temperature using five different total strain ranges including 0.003, 0.005, 0.007, 0.009, and 0.012. The obtained cyclic stress-strain curves were recorded up to the 20th cycle, where the hysteresis loops became somewhat stable from one cycle to the other. The obtained hysteresis loops were then analyzed to evaluate the plastic work accumulated, the peak stress, and the plastic strain range for each of the total strain ranges considered. The plastic work dissipated per cycle is often an important parameter in predicting solder joint reliability with models such as the Morrow/Darveaux models. For each solder alloy, the obtained plastic work was correlated with the applied total strain range to develop correlations between the two quantities. Using the obtained results, specimens of the various $text{SAC} +text{Bi}$ alloys were then mechanically cycled to failure using the same initial plastic work (hysteresis loop area) in the first cycle. Failure was considered to have occurred with a 50% drop of the applied load. The cyclic stress-strain loops obtained from the fatigue failure cyclic experiments were then studied to measure the change in the cyclic properties for different bismuth contents. This approach removed the limitations from previous fatigue life studies where a constant strain range was used across all the alloys, which resulted in various hysteresis loop sizes. Rectangular cross-sectioned and polished samples of all the alloys were also cycled at the same corresponding strain ranges to study the change in microstructure of the alloys with mechanical cycling. This has helped us gain a better understanding on how the bismuth percentage in an alloy affects the microstructure evolution during mechanical cycling.
在锡铅焊料向无铅焊料过渡的过程中,Sn-Ag-Cu (SAC)合金已成为电子封装中各级互连中应用最广泛的无铅合金。为了提高SAC合金的热循环可靠性,开发了新的掺杂$text{SAC} + maththrm {X}$合金,其中X =铋经常被添加以提供增强的强度和改善的抗老化性。我们之前的工作表明,使用$text{SAC}+text{Bi}$焊料可以提高电子封装的可靠性。然而,关于添加铋的无铅SAC钎料合金的循环力学性能的研究非常有限。在本文中,作者量化了$text{SAC} +text{Bi}$无铅焊点在等温机械循环作用下的性能演变。研究了不同水平的铋含量,包括1%、2%和3%,并将结果与先前在SAC305上进行的研究进行了比较。制备了圆柱形焊料试样,并使用类似于工业SMT接头中使用的回流曲线进行回流。然后在室温下使用0.003、0.005、0.007、0.009和0.012五种不同的总应变范围进行机械循环。得到的循环应力-应变曲线记录到第20个循环,从一个循环到另一个循环,滞回曲线趋于稳定。然后对得到的滞回线进行分析,以评估所考虑的每个总应变范围的累积塑性功、峰值应力和塑性应变范围。每个周期消耗的塑料功通常是预测焊点可靠性的一个重要参数,如Morrow/Darveaux模型。对于每种焊料合金,获得的塑性功与应用的总应变范围相关联,以建立两者之间的相关性。利用得到的结果,在第一次循环中使用相同的初始塑性功(迟滞回线面积),对各种$text{SAC} +text{Bi}$合金试样进行机械循环直至失效。故障被认为发生了50%的下降所施加的负载。然后研究了疲劳破坏循环试验得到的循环应力-应变环,以测量不同铋含量下循环性能的变化。这种方法消除了以前的疲劳寿命研究的局限性,在这些研究中,所有合金都使用恒定的应变范围,导致各种迟滞回线尺寸。在相同的应变范围内,对所有合金的矩形截面和抛光试样进行循环,研究合金的微观组织随机械循环的变化。这有助于我们更好地理解合金中铋含量对机械循环过程中微观组织演变的影响。
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引用次数: 2
Next generation of adhesion enhancement system for high speed substrate manufacturing 用于高速基材制造的下一代附着力增强系统
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00042
T. Thomas, P. Brooks, F. Michalik, W. Cho
Improving adhesion between copper and lamination resin is one of the biggest challenges in micro-electronic manufacturing, such as IC substrate. Bonding enhancement process by surface roughening is predominant use method, due to providing the highest possible mechanical interlocking. In this process typically $mathrm{1}-mathrm{2} mumathrm{m}$ of copper need to be removed for reliable adhesion of dielectrics to the copper surface. Follow rapid development of electronics industry, where fine $mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$ and good signal propagation at higher speed are required. The conventional approach to ensure good adhesion of the conductor to the dielectrics by increasing surface roughness to achieve adhesion is no longer applicable. This work demonstrates the development of a novel surface treatment method of copper which can meet all the challenges of IC substate manufacturing for high speed function. The developed surface treatment system adopted subsequent treatment of organic coating so called “adhesion promoter (AP)” on top of copper surface to provide the strongest possible bond strength via chemical adhesion. As a result, significant improvement of adhesion of conductor to dielectrics can be obtained at ultra-low copper surface roughness.
提高铜与层压树脂之间的粘附性是微电子制造中最大的挑战之一,例如集成电路衬底。由于提供了尽可能高的机械联锁,通过表面粗化增强粘合工艺是主要的使用方法。在这个过程中,通常需要去除$ mathm {1}- $ mathm {2} mu mathm {m}$的铜,以保证电介质与铜表面的可靠粘附。随着电子工业的快速发展,对$mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$和较高速度下良好的信号传播提出了要求。通过增加表面粗糙度来确保导体与电介质良好粘附的传统方法已不再适用。这项工作证明了一种新的铜表面处理方法的发展,可以满足高速功能IC基态制造的所有挑战。所开发的表面处理系统采用了在铜表面上进行后续处理的有机涂层,即所谓的“粘附促进剂(AP)”,通过化学粘附提供尽可能强的结合强度。结果表明,在铜表面粗糙度极低的情况下,导体与介电体的附着力显著提高。
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引用次数: 0
PI/SI consideration for enabling 3D IC design PI/SI考虑实现3D IC设计
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00211
Jung-Man Son, S. Moon, Seungki Nam, Wook Kim
In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.
在这项工作中,我们提出了在设计3D IC时应考虑功率完整性(PI)和信号完整性(SI)的参数的综合分析方法。通过分析3D IC的基本结构,将每个模块分离并使用等效电路公式修改为简化模型,以创建简化的全系统仿真环境。利用该结构分析了考虑不同通硅通孔(TSV)类型、节距等因素的系统供电网络(PDN)环境下的电压噪声,并比较了与现有二维结构的区别。此外,还发现电压降与面积开销之间存在一种权衡关系,即tsv数量的增加以及同时满足这两个条件的优化过程。最后,考虑到3D集成电路初始设计阶段的热效应,对IP布局的顶部和底部模具所需的IP功率密度进行了检查。每个单独的分析都总结在一个统一的数据库中,并最终能够通过找到满足所有给定条件的解决方案的过程,在早期阶段提供设计指南。
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引用次数: 3
Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance 系统级封装中并排分立SoC-DRAM配置对SI、PI和热性能的影响
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00285
Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im
In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.
在本文中,在SI(信号完整性),PI(功率完整性)和热性能方面,将SoC(片上系统)- DRAM配置的2D平面并排SiP(系统中封装)与传统的单芯片封装(单芯片封装)进行了比较。在SI和PI方面,DQ信号的孔径宽度被用作性能决策的优劣指标。SiP较短的信道长度和较少的不连续可以导致更大的孔径,但其更长的和更小的PDN(电力输送网络)形状使其变窄。为了提高SiP PI和由此产生的更宽的眼孔径宽度,De-cap(去耦电容)值被扫描,它们的数量、容量和位置被改变。最后,可以找到实现稳健PI性能的最佳De-cap放置。然而,由于SiP配置的SoC与DRAM之间的距离较短,热耦合较大,因此SiP配置的热性能相对较板载SCP差。热比较是基于SoC和DRAM顶部表面的两个温度,以及两个SoC的泄漏功率。通过对星载SCP和SiP协议的比较研究,对如何在数字电视(D-TV)的SiP应用中采用先进的DDR特性有了基本的了解。
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引用次数: 1
Comparison of Global Optimization Algorithms for Inverse Design of Substrate Metal Density for Low Warpage Design in Ultra-Thin Packages 面向超薄封装低翘曲设计的基板金属密度反设计全局优化算法比较
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00363
C. Selvanayagam, P. Duong, Brett Wilkerson, N. Raghavan
An inverse design framework incorporating a physics-based surrogate model and global optimization is proposed to assist in the design of low warpage ultra-thin packages by adjusting the metal densities over substrate subsections and layers. The surrogate model is derived from two finite element analysis (FEA) models. The first one describes the relationship between the metal density in the substrate layer to the coefficient of thermal expansion (CTE) while the second one describes the relationship between in-plane CTE variation of the substrate to the warpage profile. Results from these two FEA models are used to train separate artificial neural networks (ANN). When these ANNs are run sequentially, the surrogate model can accurately determine the warpage profile for any set of metal densities. Three global optimization algorithms, Particle Swarm Optimization (PSO), Genetic Algorithm (GA) and Cross Entropy (CE) were then evaluated using this surrogate model. Three case studies consisting of different warpage profiles (original and 20% reduced warpage) and constraints to the optimization search space (±20% or ±50% change to metal density) were then evaluated using these algorithms. For all three cases, the three algorithms converged to similar solutions, indicating that indeed the global minimum has been attained and determined. However, GA took a significantly longer time to converge than PSO and CE. Based on these results, PSO and CE are recommended to be suitable algorithms to carry out inverse design for this type of problem.
提出了一个包含基于物理的代理模型和全局优化的逆设计框架,通过调整基板分段和层上的金属密度来帮助设计低翘曲超薄封装。代理模型由两个有限元分析模型推导而来。第一个模型描述了基板层中的金属密度与热膨胀系数(CTE)之间的关系,第二个模型描述了基板的平面内CTE变化与翘曲轮廓之间的关系。这两种有限元模型的结果用于训练单独的人工神经网络。当这些人工神经网络依次运行时,代理模型可以准确地确定任何一组金属密度的翘曲分布。利用该模型对粒子群优化(PSO)、遗传算法(GA)和交叉熵优化(CE)三种全局优化算法进行了评价。然后使用这些算法评估了由不同翘曲轮廓(原始翘曲和减少20%翘曲)和优化搜索空间约束(金属密度变化±20%或±50%)组成的三个案例研究。对于这三种情况,三种算法收敛到相似的解,表明确实已经达到并确定了全局最小值。然而,遗传算法的收敛时间明显长于PSO和CE。在此基础上,提出了PSO算法和CE算法作为求解该类问题的合适算法。
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引用次数: 1
Evaluation of Low-k Integration Integrity Using Shear Testing on Sub-30 Micron Micro-Cu Pillars 基于剪切试验的亚30微米微铜柱低k集成完整性评价
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00139
Tae-Kyu Lee, Greg Baty, O. Ahmed, P. Su, Bernard Glasauer
Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.
对于使用先进硅节点的器件来说,低k介电薄膜的机械完整性仍然是一个质量和可靠性方面的挑战。在晶圆厂,虽然在控制和监控单个加工步骤方面付出了巨大的努力,但通常无法有效地监控特定设备的整体机械质量。界面分层等缺陷可能仅在系统组装过程中或现场操作中出现,对生产和产品质量造成重大干扰和影响。随着硅尺寸和封装尺寸的不断增长,芯片封装相互作用变得更加重要,因此低k相关故障的风险也随之增加。特别是对于3D和2.5D器件,芯片堆叠的复杂性使得对介电质量进行定量评估对于良率和持续可靠性管理都很重要。在2.5D和3D器件上采用微铜柱为直接测量集成质量提供了机会。如果可以对单个微铜柱进行剪切测试,则可以对此类测试的响应进行分析和量化,作为集成质量的直接测量。此外,这样的测试可以在感兴趣的特定设备和模具上的特定位置进行,这使得有可能使用这种技术作为产品质量控制方法。本文将报道亚30微米微铜柱的剪切试验结果。将报告来自多个晶圆、晶片和凸点位置的数据。分析了载荷-距离曲线和最大断裂载荷等响应。此外,还建立了多级有限元模型来模拟剪切试验。应力集中的位置将被识别,并与剪切试验中的断裂界面进行比较。还将研究介电层特性变化的响应,从而深入了解在实际share测试中观察到的剪切强度变化。
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引用次数: 0
IEEE 71st Electronic Components and Technology Conference [Title page] IEEE第71届电子元件与技术会议[标题页]
Pub Date : 2021-06-01 DOI: 10.1109/ectc32696.2021.00002
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引用次数: 0
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2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
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