Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00039
F. Herrault, J. Wong, I. Ramos, H. Tai, M. King
The Metal Embedded Chiplet Assembly for Microwave Integrated Circuits (MECAMIC) technology utilizes RF GaN transistor chiplets integrated into passive interposer wafers using a metal electroplating embedding approach. Chiplets in Wafers (CiW) enable high level of integration between the transistor chiplets and the packaging circuitry, resulting in high RF performance. In this paper, we present the detailed process flow, the development of a MECAMIC Process Design Kit (PDK) for mm-wave RF Integrated Circuits (ICs), and its application to the design, simulation, fabrication and measurements of heterogeneously-integrated multi-stage W-band Low Noise Amplifiers (LNAs) using state-of-the-art mm-wave GaN transistor chiplets and low-cost silicon interposer packaging with 16 dB gain and 4dB noise figure at 77 GHz.
{"title":"Chiplets in Wafers (CiW) - Process Design Kit and Demonstration of High-Frequency Circuits with GaN Chiplets in Silicon Interposers","authors":"F. Herrault, J. Wong, I. Ramos, H. Tai, M. King","doi":"10.1109/ECTC32696.2021.00039","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00039","url":null,"abstract":"The Metal Embedded Chiplet Assembly for Microwave Integrated Circuits (MECAMIC) technology utilizes RF GaN transistor chiplets integrated into passive interposer wafers using a metal electroplating embedding approach. Chiplets in Wafers (CiW) enable high level of integration between the transistor chiplets and the packaging circuitry, resulting in high RF performance. In this paper, we present the detailed process flow, the development of a MECAMIC Process Design Kit (PDK) for mm-wave RF Integrated Circuits (ICs), and its application to the design, simulation, fabrication and measurements of heterogeneously-integrated multi-stage W-band Low Noise Amplifiers (LNAs) using state-of-the-art mm-wave GaN transistor chiplets and low-cost silicon interposer packaging with 16 dB gain and 4dB noise figure at 77 GHz.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131469294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00298
K. Murayama, Mitsuhiro Aizawa, K. Oi
In recent years, global warming prevention and reduction of energy consumption are increasingly required. And technical point of view, low stress bonding is required. A low temperature bonding using Sn-Bi solder is candidate technique to solve these problems. In this report, improving the reliability of electro-migration at flip chip interconnect in Sn-Bi solder, which is a low-temperature solder, are focused. A combination of six types of Sn-Bi solder and surface finish of interposer pad were studied, these are, combination of Sn30wt.%Bi (Sn30Bi) solder, Sn57wt.%Bi (Sn57Bi) solder, electroless Ni/Au on Cu pad and Ni/Pd/ Au on Cu pad. The effects of Bi concentration, trace element and inter-metallic compounds formation on electromigration resistivity were evaluated. The current density of 40 kA/cm2 was applied at 125 degrees C. Analysis of the microstructure and crystal orientation of the interconnected bumps were performed in all combinations by electron backscatter diffraction and electron probe microanalyzer. Mean time to failure of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick) and that of Sn30Bi/NiPdAu were19, 141 and 600 hours, respectively. And maximum resistance increases from initial of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick), Sn30Bi/NiPdAu were 60.6%, 19.5%, 13.2% after 2500 hours. Reducing the total amount of Au and Pd atoms in the solder can delay increase of resistance after current stressing. In cases of NiAu(thick) and NiAu(thin) pads, two types of failure mode were observed after current stressing. One was growth of large (Cu, Ni)6Sn5 with thick Ni(P rich) layer. The other was the mode in which (Cu, Ni) 6Sn5 hardly grow and unreacted Sn layer remains. In case of c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad to the solder was accelerated. On the other hand, in the case of NiPdAu pad, only one failure mode was observed after current stressing. It is a mode in which the unreacted Sn layer remains. Even if c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad was not observed. Focusing on the intermetallic compounds (IMCs) formed on the interposer pad after 10% resistance change, in cases of NiAu(thick) and NiAu(thin) pads, un-uniform and needle-type (Cu, Ni) 6Sn5 were formed. Large Ni diffusion from their grain boundary into IMCs were observed after current stressing. On the other hand, in the case of NiPdAu pad, thin (Ni, Cu)3Sn4 and uniform and dense scallop-type (Cu, Ni)6Sn5 were formed after 10% resistance change. They were still stabled after current stressing. The significant increase in resistance in the early stage is influenced by Bi concentration in solder. And Au atoms play a role of accelerating diffusion and increase in resistance at early stage on electro-migration test. Dense scallop-type (Cu, Ni)6Sn5 layer on Ni pad showed as an effective barrier diffusion of Cu or Ni. It was found that if a uniform and dense IMCs were formed on the interpose
{"title":"Effect of crystal anisotropy and IMCs on electromigration resistivity of low temperature flip chip interconnect","authors":"K. Murayama, Mitsuhiro Aizawa, K. Oi","doi":"10.1109/ECTC32696.2021.00298","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00298","url":null,"abstract":"In recent years, global warming prevention and reduction of energy consumption are increasingly required. And technical point of view, low stress bonding is required. A low temperature bonding using Sn-Bi solder is candidate technique to solve these problems. In this report, improving the reliability of electro-migration at flip chip interconnect in Sn-Bi solder, which is a low-temperature solder, are focused. A combination of six types of Sn-Bi solder and surface finish of interposer pad were studied, these are, combination of Sn30wt.%Bi (Sn30Bi) solder, Sn57wt.%Bi (Sn57Bi) solder, electroless Ni/Au on Cu pad and Ni/Pd/ Au on Cu pad. The effects of Bi concentration, trace element and inter-metallic compounds formation on electromigration resistivity were evaluated. The current density of 40 kA/cm2 was applied at 125 degrees C. Analysis of the microstructure and crystal orientation of the interconnected bumps were performed in all combinations by electron backscatter diffraction and electron probe microanalyzer. Mean time to failure of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick) and that of Sn30Bi/NiPdAu were19, 141 and 600 hours, respectively. And maximum resistance increases from initial of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick), Sn30Bi/NiPdAu were 60.6%, 19.5%, 13.2% after 2500 hours. Reducing the total amount of Au and Pd atoms in the solder can delay increase of resistance after current stressing. In cases of NiAu(thick) and NiAu(thin) pads, two types of failure mode were observed after current stressing. One was growth of large (Cu, Ni)6Sn5 with thick Ni(P rich) layer. The other was the mode in which (Cu, Ni) 6Sn5 hardly grow and unreacted Sn layer remains. In case of c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad to the solder was accelerated. On the other hand, in the case of NiPdAu pad, only one failure mode was observed after current stressing. It is a mode in which the unreacted Sn layer remains. Even if c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad was not observed. Focusing on the intermetallic compounds (IMCs) formed on the interposer pad after 10% resistance change, in cases of NiAu(thick) and NiAu(thin) pads, un-uniform and needle-type (Cu, Ni) 6Sn5 were formed. Large Ni diffusion from their grain boundary into IMCs were observed after current stressing. On the other hand, in the case of NiPdAu pad, thin (Ni, Cu)3Sn4 and uniform and dense scallop-type (Cu, Ni)6Sn5 were formed after 10% resistance change. They were still stabled after current stressing. The significant increase in resistance in the early stage is influenced by Bi concentration in solder. And Au atoms play a role of accelerating diffusion and increase in resistance at early stage on electro-migration test. Dense scallop-type (Cu, Ni)6Sn5 layer on Ni pad showed as an effective barrier diffusion of Cu or Ni. It was found that if a uniform and dense IMCs were formed on the interpose","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121781348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00149
A. Schiffmacher, D. Strahringer, Shreyas Malasani, J. Wilde, Carsten Kempiak, A. Lindemann
Within the scope of this work three in-situ degradation monitoring methods are presented. The methods are suitable for the detection of degradations in power electronic modules during active power cycling test without interrupting the test itself. A comparison of the results is illustrated by conducting all three techniques during the lifetime testing of a power electronic module at the same time. In sum, electrical, electrothermal, thermal and thermomechanical parameters were evaluated. From the observations, we conclude that the primary failure mechanism of a novel die-top interconnect technology for power modules is the crack propagation in the Al-metallisation of the semiconductor. Cross-sectional images of the samples were prepared to confirm the previously given evidence of the failure. Furthermore a lifetime model was established for this assembly technology. Finally, a comparison of the advantages and limitations of the conducted degradation monitoring techniques will be presented.
{"title":"In Situ Degradation Monitoring Methods during Lifetime Testing of Power Electronic Modules","authors":"A. Schiffmacher, D. Strahringer, Shreyas Malasani, J. Wilde, Carsten Kempiak, A. Lindemann","doi":"10.1109/ECTC32696.2021.00149","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00149","url":null,"abstract":"Within the scope of this work three in-situ degradation monitoring methods are presented. The methods are suitable for the detection of degradations in power electronic modules during active power cycling test without interrupting the test itself. A comparison of the results is illustrated by conducting all three techniques during the lifetime testing of a power electronic module at the same time. In sum, electrical, electrothermal, thermal and thermomechanical parameters were evaluated. From the observations, we conclude that the primary failure mechanism of a novel die-top interconnect technology for power modules is the crack propagation in the Al-metallisation of the semiconductor. Cross-sectional images of the samples were prepared to confirm the previously given evidence of the failure. Furthermore a lifetime model was established for this assembly technology. Finally, a comparison of the advantages and limitations of the conducted degradation monitoring techniques will be presented.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133223975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00069
F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann
In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5 mumathrm{m}$ edge length bumps and fine pitches less than $8 mumathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $mu mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.
{"title":"Room Temperature KlettWelding Interconnect Technology for High Performance CMOS Logic","authors":"F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann","doi":"10.1109/ECTC32696.2021.00069","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00069","url":null,"abstract":"In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5 mumathrm{m}$ edge length bumps and fine pitches less than $8 mumathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $mu mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00259
Hongyu Li, W. Seit, Hwang Gilho, P. Zhao, J. Tao, C. S. Tan
Si substrate provide the integration platform for surface ion trap device fabrication. Grounding metal for the surface ion trap is necessary because of high RF voltage ($> 100mathrm{V}$) applied and lower RF loss required within functionality. High resistivity Si substrate with floating metal grounding and low-grade Si substrate with connected grounding metal were integrated with surface ion trap. Ion trap resonance curves were observed at 47.1 MHz frequency for ion trap devices with different grounding metal. The curves have similar resonant power.
{"title":"Low Cost Grounding Integration for Surface Ion Trap","authors":"Hongyu Li, W. Seit, Hwang Gilho, P. Zhao, J. Tao, C. S. Tan","doi":"10.1109/ECTC32696.2021.00259","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00259","url":null,"abstract":"Si substrate provide the integration platform for surface ion trap device fabrication. Grounding metal for the surface ion trap is necessary because of high RF voltage ($> 100mathrm{V}$) applied and lower RF loss required within functionality. High resistivity Si substrate with floating metal grounding and low-grade Si substrate with connected grounding metal were integrated with surface ion trap. Ion trap resonance curves were observed at 47.1 MHz frequency for ion trap devices with different grounding metal. The curves have similar resonant power.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132282608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00143
R. Pahwa, S. Gopalakrishnan, Huang Su, Ong Ee Ping, Haiwen Dai, D. Wee, Ren Qin, V. S. Rao
Yield improvement is a critical component of semiconductor manufacturing. It is done by collecting, analyzing, identifying the causes of defects, and then coming up with a practical solution to resolve the root causes. Semiconductor components such as Through Silicon Vias (TSVs) and other package interconnects are getting smaller and smaller with the ongoing miniaturization progress in the industry. Detecting defects in these buried interconnects is becoming both more difficult and more important. We collect both 2D and 3D X-Ray scans of defective TSVs containing defects such as voids. We label the data in 3D and perform registration between 2D and 3D scans. We use this registration information to locate the TSVs and void defects in these 2D X-ray scans which would be difficult to label manually as these voids look very fuzzy in 2D scans. Thereafter we use a state-of-the-art deep-learning segmentation network to train models to identify foreground (TSV, void defects) from the background. We show that our model can accurately identify the TSVs and their voids in images where it is impossible to locate the defects manually. We report a dice score of 0.87 for TSV segmentation and a dice score of 0.67 for void detection. The dice score for voids demonstrates the capability of our models to detect these difficult buried defects in 2D directly.
{"title":"Automated Void Detection in TSVs from 2D X-Ray Scans using Supervised Learning with 3D X-Ray Scans","authors":"R. Pahwa, S. Gopalakrishnan, Huang Su, Ong Ee Ping, Haiwen Dai, D. Wee, Ren Qin, V. S. Rao","doi":"10.1109/ECTC32696.2021.00143","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00143","url":null,"abstract":"Yield improvement is a critical component of semiconductor manufacturing. It is done by collecting, analyzing, identifying the causes of defects, and then coming up with a practical solution to resolve the root causes. Semiconductor components such as Through Silicon Vias (TSVs) and other package interconnects are getting smaller and smaller with the ongoing miniaturization progress in the industry. Detecting defects in these buried interconnects is becoming both more difficult and more important. We collect both 2D and 3D X-Ray scans of defective TSVs containing defects such as voids. We label the data in 3D and perform registration between 2D and 3D scans. We use this registration information to locate the TSVs and void defects in these 2D X-ray scans which would be difficult to label manually as these voids look very fuzzy in 2D scans. Thereafter we use a state-of-the-art deep-learning segmentation network to train models to identify foreground (TSV, void defects) from the background. We show that our model can accurately identify the TSVs and their voids in images where it is impossible to locate the defects manually. We report a dice score of 0.87 for TSV segmentation and a dice score of 0.67 for void detection. The dice score for voids demonstrates the capability of our models to detect these difficult buried defects in 2D directly.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00367
Jiaxiong Li, K. Mohanalingam, Omkar Gupte, Zhijian Sun, K. Moon, C. Wong
Drive train electrification in automotive industry has become the general trend in recent years. As crucial components in the encapsulation and isolation of future wide-bandgap semiconductor-based power cards, epoxy resin and its composites face great challenges from the high voltage operation. This work provides an exploration into employing a group of polycyclic aromatic hydrocarbon molecules with varied number of aromatic rings, namely naphthalene, anthracene and pyrene, as voltage stabilizers in epoxy resin. The conjugated $pi$ system can be excited by the incoming high energy electrons, thus absorbing their kinetic energy which endangers the polymer integrity. The UV-Vis spectra of the compounds were recorded to illustrate the energy absorbing behavior, and the effects of these additives on epoxy curing, glass transition temperature and dielectric properties are presented. In the study, pyrene was found to enhance the breakdown voltage of the epoxy film.
{"title":"Investigation of Aromatic Voltage Stabilizers for Enhancing High Voltage Stability of Epoxy for Power Electronics","authors":"Jiaxiong Li, K. Mohanalingam, Omkar Gupte, Zhijian Sun, K. Moon, C. Wong","doi":"10.1109/ECTC32696.2021.00367","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00367","url":null,"abstract":"Drive train electrification in automotive industry has become the general trend in recent years. As crucial components in the encapsulation and isolation of future wide-bandgap semiconductor-based power cards, epoxy resin and its composites face great challenges from the high voltage operation. This work provides an exploration into employing a group of polycyclic aromatic hydrocarbon molecules with varied number of aromatic rings, namely naphthalene, anthracene and pyrene, as voltage stabilizers in epoxy resin. The conjugated $pi$ system can be excited by the incoming high energy electrons, thus absorbing their kinetic energy which endangers the polymer integrity. The UV-Vis spectra of the compounds were recorded to illustrate the energy absorbing behavior, and the effects of these additives on epoxy curing, glass transition temperature and dielectric properties are presented. In the study, pyrene was found to enhance the breakdown voltage of the epoxy film.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134511587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00284
M. A. Haq, M. A. Hoque, J. Suhling, P. Lall
During the transition from tin-lead solders to lead-free solders, Sn-Ag-Cu (SAC) alloys have become the most widely used lead free alloys for the various levels of interconnects in an electronic package. To improve the thermal cycling reliability of SAC alloys, new doped $text{SAC} +mathrm{X}$ alloys have been developed, were X = Bismuth is often added to provide enhanced strength and improved aging resistance. Our prior work has shown that the use of $text{SAC}+text{Bi}$ solders can improve the reliability of the electronic package. However, there have been only limited studies regarding the cyclic mechanical properties of lead free SAC solder alloys with added bismuth content. In this paper, the authors have quantified the evolution of the properties of $text{SAC} +text{Bi}$ lead free solder joints subjected to isothermal mechanical cycling. Various levels of bismuth content have been studied including 1%, 2%, and 3%, and the results have been compared to previous studies performed on SAC305. Cylindrical solder specimens were prepared and reflowed with a reflow profile similar to that utilized in industry SMT joints. The formed samples were then mechanically cycled at room temperature using five different total strain ranges including 0.003, 0.005, 0.007, 0.009, and 0.012. The obtained cyclic stress-strain curves were recorded up to the 20th cycle, where the hysteresis loops became somewhat stable from one cycle to the other. The obtained hysteresis loops were then analyzed to evaluate the plastic work accumulated, the peak stress, and the plastic strain range for each of the total strain ranges considered. The plastic work dissipated per cycle is often an important parameter in predicting solder joint reliability with models such as the Morrow/Darveaux models. For each solder alloy, the obtained plastic work was correlated with the applied total strain range to develop correlations between the two quantities. Using the obtained results, specimens of the various $text{SAC} +text{Bi}$ alloys were then mechanically cycled to failure using the same initial plastic work (hysteresis loop area) in the first cycle. Failure was considered to have occurred with a 50% drop of the applied load. The cyclic stress-strain loops obtained from the fatigue failure cyclic experiments were then studied to measure the change in the cyclic properties for different bismuth contents. This approach removed the limitations from previous fatigue life studies where a constant strain range was used across all the alloys, which resulted in various hysteresis loop sizes. Rectangular cross-sectioned and polished samples of all the alloys were also cycled at the same corresponding strain ranges to study the change in microstructure of the alloys with mechanical cycling. This has helped us gain a better understanding on how the bismuth percentage in an alloy affects the microstructure evolution during mechanical cycling.
{"title":"Effect of Bismuth Content on the Mechanical Cyclic Properties of SAC+Bi Lead Free Solders","authors":"M. A. Haq, M. A. Hoque, J. Suhling, P. Lall","doi":"10.1109/ECTC32696.2021.00284","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00284","url":null,"abstract":"During the transition from tin-lead solders to lead-free solders, Sn-Ag-Cu (SAC) alloys have become the most widely used lead free alloys for the various levels of interconnects in an electronic package. To improve the thermal cycling reliability of SAC alloys, new doped $text{SAC} +mathrm{X}$ alloys have been developed, were X = Bismuth is often added to provide enhanced strength and improved aging resistance. Our prior work has shown that the use of $text{SAC}+text{Bi}$ solders can improve the reliability of the electronic package. However, there have been only limited studies regarding the cyclic mechanical properties of lead free SAC solder alloys with added bismuth content. In this paper, the authors have quantified the evolution of the properties of $text{SAC} +text{Bi}$ lead free solder joints subjected to isothermal mechanical cycling. Various levels of bismuth content have been studied including 1%, 2%, and 3%, and the results have been compared to previous studies performed on SAC305. Cylindrical solder specimens were prepared and reflowed with a reflow profile similar to that utilized in industry SMT joints. The formed samples were then mechanically cycled at room temperature using five different total strain ranges including 0.003, 0.005, 0.007, 0.009, and 0.012. The obtained cyclic stress-strain curves were recorded up to the 20th cycle, where the hysteresis loops became somewhat stable from one cycle to the other. The obtained hysteresis loops were then analyzed to evaluate the plastic work accumulated, the peak stress, and the plastic strain range for each of the total strain ranges considered. The plastic work dissipated per cycle is often an important parameter in predicting solder joint reliability with models such as the Morrow/Darveaux models. For each solder alloy, the obtained plastic work was correlated with the applied total strain range to develop correlations between the two quantities. Using the obtained results, specimens of the various $text{SAC} +text{Bi}$ alloys were then mechanically cycled to failure using the same initial plastic work (hysteresis loop area) in the first cycle. Failure was considered to have occurred with a 50% drop of the applied load. The cyclic stress-strain loops obtained from the fatigue failure cyclic experiments were then studied to measure the change in the cyclic properties for different bismuth contents. This approach removed the limitations from previous fatigue life studies where a constant strain range was used across all the alloys, which resulted in various hysteresis loop sizes. Rectangular cross-sectioned and polished samples of all the alloys were also cycled at the same corresponding strain ranges to study the change in microstructure of the alloys with mechanical cycling. This has helped us gain a better understanding on how the bismuth percentage in an alloy affects the microstructure evolution during mechanical cycling.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134525140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00139
Tae-Kyu Lee, Greg Baty, O. Ahmed, P. Su, Bernard Glasauer
Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.
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