Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00259
Hongyu Li, W. Seit, Hwang Gilho, P. Zhao, J. Tao, C. S. Tan
Si substrate provide the integration platform for surface ion trap device fabrication. Grounding metal for the surface ion trap is necessary because of high RF voltage ($> 100mathrm{V}$) applied and lower RF loss required within functionality. High resistivity Si substrate with floating metal grounding and low-grade Si substrate with connected grounding metal were integrated with surface ion trap. Ion trap resonance curves were observed at 47.1 MHz frequency for ion trap devices with different grounding metal. The curves have similar resonant power.
{"title":"Low Cost Grounding Integration for Surface Ion Trap","authors":"Hongyu Li, W. Seit, Hwang Gilho, P. Zhao, J. Tao, C. S. Tan","doi":"10.1109/ECTC32696.2021.00259","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00259","url":null,"abstract":"Si substrate provide the integration platform for surface ion trap device fabrication. Grounding metal for the surface ion trap is necessary because of high RF voltage ($> 100mathrm{V}$) applied and lower RF loss required within functionality. High resistivity Si substrate with floating metal grounding and low-grade Si substrate with connected grounding metal were integrated with surface ion trap. Ion trap resonance curves were observed at 47.1 MHz frequency for ion trap devices with different grounding metal. The curves have similar resonant power.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132282608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00143
R. Pahwa, S. Gopalakrishnan, Huang Su, Ong Ee Ping, Haiwen Dai, D. Wee, Ren Qin, V. S. Rao
Yield improvement is a critical component of semiconductor manufacturing. It is done by collecting, analyzing, identifying the causes of defects, and then coming up with a practical solution to resolve the root causes. Semiconductor components such as Through Silicon Vias (TSVs) and other package interconnects are getting smaller and smaller with the ongoing miniaturization progress in the industry. Detecting defects in these buried interconnects is becoming both more difficult and more important. We collect both 2D and 3D X-Ray scans of defective TSVs containing defects such as voids. We label the data in 3D and perform registration between 2D and 3D scans. We use this registration information to locate the TSVs and void defects in these 2D X-ray scans which would be difficult to label manually as these voids look very fuzzy in 2D scans. Thereafter we use a state-of-the-art deep-learning segmentation network to train models to identify foreground (TSV, void defects) from the background. We show that our model can accurately identify the TSVs and their voids in images where it is impossible to locate the defects manually. We report a dice score of 0.87 for TSV segmentation and a dice score of 0.67 for void detection. The dice score for voids demonstrates the capability of our models to detect these difficult buried defects in 2D directly.
{"title":"Automated Void Detection in TSVs from 2D X-Ray Scans using Supervised Learning with 3D X-Ray Scans","authors":"R. Pahwa, S. Gopalakrishnan, Huang Su, Ong Ee Ping, Haiwen Dai, D. Wee, Ren Qin, V. S. Rao","doi":"10.1109/ECTC32696.2021.00143","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00143","url":null,"abstract":"Yield improvement is a critical component of semiconductor manufacturing. It is done by collecting, analyzing, identifying the causes of defects, and then coming up with a practical solution to resolve the root causes. Semiconductor components such as Through Silicon Vias (TSVs) and other package interconnects are getting smaller and smaller with the ongoing miniaturization progress in the industry. Detecting defects in these buried interconnects is becoming both more difficult and more important. We collect both 2D and 3D X-Ray scans of defective TSVs containing defects such as voids. We label the data in 3D and perform registration between 2D and 3D scans. We use this registration information to locate the TSVs and void defects in these 2D X-ray scans which would be difficult to label manually as these voids look very fuzzy in 2D scans. Thereafter we use a state-of-the-art deep-learning segmentation network to train models to identify foreground (TSV, void defects) from the background. We show that our model can accurately identify the TSVs and their voids in images where it is impossible to locate the defects manually. We report a dice score of 0.87 for TSV segmentation and a dice score of 0.67 for void detection. The dice score for voids demonstrates the capability of our models to detect these difficult buried defects in 2D directly.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00367
Jiaxiong Li, K. Mohanalingam, Omkar Gupte, Zhijian Sun, K. Moon, C. Wong
Drive train electrification in automotive industry has become the general trend in recent years. As crucial components in the encapsulation and isolation of future wide-bandgap semiconductor-based power cards, epoxy resin and its composites face great challenges from the high voltage operation. This work provides an exploration into employing a group of polycyclic aromatic hydrocarbon molecules with varied number of aromatic rings, namely naphthalene, anthracene and pyrene, as voltage stabilizers in epoxy resin. The conjugated $pi$ system can be excited by the incoming high energy electrons, thus absorbing their kinetic energy which endangers the polymer integrity. The UV-Vis spectra of the compounds were recorded to illustrate the energy absorbing behavior, and the effects of these additives on epoxy curing, glass transition temperature and dielectric properties are presented. In the study, pyrene was found to enhance the breakdown voltage of the epoxy film.
{"title":"Investigation of Aromatic Voltage Stabilizers for Enhancing High Voltage Stability of Epoxy for Power Electronics","authors":"Jiaxiong Li, K. Mohanalingam, Omkar Gupte, Zhijian Sun, K. Moon, C. Wong","doi":"10.1109/ECTC32696.2021.00367","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00367","url":null,"abstract":"Drive train electrification in automotive industry has become the general trend in recent years. As crucial components in the encapsulation and isolation of future wide-bandgap semiconductor-based power cards, epoxy resin and its composites face great challenges from the high voltage operation. This work provides an exploration into employing a group of polycyclic aromatic hydrocarbon molecules with varied number of aromatic rings, namely naphthalene, anthracene and pyrene, as voltage stabilizers in epoxy resin. The conjugated $pi$ system can be excited by the incoming high energy electrons, thus absorbing their kinetic energy which endangers the polymer integrity. The UV-Vis spectra of the compounds were recorded to illustrate the energy absorbing behavior, and the effects of these additives on epoxy curing, glass transition temperature and dielectric properties are presented. In the study, pyrene was found to enhance the breakdown voltage of the epoxy film.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134511587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00284
M. A. Haq, M. A. Hoque, J. Suhling, P. Lall
During the transition from tin-lead solders to lead-free solders, Sn-Ag-Cu (SAC) alloys have become the most widely used lead free alloys for the various levels of interconnects in an electronic package. To improve the thermal cycling reliability of SAC alloys, new doped $text{SAC} +mathrm{X}$ alloys have been developed, were X = Bismuth is often added to provide enhanced strength and improved aging resistance. Our prior work has shown that the use of $text{SAC}+text{Bi}$ solders can improve the reliability of the electronic package. However, there have been only limited studies regarding the cyclic mechanical properties of lead free SAC solder alloys with added bismuth content. In this paper, the authors have quantified the evolution of the properties of $text{SAC} +text{Bi}$ lead free solder joints subjected to isothermal mechanical cycling. Various levels of bismuth content have been studied including 1%, 2%, and 3%, and the results have been compared to previous studies performed on SAC305. Cylindrical solder specimens were prepared and reflowed with a reflow profile similar to that utilized in industry SMT joints. The formed samples were then mechanically cycled at room temperature using five different total strain ranges including 0.003, 0.005, 0.007, 0.009, and 0.012. The obtained cyclic stress-strain curves were recorded up to the 20th cycle, where the hysteresis loops became somewhat stable from one cycle to the other. The obtained hysteresis loops were then analyzed to evaluate the plastic work accumulated, the peak stress, and the plastic strain range for each of the total strain ranges considered. The plastic work dissipated per cycle is often an important parameter in predicting solder joint reliability with models such as the Morrow/Darveaux models. For each solder alloy, the obtained plastic work was correlated with the applied total strain range to develop correlations between the two quantities. Using the obtained results, specimens of the various $text{SAC} +text{Bi}$ alloys were then mechanically cycled to failure using the same initial plastic work (hysteresis loop area) in the first cycle. Failure was considered to have occurred with a 50% drop of the applied load. The cyclic stress-strain loops obtained from the fatigue failure cyclic experiments were then studied to measure the change in the cyclic properties for different bismuth contents. This approach removed the limitations from previous fatigue life studies where a constant strain range was used across all the alloys, which resulted in various hysteresis loop sizes. Rectangular cross-sectioned and polished samples of all the alloys were also cycled at the same corresponding strain ranges to study the change in microstructure of the alloys with mechanical cycling. This has helped us gain a better understanding on how the bismuth percentage in an alloy affects the microstructure evolution during mechanical cycling.
{"title":"Effect of Bismuth Content on the Mechanical Cyclic Properties of SAC+Bi Lead Free Solders","authors":"M. A. Haq, M. A. Hoque, J. Suhling, P. Lall","doi":"10.1109/ECTC32696.2021.00284","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00284","url":null,"abstract":"During the transition from tin-lead solders to lead-free solders, Sn-Ag-Cu (SAC) alloys have become the most widely used lead free alloys for the various levels of interconnects in an electronic package. To improve the thermal cycling reliability of SAC alloys, new doped $text{SAC} +mathrm{X}$ alloys have been developed, were X = Bismuth is often added to provide enhanced strength and improved aging resistance. Our prior work has shown that the use of $text{SAC}+text{Bi}$ solders can improve the reliability of the electronic package. However, there have been only limited studies regarding the cyclic mechanical properties of lead free SAC solder alloys with added bismuth content. In this paper, the authors have quantified the evolution of the properties of $text{SAC} +text{Bi}$ lead free solder joints subjected to isothermal mechanical cycling. Various levels of bismuth content have been studied including 1%, 2%, and 3%, and the results have been compared to previous studies performed on SAC305. Cylindrical solder specimens were prepared and reflowed with a reflow profile similar to that utilized in industry SMT joints. The formed samples were then mechanically cycled at room temperature using five different total strain ranges including 0.003, 0.005, 0.007, 0.009, and 0.012. The obtained cyclic stress-strain curves were recorded up to the 20th cycle, where the hysteresis loops became somewhat stable from one cycle to the other. The obtained hysteresis loops were then analyzed to evaluate the plastic work accumulated, the peak stress, and the plastic strain range for each of the total strain ranges considered. The plastic work dissipated per cycle is often an important parameter in predicting solder joint reliability with models such as the Morrow/Darveaux models. For each solder alloy, the obtained plastic work was correlated with the applied total strain range to develop correlations between the two quantities. Using the obtained results, specimens of the various $text{SAC} +text{Bi}$ alloys were then mechanically cycled to failure using the same initial plastic work (hysteresis loop area) in the first cycle. Failure was considered to have occurred with a 50% drop of the applied load. The cyclic stress-strain loops obtained from the fatigue failure cyclic experiments were then studied to measure the change in the cyclic properties for different bismuth contents. This approach removed the limitations from previous fatigue life studies where a constant strain range was used across all the alloys, which resulted in various hysteresis loop sizes. Rectangular cross-sectioned and polished samples of all the alloys were also cycled at the same corresponding strain ranges to study the change in microstructure of the alloys with mechanical cycling. This has helped us gain a better understanding on how the bismuth percentage in an alloy affects the microstructure evolution during mechanical cycling.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134525140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00042
T. Thomas, P. Brooks, F. Michalik, W. Cho
Improving adhesion between copper and lamination resin is one of the biggest challenges in micro-electronic manufacturing, such as IC substrate. Bonding enhancement process by surface roughening is predominant use method, due to providing the highest possible mechanical interlocking. In this process typically $mathrm{1}-mathrm{2} mumathrm{m}$ of copper need to be removed for reliable adhesion of dielectrics to the copper surface. Follow rapid development of electronics industry, where fine $mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$ and good signal propagation at higher speed are required. The conventional approach to ensure good adhesion of the conductor to the dielectrics by increasing surface roughness to achieve adhesion is no longer applicable. This work demonstrates the development of a novel surface treatment method of copper which can meet all the challenges of IC substate manufacturing for high speed function. The developed surface treatment system adopted subsequent treatment of organic coating so called “adhesion promoter (AP)” on top of copper surface to provide the strongest possible bond strength via chemical adhesion. As a result, significant improvement of adhesion of conductor to dielectrics can be obtained at ultra-low copper surface roughness.
{"title":"Next generation of adhesion enhancement system for high speed substrate manufacturing","authors":"T. Thomas, P. Brooks, F. Michalik, W. Cho","doi":"10.1109/ECTC32696.2021.00042","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00042","url":null,"abstract":"Improving adhesion between copper and lamination resin is one of the biggest challenges in micro-electronic manufacturing, such as IC substrate. Bonding enhancement process by surface roughening is predominant use method, due to providing the highest possible mechanical interlocking. In this process typically $mathrm{1}-mathrm{2} mumathrm{m}$ of copper need to be removed for reliable adhesion of dielectrics to the copper surface. Follow rapid development of electronics industry, where fine $mathrm{L}/mathrm{S}, (< mathrm{10} mumathrm{m})$ and good signal propagation at higher speed are required. The conventional approach to ensure good adhesion of the conductor to the dielectrics by increasing surface roughness to achieve adhesion is no longer applicable. This work demonstrates the development of a novel surface treatment method of copper which can meet all the challenges of IC substate manufacturing for high speed function. The developed surface treatment system adopted subsequent treatment of organic coating so called “adhesion promoter (AP)” on top of copper surface to provide the strongest possible bond strength via chemical adhesion. As a result, significant improvement of adhesion of conductor to dielectrics can be obtained at ultra-low copper surface roughness.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115422224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00211
Jung-Man Son, S. Moon, Seungki Nam, Wook Kim
In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.
{"title":"PI/SI consideration for enabling 3D IC design","authors":"Jung-Man Son, S. Moon, Seungki Nam, Wook Kim","doi":"10.1109/ECTC32696.2021.00211","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00211","url":null,"abstract":"In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115514507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00285
Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im
In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.
{"title":"Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance","authors":"Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im","doi":"10.1109/ECTC32696.2021.00285","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00285","url":null,"abstract":"In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00363
C. Selvanayagam, P. Duong, Brett Wilkerson, N. Raghavan
An inverse design framework incorporating a physics-based surrogate model and global optimization is proposed to assist in the design of low warpage ultra-thin packages by adjusting the metal densities over substrate subsections and layers. The surrogate model is derived from two finite element analysis (FEA) models. The first one describes the relationship between the metal density in the substrate layer to the coefficient of thermal expansion (CTE) while the second one describes the relationship between in-plane CTE variation of the substrate to the warpage profile. Results from these two FEA models are used to train separate artificial neural networks (ANN). When these ANNs are run sequentially, the surrogate model can accurately determine the warpage profile for any set of metal densities. Three global optimization algorithms, Particle Swarm Optimization (PSO), Genetic Algorithm (GA) and Cross Entropy (CE) were then evaluated using this surrogate model. Three case studies consisting of different warpage profiles (original and 20% reduced warpage) and constraints to the optimization search space (±20% or ±50% change to metal density) were then evaluated using these algorithms. For all three cases, the three algorithms converged to similar solutions, indicating that indeed the global minimum has been attained and determined. However, GA took a significantly longer time to converge than PSO and CE. Based on these results, PSO and CE are recommended to be suitable algorithms to carry out inverse design for this type of problem.
{"title":"Comparison of Global Optimization Algorithms for Inverse Design of Substrate Metal Density for Low Warpage Design in Ultra-Thin Packages","authors":"C. Selvanayagam, P. Duong, Brett Wilkerson, N. Raghavan","doi":"10.1109/ECTC32696.2021.00363","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00363","url":null,"abstract":"An inverse design framework incorporating a physics-based surrogate model and global optimization is proposed to assist in the design of low warpage ultra-thin packages by adjusting the metal densities over substrate subsections and layers. The surrogate model is derived from two finite element analysis (FEA) models. The first one describes the relationship between the metal density in the substrate layer to the coefficient of thermal expansion (CTE) while the second one describes the relationship between in-plane CTE variation of the substrate to the warpage profile. Results from these two FEA models are used to train separate artificial neural networks (ANN). When these ANNs are run sequentially, the surrogate model can accurately determine the warpage profile for any set of metal densities. Three global optimization algorithms, Particle Swarm Optimization (PSO), Genetic Algorithm (GA) and Cross Entropy (CE) were then evaluated using this surrogate model. Three case studies consisting of different warpage profiles (original and 20% reduced warpage) and constraints to the optimization search space (±20% or ±50% change to metal density) were then evaluated using these algorithms. For all three cases, the three algorithms converged to similar solutions, indicating that indeed the global minimum has been attained and determined. However, GA took a significantly longer time to converge than PSO and CE. Based on these results, PSO and CE are recommended to be suitable algorithms to carry out inverse design for this type of problem.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00139
Tae-Kyu Lee, Greg Baty, O. Ahmed, P. Su, Bernard Glasauer
Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.
{"title":"Evaluation of Low-k Integration Integrity Using Shear Testing on Sub-30 Micron Micro-Cu Pillars","authors":"Tae-Kyu Lee, Greg Baty, O. Ahmed, P. Su, Bernard Glasauer","doi":"10.1109/ECTC32696.2021.00139","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00139","url":null,"abstract":"Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114123744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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