Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00079
K. Shie, Pin-Syuan He, Yu-Hao Kuo, J. Ong, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen
The temperature for hybrid bonding is favorably to be lower than 250 °C, and thus nanotwinned Cu (nt-Cu) and low curing temperature dielectrics were combined to achieve that. To facilitate the fabrication of highly (111)-oriented surface of nt-Cu, Cu first process was chosen. In contrast to damascene Cu process, Cu first process changed the sequences of dielectric coating and Cu electroplating processes. In this study, patterned nt-Cu was plated first, and then dielectric was added in the process before or after chemical mechanical planarization (CMP). Low-temperature polyimide (PI) and non-conductive paste (NCP) were used to conduct two kinds of processes of hybrid bonding. If PI was coated and partially cured on a patterned wafer before CMP, co-planarization of nt-Cu/PI should be done afterwards to fabricate Cu/PI structure. The Cu/PI hybrid bonding can be achieved at 200 °C for 30 min. If a patterned wafer was planarized firstly, NCP was dropped on the samples and bonding process can be carried out at 180 °C for 2 h. This process was denoted as Cu + NCP hybrid bonding. The above two methods of hybrid bonding could be achieved under 250 °C, and might be the solutions for hybrid bonding technology with low thermal budget.
{"title":"Hybrid Bonding of Nanotwinned Copper/organic Dielectrics with Low Thermal Budget","authors":"K. Shie, Pin-Syuan He, Yu-Hao Kuo, J. Ong, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen","doi":"10.1109/ECTC32696.2021.00079","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00079","url":null,"abstract":"The temperature for hybrid bonding is favorably to be lower than 250 °C, and thus nanotwinned Cu (nt-Cu) and low curing temperature dielectrics were combined to achieve that. To facilitate the fabrication of highly (111)-oriented surface of nt-Cu, Cu first process was chosen. In contrast to damascene Cu process, Cu first process changed the sequences of dielectric coating and Cu electroplating processes. In this study, patterned nt-Cu was plated first, and then dielectric was added in the process before or after chemical mechanical planarization (CMP). Low-temperature polyimide (PI) and non-conductive paste (NCP) were used to conduct two kinds of processes of hybrid bonding. If PI was coated and partially cured on a patterned wafer before CMP, co-planarization of nt-Cu/PI should be done afterwards to fabricate Cu/PI structure. The Cu/PI hybrid bonding can be achieved at 200 °C for 30 min. If a patterned wafer was planarized firstly, NCP was dropped on the samples and bonding process can be carried out at 180 °C for 2 h. This process was denoted as Cu + NCP hybrid bonding. The above two methods of hybrid bonding could be achieved under 250 °C, and might be the solutions for hybrid bonding technology with low thermal budget.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00283
S. Neermann, J. Franke, M. Sippel, K. Lomakin, G. Gold
In recent years, the focus of research and industry in the field of printed electronics has been primarily on challenges relating to process improvements like resolution and process stability or material improvements. In contrast, environmental simulation on-tests such as temperature shock tests or humidity-heat tests and their effects on electrical and mechanical properties as well as the high frequency (HF) properties of printed structures have hardly been considered so far. However, such environmental requirements for electronic components are particularly important for reliable use in all areas of printed electronics. In this paper, environmental simulation tests on printed conductive structures were therefore carried out and their effects on the electrical conductivity and microwave frequency properties were measured, analyzed and evaluated. The common environmental simulation test methods as well as their purpose and implementation variants are examined in detail for this purpose. Based on these fundamentals, first of all the selected substrate material RO4350B is printed with a conductive silver paste according to microwave frequency technical specifications using a dispensing printing process and sintered according to the manufacturers specifications. The substrate material has a relative permittivity $varepsilon_{r}=3.48$ on which the geometry of the additively produced structures depends. To achieve the required characteristic impedance $Z_{L}approx 50 Omega$, a width of $1080 mumathrm{m}$ must be reached. The printed samples are then subjected to various environmental simulation tests and examined using various measurement procedures. For the long-term reliability tests, the temperature shock test between −40°C and 140 °C for 1000 cycles, the humidity-heat test with 85°C and 85% relative humidity for 1000 h and the vibration test were selected according to DIN EN 60068. The evaluation methods are to focus on the effects of the environmental simulation tests on electrical and mechanical properties as well as the influence on the high-frequency properties. The conductivity is measured by means of four-wire measurement. A comparison was made of the electrical conductivity in the sintered state, during the reliability tests and at the end of the tests. The samples in the thermal shock test were examined after 250 cycles, 500 cycles, 750 cycles and 1000 cycles to make premature failures of the samples visible. In the moisture-heat test the samples were taken and examined after 500 h and 1000 h. The detection of defects and cracks is carried out using optical control. To determine the high-frequency characteristics, a 2-port measurement of the S-parameters up to 12 GHz was performed. The insertion loss without impact from the transitions was determined using a multi-line method. It can be summarized that the reliability tests have no significant influence on the insertion loss of the printed samples compared to the sintered references. While
近年来，印刷电子领域的研究和工业重点主要集中在与分辨率和工艺稳定性或材料改进等工艺改进有关的挑战上。相比之下，环境模拟试验，如温度冲击试验或湿热试验，以及它们对印刷结构的电气和机械性能以及高频(HF)性能的影响迄今几乎没有考虑。然而，这种对电子元件的环境要求对于在印刷电子的所有领域中可靠使用尤为重要。因此，本文对印刷导电结构进行了环境模拟试验，并对其电导率和微波频率性能的影响进行了测量、分析和评价。为此，详细研究了常见的环境模拟测试方法及其目的和实现变体。基于这些基本原理，首先选用基板材料ro450b，根据微波频率技术规范，采用点胶印刷工艺，用导电银浆进行印刷，并按照厂家规格进行烧结。所述衬底材料具有相对介电常数$varepsilon_{r}=3.48$，所述增材制造的结构的几何形状取决于该介电常数。为了达到所需的特性阻抗$Z_{L}approx 50 Omega$，必须达到$1080 mumathrm{m}$的宽度。然后将打印的样品进行各种环境模拟测试，并使用各种测量程序进行检查。对于长期可靠性试验，温度冲击试验在−40℃～ 140℃之间进行1000次循环，湿热试验在85℃～ 85℃之间进行% relative humidity for 1000 h and the vibration test were selected according to DIN EN 60068. The evaluation methods are to focus on the effects of the environmental simulation tests on electrical and mechanical properties as well as the influence on the high-frequency properties. The conductivity is measured by means of four-wire measurement. A comparison was made of the electrical conductivity in the sintered state, during the reliability tests and at the end of the tests. The samples in the thermal shock test were examined after 250 cycles, 500 cycles, 750 cycles and 1000 cycles to make premature failures of the samples visible. In the moisture-heat test the samples were taken and examined after 500 h and 1000 h. The detection of defects and cracks is carried out using optical control. To determine the high-frequency characteristics, a 2-port measurement of the S-parameters up to 12 GHz was performed. The insertion loss without impact from the transitions was determined using a multi-line method. It can be summarized that the reliability tests have no significant influence on the insertion loss of the printed samples compared to the sintered references. While, especially in the temperature shock test, a change in electrical conductivity and isolated crack formations can be measured. This change regarding conductivity is due to the post-sintering effect caused by temperature exposure during reliability studies and suggests that the sintering time and method recommended by the manufacturer must be adjusted.
{"title":"Reliability of Printed Microwave Electronics","authors":"S. Neermann, J. Franke, M. Sippel, K. Lomakin, G. Gold","doi":"10.1109/ECTC32696.2021.00283","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00283","url":null,"abstract":"In recent years, the focus of research and industry in the field of printed electronics has been primarily on challenges relating to process improvements like resolution and process stability or material improvements. In contrast, environmental simulation on-tests such as temperature shock tests or humidity-heat tests and their effects on electrical and mechanical properties as well as the high frequency (HF) properties of printed structures have hardly been considered so far. However, such environmental requirements for electronic components are particularly important for reliable use in all areas of printed electronics. In this paper, environmental simulation tests on printed conductive structures were therefore carried out and their effects on the electrical conductivity and microwave frequency properties were measured, analyzed and evaluated. The common environmental simulation test methods as well as their purpose and implementation variants are examined in detail for this purpose. Based on these fundamentals, first of all the selected substrate material RO4350B is printed with a conductive silver paste according to microwave frequency technical specifications using a dispensing printing process and sintered according to the manufacturers specifications. The substrate material has a relative permittivity $varepsilon_{r}=3.48$ on which the geometry of the additively produced structures depends. To achieve the required characteristic impedance $Z_{L}approx 50 Omega$, a width of $1080 mumathrm{m}$ must be reached. The printed samples are then subjected to various environmental simulation tests and examined using various measurement procedures. For the long-term reliability tests, the temperature shock test between −40°C and 140 °C for 1000 cycles, the humidity-heat test with 85°C and 85% relative humidity for 1000 h and the vibration test were selected according to DIN EN 60068. The evaluation methods are to focus on the effects of the environmental simulation tests on electrical and mechanical properties as well as the influence on the high-frequency properties. The conductivity is measured by means of four-wire measurement. A comparison was made of the electrical conductivity in the sintered state, during the reliability tests and at the end of the tests. The samples in the thermal shock test were examined after 250 cycles, 500 cycles, 750 cycles and 1000 cycles to make premature failures of the samples visible. In the moisture-heat test the samples were taken and examined after 500 h and 1000 h. The detection of defects and cracks is carried out using optical control. To determine the high-frequency characteristics, a 2-port measurement of the S-parameters up to 12 GHz was performed. The insertion loss without impact from the transitions was determined using a multi-line method. It can be summarized that the reliability tests have no significant influence on the insertion loss of the printed samples compared to the sintered references. While","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00350
E. Passalacqua, C. Laprais, M. Bylund, Q. Li, V. Marknäs, R. Andersson, A. Saleem, V. Desmaris
In this paper, we propose the introduction of vertically aligned carbon nanofibers (CNF) directly grown on the bonding pad by chemical vapor deposition at CMOS compatible temperatures as a solution to reinforce and confine the solder joint between two chips bonded by solder. This concept potentially enables the reduction of pitches and size of the solder interconnects. The solder joints are realized by thermal compression bonding technique and the assemblies are characterized by means of electrical measurements of daisy chains and kelvin structures formed by the connection of the two chips. Flip chip interconnects based on two solder composite solutions (CNFs/SnAg and CNFs/SAC305) are analyzed in terms of electrical resistance, and different growth conditions for the CNFs and a post-growth treatment have been tested. The addition of the carbon nanofibers to the solder led to an additional resistance lower than 10% of the total resistance, while possibly improving the reliability of the joint.
{"title":"Flip chip interconnects based on carbon nanofibers-solder composites","authors":"E. Passalacqua, C. Laprais, M. Bylund, Q. Li, V. Marknäs, R. Andersson, A. Saleem, V. Desmaris","doi":"10.1109/ECTC32696.2021.00350","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00350","url":null,"abstract":"In this paper, we propose the introduction of vertically aligned carbon nanofibers (CNF) directly grown on the bonding pad by chemical vapor deposition at CMOS compatible temperatures as a solution to reinforce and confine the solder joint between two chips bonded by solder. This concept potentially enables the reduction of pitches and size of the solder interconnects. The solder joints are realized by thermal compression bonding technique and the assemblies are characterized by means of electrical measurements of daisy chains and kelvin structures formed by the connection of the two chips. Flip chip interconnects based on two solder composite solutions (CNFs/SnAg and CNFs/SAC305) are analyzed in terms of electrical resistance, and different growth conditions for the CNFs and a post-growth treatment have been tested. The addition of the carbon nanofibers to the solder led to an additional resistance lower than 10% of the total resistance, while possibly improving the reliability of the joint.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126299253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00263
K. Pan, Jiefeng Xu, Yang Lai, Seungbae Park, C. Okoro, Dhananjay Joshi, S. Pollard
Glass interposers have attracted much interest from academia and industry because of the outstanding material properties of glass. However, the thermal mismatch between a copper via and glass causes reliability issues, such as glass and TGV cracking, copper via protrusion, and copper via sliding and delamination. This study investigated the copper and glass (Corning® HPFS® Fused Silica) interaction in TGV during thermal cycling. Optical profilometry was used to measure the copper via protrusion during thermal cycling. The TGV was heated up from room temperature (RT) 23°C to 400°C and then cooled to RT. An irreversible copper protrusion height was recorded at different temperatures. Furthermore, in-plane deformation of the glass caused by thermal mismatch is another reliability concern. Thus, two-dimensional digital image correlation (2D DIC) was applied to measure the in-plane deformation of the HPFS glass near the TGV during thermal cycling. The TGV sample was heated to 400°C from RT by a hotplate, and then the sample was cooled to RT using liquid nitrogen. The in-plane displacement of HPFS glass reached its maximum around 250°C, then it started to decrease because of the copper protrusion and copper material change at elevated temperatures.
{"title":"Investigation of Copper and Glass Interaction in Through Glass Via (TGV) During Thermal Cycling","authors":"K. Pan, Jiefeng Xu, Yang Lai, Seungbae Park, C. Okoro, Dhananjay Joshi, S. Pollard","doi":"10.1109/ECTC32696.2021.00263","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00263","url":null,"abstract":"Glass interposers have attracted much interest from academia and industry because of the outstanding material properties of glass. However, the thermal mismatch between a copper via and glass causes reliability issues, such as glass and TGV cracking, copper via protrusion, and copper via sliding and delamination. This study investigated the copper and glass (Corning® HPFS® Fused Silica) interaction in TGV during thermal cycling. Optical profilometry was used to measure the copper via protrusion during thermal cycling. The TGV was heated up from room temperature (RT) 23°C to 400°C and then cooled to RT. An irreversible copper protrusion height was recorded at different temperatures. Furthermore, in-plane deformation of the glass caused by thermal mismatch is another reliability concern. Thus, two-dimensional digital image correlation (2D DIC) was applied to measure the in-plane deformation of the HPFS glass near the TGV during thermal cycling. The TGV sample was heated to 400°C from RT by a hotplate, and then the sample was cooled to RT using liquid nitrogen. The in-plane displacement of HPFS glass reached its maximum around 250°C, then it started to decrease because of the copper protrusion and copper material change at elevated temperatures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121110557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00355
Guangqi Ouyang, G. Ezhilarasu, Henry Sun, Haoxiang Ren, Yu-Tao Yang, S. Iyer
In this work, flexible corrugated interconnection and Fan-Out Wafer-Level packaging platform called FlexTrate™ is used to fabricate a thin film, flexible, magnetic resonant wireless recharging module for charging commercial Li-ion battery at an output of 3.3 V constant voltage. A power management IC (LDO bare die LDBL20) for voltage regulation, a fullwave bridge rectifier, a Si-DT capacitor dies for antenna matching. The coil antenna is also fabricated on the PDMS substrate using standard BEOL Cu metallization. The designed power module can deliver 3.9 mW regulated power.
{"title":"A Flexible Power Module for Wearable Medical Devices with Wireless Recharging using Corrugated Flexible Coils","authors":"Guangqi Ouyang, G. Ezhilarasu, Henry Sun, Haoxiang Ren, Yu-Tao Yang, S. Iyer","doi":"10.1109/ECTC32696.2021.00355","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00355","url":null,"abstract":"In this work, flexible corrugated interconnection and Fan-Out Wafer-Level packaging platform called FlexTrate™ is used to fabricate a thin film, flexible, magnetic resonant wireless recharging module for charging commercial Li-ion battery at an output of 3.3 V constant voltage. A power management IC (LDO bare die LDBL20) for voltage regulation, a fullwave bridge rectifier, a Si-DT capacitor dies for antenna matching. The coil antenna is also fabricated on the PDMS substrate using standard BEOL Cu metallization. The designed power module can deliver 3.9 mW regulated power.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121226847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00081
C. Hsiao, H. Fu, C. Chiang, O. Lee, Tsung-Yu Ou Yang, Hsiang-Hung Chang
In this study, the wafer-level nanotwinned copper (nt-Cu) and BCB adhesive hybrid bonding is proposed. The (111) oriented nt-Cu and BCB adhesive are used for electrical interconnection and mechanical enhancement, respectively. Nanotwinned copper direct bonding, BCB adhesive bonding, nt-Cu and BCB adhesive hybrid bonding are investigated. In nt-Cu direct bonding, the highly (111) oriented surface ratio of nt-Cu is 97% by increasing plating current density, the columnar grain size and (111) oriented surface ratio are identified by Focused Ion Beam (FIB) and Electron Back Scatter Diffraction (EBSD). The surface roughness of nt-Cu is reduced to 0.72 nm after Chemical Mechanical Polishing (CMP) and nt-Cu to nt-Cu direct bonding without large bonding voids is achieved at 250 °C for 1 h. In BCB adhesive bonding, BCB to BCB could be well bonded at 250 °C. There are no samples peeling after dicing and the average shear strength is larger than 24 MPa. Currently, the surface topography and bonding result of nt-Cu and BCB hybrid structure are improved after tuning BCB curing and fly cutting condition.
{"title":"Feasibility Study of Nanotwinned Copper and Adhesive Hybrid Bonding for Heterogeneous Integration","authors":"C. Hsiao, H. Fu, C. Chiang, O. Lee, Tsung-Yu Ou Yang, Hsiang-Hung Chang","doi":"10.1109/ECTC32696.2021.00081","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00081","url":null,"abstract":"In this study, the wafer-level nanotwinned copper (nt-Cu) and BCB adhesive hybrid bonding is proposed. The (111) oriented nt-Cu and BCB adhesive are used for electrical interconnection and mechanical enhancement, respectively. Nanotwinned copper direct bonding, BCB adhesive bonding, nt-Cu and BCB adhesive hybrid bonding are investigated. In nt-Cu direct bonding, the highly (111) oriented surface ratio of nt-Cu is 97% by increasing plating current density, the columnar grain size and (111) oriented surface ratio are identified by Focused Ion Beam (FIB) and Electron Back Scatter Diffraction (EBSD). The surface roughness of nt-Cu is reduced to 0.72 nm after Chemical Mechanical Polishing (CMP) and nt-Cu to nt-Cu direct bonding without large bonding voids is achieved at 250 °C for 1 h. In BCB adhesive bonding, BCB to BCB could be well bonded at 250 °C. There are no samples peeling after dicing and the average shear strength is larger than 24 MPa. Currently, the surface topography and bonding result of nt-Cu and BCB hybrid structure are improved after tuning BCB curing and fly cutting condition.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121488257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00039
F. Herrault, J. Wong, I. Ramos, H. Tai, M. King
The Metal Embedded Chiplet Assembly for Microwave Integrated Circuits (MECAMIC) technology utilizes RF GaN transistor chiplets integrated into passive interposer wafers using a metal electroplating embedding approach. Chiplets in Wafers (CiW) enable high level of integration between the transistor chiplets and the packaging circuitry, resulting in high RF performance. In this paper, we present the detailed process flow, the development of a MECAMIC Process Design Kit (PDK) for mm-wave RF Integrated Circuits (ICs), and its application to the design, simulation, fabrication and measurements of heterogeneously-integrated multi-stage W-band Low Noise Amplifiers (LNAs) using state-of-the-art mm-wave GaN transistor chiplets and low-cost silicon interposer packaging with 16 dB gain and 4dB noise figure at 77 GHz.
{"title":"Chiplets in Wafers (CiW) - Process Design Kit and Demonstration of High-Frequency Circuits with GaN Chiplets in Silicon Interposers","authors":"F. Herrault, J. Wong, I. Ramos, H. Tai, M. King","doi":"10.1109/ECTC32696.2021.00039","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00039","url":null,"abstract":"The Metal Embedded Chiplet Assembly for Microwave Integrated Circuits (MECAMIC) technology utilizes RF GaN transistor chiplets integrated into passive interposer wafers using a metal electroplating embedding approach. Chiplets in Wafers (CiW) enable high level of integration between the transistor chiplets and the packaging circuitry, resulting in high RF performance. In this paper, we present the detailed process flow, the development of a MECAMIC Process Design Kit (PDK) for mm-wave RF Integrated Circuits (ICs), and its application to the design, simulation, fabrication and measurements of heterogeneously-integrated multi-stage W-band Low Noise Amplifiers (LNAs) using state-of-the-art mm-wave GaN transistor chiplets and low-cost silicon interposer packaging with 16 dB gain and 4dB noise figure at 77 GHz.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131469294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00298
K. Murayama, Mitsuhiro Aizawa, K. Oi
In recent years, global warming prevention and reduction of energy consumption are increasingly required. And technical point of view, low stress bonding is required. A low temperature bonding using Sn-Bi solder is candidate technique to solve these problems. In this report, improving the reliability of electro-migration at flip chip interconnect in Sn-Bi solder, which is a low-temperature solder, are focused. A combination of six types of Sn-Bi solder and surface finish of interposer pad were studied, these are, combination of Sn30wt.%Bi (Sn30Bi) solder, Sn57wt.%Bi (Sn57Bi) solder, electroless Ni/Au on Cu pad and Ni/Pd/ Au on Cu pad. The effects of Bi concentration, trace element and inter-metallic compounds formation on electromigration resistivity were evaluated. The current density of 40 kA/cm2 was applied at 125 degrees C. Analysis of the microstructure and crystal orientation of the interconnected bumps were performed in all combinations by electron backscatter diffraction and electron probe microanalyzer. Mean time to failure of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick) and that of Sn30Bi/NiPdAu were19, 141 and 600 hours, respectively. And maximum resistance increases from initial of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick), Sn30Bi/NiPdAu were 60.6%, 19.5%, 13.2% after 2500 hours. Reducing the total amount of Au and Pd atoms in the solder can delay increase of resistance after current stressing. In cases of NiAu(thick) and NiAu(thin) pads, two types of failure mode were observed after current stressing. One was growth of large (Cu, Ni)6Sn5 with thick Ni(P rich) layer. The other was the mode in which (Cu, Ni) 6Sn5 hardly grow and unreacted Sn layer remains. In case of c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad to the solder was accelerated. On the other hand, in the case of NiPdAu pad, only one failure mode was observed after current stressing. It is a mode in which the unreacted Sn layer remains. Even if c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad was not observed. Focusing on the intermetallic compounds (IMCs) formed on the interposer pad after 10% resistance change, in cases of NiAu(thick) and NiAu(thin) pads, un-uniform and needle-type (Cu, Ni) 6Sn5 were formed. Large Ni diffusion from their grain boundary into IMCs were observed after current stressing. On the other hand, in the case of NiPdAu pad, thin (Ni, Cu)3Sn4 and uniform and dense scallop-type (Cu, Ni)6Sn5 were formed after 10% resistance change. They were still stabled after current stressing. The significant increase in resistance in the early stage is influenced by Bi concentration in solder. And Au atoms play a role of accelerating diffusion and increase in resistance at early stage on electro-migration test. Dense scallop-type (Cu, Ni)6Sn5 layer on Ni pad showed as an effective barrier diffusion of Cu or Ni. It was found that if a uniform and dense IMCs were formed on the interpose
{"title":"Effect of crystal anisotropy and IMCs on electromigration resistivity of low temperature flip chip interconnect","authors":"K. Murayama, Mitsuhiro Aizawa, K. Oi","doi":"10.1109/ECTC32696.2021.00298","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00298","url":null,"abstract":"In recent years, global warming prevention and reduction of energy consumption are increasingly required. And technical point of view, low stress bonding is required. A low temperature bonding using Sn-Bi solder is candidate technique to solve these problems. In this report, improving the reliability of electro-migration at flip chip interconnect in Sn-Bi solder, which is a low-temperature solder, are focused. A combination of six types of Sn-Bi solder and surface finish of interposer pad were studied, these are, combination of Sn30wt.%Bi (Sn30Bi) solder, Sn57wt.%Bi (Sn57Bi) solder, electroless Ni/Au on Cu pad and Ni/Pd/ Au on Cu pad. The effects of Bi concentration, trace element and inter-metallic compounds formation on electromigration resistivity were evaluated. The current density of 40 kA/cm2 was applied at 125 degrees C. Analysis of the microstructure and crystal orientation of the interconnected bumps were performed in all combinations by electron backscatter diffraction and electron probe microanalyzer. Mean time to failure of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick) and that of Sn30Bi/NiPdAu were19, 141 and 600 hours, respectively. And maximum resistance increases from initial of Sn57Bi/NiAu(thick), that of Sn30Bi/NiAu(thick), Sn30Bi/NiPdAu were 60.6%, 19.5%, 13.2% after 2500 hours. Reducing the total amount of Au and Pd atoms in the solder can delay increase of resistance after current stressing. In cases of NiAu(thick) and NiAu(thin) pads, two types of failure mode were observed after current stressing. One was growth of large (Cu, Ni)6Sn5 with thick Ni(P rich) layer. The other was the mode in which (Cu, Ni) 6Sn5 hardly grow and unreacted Sn layer remains. In case of c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad to the solder was accelerated. On the other hand, in the case of NiPdAu pad, only one failure mode was observed after current stressing. It is a mode in which the unreacted Sn layer remains. Even if c-axis of the beta-Sn grain aligned with the electron flow, Ni diffusion from Ni pad was not observed. Focusing on the intermetallic compounds (IMCs) formed on the interposer pad after 10% resistance change, in cases of NiAu(thick) and NiAu(thin) pads, un-uniform and needle-type (Cu, Ni) 6Sn5 were formed. Large Ni diffusion from their grain boundary into IMCs were observed after current stressing. On the other hand, in the case of NiPdAu pad, thin (Ni, Cu)3Sn4 and uniform and dense scallop-type (Cu, Ni)6Sn5 were formed after 10% resistance change. They were still stabled after current stressing. The significant increase in resistance in the early stage is influenced by Bi concentration in solder. And Au atoms play a role of accelerating diffusion and increase in resistance at early stage on electro-migration test. Dense scallop-type (Cu, Ni)6Sn5 layer on Ni pad showed as an effective barrier diffusion of Cu or Ni. It was found that if a uniform and dense IMCs were formed on the interpose","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121781348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00149
A. Schiffmacher, D. Strahringer, Shreyas Malasani, J. Wilde, Carsten Kempiak, A. Lindemann
Within the scope of this work three in-situ degradation monitoring methods are presented. The methods are suitable for the detection of degradations in power electronic modules during active power cycling test without interrupting the test itself. A comparison of the results is illustrated by conducting all three techniques during the lifetime testing of a power electronic module at the same time. In sum, electrical, electrothermal, thermal and thermomechanical parameters were evaluated. From the observations, we conclude that the primary failure mechanism of a novel die-top interconnect technology for power modules is the crack propagation in the Al-metallisation of the semiconductor. Cross-sectional images of the samples were prepared to confirm the previously given evidence of the failure. Furthermore a lifetime model was established for this assembly technology. Finally, a comparison of the advantages and limitations of the conducted degradation monitoring techniques will be presented.
{"title":"In Situ Degradation Monitoring Methods during Lifetime Testing of Power Electronic Modules","authors":"A. Schiffmacher, D. Strahringer, Shreyas Malasani, J. Wilde, Carsten Kempiak, A. Lindemann","doi":"10.1109/ECTC32696.2021.00149","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00149","url":null,"abstract":"Within the scope of this work three in-situ degradation monitoring methods are presented. The methods are suitable for the detection of degradations in power electronic modules during active power cycling test without interrupting the test itself. A comparison of the results is illustrated by conducting all three techniques during the lifetime testing of a power electronic module at the same time. In sum, electrical, electrothermal, thermal and thermomechanical parameters were evaluated. From the observations, we conclude that the primary failure mechanism of a novel die-top interconnect technology for power modules is the crack propagation in the Al-metallisation of the semiconductor. Cross-sectional images of the samples were prepared to confirm the previously given evidence of the failure. Furthermore a lifetime model was established for this assembly technology. Finally, a comparison of the advantages and limitations of the conducted degradation monitoring techniques will be presented.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133223975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00069
F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann
In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5 mumathrm{m}$ edge length bumps and fine pitches less than $8 mumathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $mu mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.
{"title":"Room Temperature KlettWelding Interconnect Technology for High Performance CMOS Logic","authors":"F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann","doi":"10.1109/ECTC32696.2021.00069","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00069","url":null,"abstract":"In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5 mumathrm{m}$ edge length bumps and fine pitches less than $8 mumathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $mu mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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