Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00333
Huaneng Su, Cheng-Che Tsou, Auger Horng
In this article, the polyimide formation at high pressure for advanced assembly technology is reported for the first time. Polyimides are formed in a pneumatic oven for evaluation of voids and cycle times. For comparison and production evaluation, the polyimides were fabricated by curing photo-definable aqueous developers with different recipes and batches of wafers, respectively. For the recipes in the pneumatic oven, instead of the multistep thermal cycles, the ramp-up time and curing time could be reduced drastically to enhance the production throughput. Furthermore, as shown in optical microscope (OM) results, no void was found for the pneumatic oven samples, and lots of voids were detected for the normal oven ones. This innovation enables manufacturers to reduce 36% of process cycle time. The polyimide cyclization rate was estimated from the signal strength ratio by using Fourier-transform infrared spectroscopy (FTIR). The thermal stability by using a thermogravimetric analyzer (TGA) and the glass transition temperature by thermomechanical analysis (TMA) was analyzed to clarify the properties of the polyimides for these recipes. The results show no obvious difference is observed between pneumatic cured polyimides and normal-oven cured ones. Mechanical strength and outgassing were enhanced for the pneumatic-oven samples and no oxidation was found after pneumatic curing due to the well-controlled oxygen content of the oven.
{"title":"Effect of Pneumatic Curing on Cycle Time Reduction and Void Suppression of Polyimide Wafer Coating","authors":"Huaneng Su, Cheng-Che Tsou, Auger Horng","doi":"10.1109/ECTC32696.2021.00333","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00333","url":null,"abstract":"In this article, the polyimide formation at high pressure for advanced assembly technology is reported for the first time. Polyimides are formed in a pneumatic oven for evaluation of voids and cycle times. For comparison and production evaluation, the polyimides were fabricated by curing photo-definable aqueous developers with different recipes and batches of wafers, respectively. For the recipes in the pneumatic oven, instead of the multistep thermal cycles, the ramp-up time and curing time could be reduced drastically to enhance the production throughput. Furthermore, as shown in optical microscope (OM) results, no void was found for the pneumatic oven samples, and lots of voids were detected for the normal oven ones. This innovation enables manufacturers to reduce 36% of process cycle time. The polyimide cyclization rate was estimated from the signal strength ratio by using Fourier-transform infrared spectroscopy (FTIR). The thermal stability by using a thermogravimetric analyzer (TGA) and the glass transition temperature by thermomechanical analysis (TMA) was analyzed to clarify the properties of the polyimides for these recipes. The results show no obvious difference is observed between pneumatic cured polyimides and normal-oven cured ones. Mechanical strength and outgassing were enhanced for the pneumatic-oven samples and no oxidation was found after pneumatic curing due to the well-controlled oxygen content of the oven.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00300
Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen
Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.
{"title":"Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters","authors":"Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen","doi":"10.1109/ECTC32696.2021.00300","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00300","url":null,"abstract":"Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126147743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00050
Lim Teck Guan, Eva Wai Leong Ching, Jong Ming Ching, Loh Woon Leng, D. Wee, S. Bhattacharya
A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC (PIC) are described here. These two platforms are capable to support high-speed integration and scalable design of the next generation Optical Engine. The integration of the PIC on the FOWLP is achieved by a simple novel solution. An additional section of the Si substrate is designed at the end of the PIC to protect the optical I/Os during the FOWLP embedding process. For the Through Si-Interposer, besides providing the EIC and PIC, it include the passive alignment feature for the fibre to the PIC assembly.
{"title":"FOWLP and Si-Interposer for High-Speed Photonic Packaging","authors":"Lim Teck Guan, Eva Wai Leong Ching, Jong Ming Ching, Loh Woon Leng, D. Wee, S. Bhattacharya","doi":"10.1109/ECTC32696.2021.00050","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00050","url":null,"abstract":"A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC (PIC) are described here. These two platforms are capable to support high-speed integration and scalable design of the next generation Optical Engine. The integration of the PIC on the FOWLP is achieved by a simple novel solution. An additional section of the Si substrate is designed at the end of the PIC to protect the optical I/Os during the FOWLP embedding process. For the Through Si-Interposer, besides providing the EIC and PIC, it include the passive alignment feature for the fibre to the PIC assembly.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129482207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00277
Juno Kim, K. Lim, S. Hahn, Mingu Lee, D. Rhee
A new characterization method for interfacial adhesion between die to die hybrid bonding interface at chip level is developed to evaluate and analyze the adhesion strength. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3DIC Heterogeneous. However, there is no proven methodology or guideline to characterize the die level hybrid bonding strength which is very much dependent on the surface treatment process parameters, the physical and chemical characteristics of the bonding interfaces and particles and so on. To improve the quality and reliability of the die level hybrid bonding interface, it is crucial to identify well defined characterization methodology, especially for the thin die case which is no more applicable by using conventionally used die shear test method. In this paper, the authors developed novel characterization method of die level hybrid bonded interface strength by applying the single cantilever method using thin die with a thickness of $100 mumathrm{m}$. To optimize the test specimen design and testing condition, the finite element analysis (FEA) is performed. Using the optimized methodology, a series of experiments for characterizing the die to die bonding strength are conducted at various load-point lengths, bonding lengths and annealing temperatures. Based on the FEA and experimental data, the limitations and prospects of the developed characterization method are discussed in detail.
{"title":"Novel Characterization Method of Chip Level Hybrid Bonding Strength","authors":"Juno Kim, K. Lim, S. Hahn, Mingu Lee, D. Rhee","doi":"10.1109/ECTC32696.2021.00277","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00277","url":null,"abstract":"A new characterization method for interfacial adhesion between die to die hybrid bonding interface at chip level is developed to evaluate and analyze the adhesion strength. Die to wafer or die to die hybrid bonding and stacking is very promising scheme for the next 2.5D and 3DIC Heterogeneous. However, there is no proven methodology or guideline to characterize the die level hybrid bonding strength which is very much dependent on the surface treatment process parameters, the physical and chemical characteristics of the bonding interfaces and particles and so on. To improve the quality and reliability of the die level hybrid bonding interface, it is crucial to identify well defined characterization methodology, especially for the thin die case which is no more applicable by using conventionally used die shear test method. In this paper, the authors developed novel characterization method of die level hybrid bonded interface strength by applying the single cantilever method using thin die with a thickness of $100 mumathrm{m}$. To optimize the test specimen design and testing condition, the finite element analysis (FEA) is performed. Using the optimized methodology, a series of experiments for characterizing the die to die bonding strength are conducted at various load-point lengths, bonding lengths and annealing temperatures. Based on the FEA and experimental data, the limitations and prospects of the developed characterization method are discussed in detail.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128509414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00036
D. Hu, E. Chen, J. Lee, Chia-Peng Sun, Chih Chung Hsu
In this work, a new integrated substrate structure “2.2D” is demonstrated. 2.2D substrate is a true die last solution. This solution used thin film RDL directly bonded to the substrate. This simplifies the 2.5D structure and further reduces the cost and improves the product cycle time. In this work, the 2.2D test vehicle is demonstrated with two metal layers of thin film that is bonded to a ceramic substrate. Serpentine lines run from thin film RDL to the substrate were evaluated. The process developed in this study demonstrates good registration between thin film RDL and substrate. The 2.2D TV demonstrates good warpage behavior up to the solder reflow temperature. The 2.2D structure shows good potential to be used for high performance computing substrate.
{"title":"2.2D Die last Integrated Substrate for High Performance Applications","authors":"D. Hu, E. Chen, J. Lee, Chia-Peng Sun, Chih Chung Hsu","doi":"10.1109/ECTC32696.2021.00036","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00036","url":null,"abstract":"In this work, a new integrated substrate structure “2.2D” is demonstrated. 2.2D substrate is a true die last solution. This solution used thin film RDL directly bonded to the substrate. This simplifies the 2.5D structure and further reduces the cost and improves the product cycle time. In this work, the 2.2D test vehicle is demonstrated with two metal layers of thin film that is bonded to a ceramic substrate. Serpentine lines run from thin film RDL to the substrate were evaluated. The process developed in this study demonstrates good registration between thin film RDL and substrate. The 2.2D TV demonstrates good warpage behavior up to the solder reflow temperature. The 2.2D structure shows good potential to be used for high performance computing substrate.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"2001 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00359
E. Ben Romdhane, P. Roumanille, A. Guédon-Gracia, S. Pin, P. Nguyen, H. Frémont
The microstructural analysis of as-reflowed SAC305 solder joints showed a highly textured microstructure. During thermal cycling tests, the as-solidified microstructure gradually transformed into a less textured structure with a high population of misoriented grain boundaries through a recrystallization process. Ag3Sn IMCs coalescence is also another strong phenomenon of lead-free solder microstructure evolution since the bigger and the more spaced they are, the less dislocation pinning can prevent recrystallization from occurring. The main observation is that recrystallization accompanied by Ag3Sn IMCs coalescence are preliminary leading to intergranular propagation in the high strain regions. This work presents the Sn3.0Ag0.5Cu (SAC305) solder joints microstructural evolution at different thermal cycling levels. Electron Back Scattered Diffraction (EBSD) analysis was conducted to assess the SAC305 microstructure corresponding to a specific number of thermal cycles. Microstructural properties as $beta$-Sn grain size and crystallographic orientation, grain boundary angles and the size of Ag3Sn intermetallic compounds (IMC) are investigated to characterize the different stages of microstructural changes under thermal cycling. Results show that crack initiation in chip resistors solder joints starts very early and precedes recrystallization process. However, solder joint lifetime is controlled by recrystallization and Ag3Sn IMCs coalescence which are the most important phenomena leading to the intergranular crack propagation.
{"title":"Early microstructural indicators of crack initiation in lead-free solder joints under thermal cycling","authors":"E. Ben Romdhane, P. Roumanille, A. Guédon-Gracia, S. Pin, P. Nguyen, H. Frémont","doi":"10.1109/ECTC32696.2021.00359","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00359","url":null,"abstract":"The microstructural analysis of as-reflowed SAC305 solder joints showed a highly textured microstructure. During thermal cycling tests, the as-solidified microstructure gradually transformed into a less textured structure with a high population of misoriented grain boundaries through a recrystallization process. Ag3Sn IMCs coalescence is also another strong phenomenon of lead-free solder microstructure evolution since the bigger and the more spaced they are, the less dislocation pinning can prevent recrystallization from occurring. The main observation is that recrystallization accompanied by Ag3Sn IMCs coalescence are preliminary leading to intergranular propagation in the high strain regions. This work presents the Sn3.0Ag0.5Cu (SAC305) solder joints microstructural evolution at different thermal cycling levels. Electron Back Scattered Diffraction (EBSD) analysis was conducted to assess the SAC305 microstructure corresponding to a specific number of thermal cycles. Microstructural properties as $beta$-Sn grain size and crystallographic orientation, grain boundary angles and the size of Ag3Sn intermetallic compounds (IMC) are investigated to characterize the different stages of microstructural changes under thermal cycling. Results show that crack initiation in chip resistors solder joints starts very early and precedes recrystallization process. However, solder joint lifetime is controlled by recrystallization and Ag3Sn IMCs coalescence which are the most important phenomena leading to the intergranular crack propagation.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127397880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00313
Xiaowu Zhang, B. L. Lau, Yong Han, Haoran Chen, M. C. Jong, S. Lim, S. Lim, Xiaobai Wang, Y. Andriani, Songlin Liu
In this paper, we present the design and fabrication of a mold-1st FOWLP that seeks to solve potential warpage and reliability issues. We examined three different mold-1st FOWLP options that are designed and developed for this work. We have created viscoelastic constitutive models and parameters for both the dielectric materials and epoxy molding compounds (EMCs) which have been used for the design of FOWLP. Measurement of the volumetric cure shrinkage of EMCs has been done using a newly developed method. Advanced modelling capability on wafer warpage has been successfully established after full material characterization and the predicted wafer warpage results are verified with experimental results. Based on advanced modeling results, new design metrics for FOWLP process flow useful for the packaging industry have been developed. Calibrated micro-stress sensors, that were designed and fabricated internally, are used monitor stress during the FOWLP process. The experimental stress measurements have been used to validate the predictions of the advanced stress model. Finally, board level solder joint reliability has been designed, simulated and enhanced leading to the establishment of a successful life prediction model for FOWLP that will prove useful to the packaging industry.
{"title":"Addressing Warpage Issue and Reliability Challenge of Fan-out Wafer-Level Packaging (FOWLP)","authors":"Xiaowu Zhang, B. L. Lau, Yong Han, Haoran Chen, M. C. Jong, S. Lim, S. Lim, Xiaobai Wang, Y. Andriani, Songlin Liu","doi":"10.1109/ECTC32696.2021.00313","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00313","url":null,"abstract":"In this paper, we present the design and fabrication of a mold-1st FOWLP that seeks to solve potential warpage and reliability issues. We examined three different mold-1st FOWLP options that are designed and developed for this work. We have created viscoelastic constitutive models and parameters for both the dielectric materials and epoxy molding compounds (EMCs) which have been used for the design of FOWLP. Measurement of the volumetric cure shrinkage of EMCs has been done using a newly developed method. Advanced modelling capability on wafer warpage has been successfully established after full material characterization and the predicted wafer warpage results are verified with experimental results. Based on advanced modeling results, new design metrics for FOWLP process flow useful for the packaging industry have been developed. Calibrated micro-stress sensors, that were designed and fabricated internally, are used monitor stress during the FOWLP process. The experimental stress measurements have been used to validate the predictions of the advanced stress model. Finally, board level solder joint reliability has been designed, simulated and enhanced leading to the establishment of a successful life prediction model for FOWLP that will prove useful to the packaging industry.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00025
N. S. Chase, R. Irwin, Yu-Tao Yang, Haoxiang Ren, S. Iyer
With the ever-increasing complexity of wafer scale systems as well as higher computing power requirement, reliability of these systems have become a major point of concern. The wide range of organic and inorganic materials used results in large CTE mismatch and ultimately high thermomechanical stresses. Moreover, failure due to moisture ingress in harsh environments and challenges of developing novel encapsulations with high step coverage, high throughput and robust barrier properties is another issue that is receiving a lot of emphasis. To improve the performance of the wafer scale systems, we have developed silicon interconnect fabric (Si-IF) which is a heterogeneous integration platform that utilizes metal-metal thermocompression boding to integrate dielets on a Si wafer as substrate. We have shown the advantages of Si-IF compared to conventional platforms in terms of performance, power consumption and heat dissipation [2], [3]. Replacing solder joints with metal-metal joints and limited number of materials used in Si-IF, result in low thermomechanical stresses and elimination of intermetallic compound formation during operation and fabrication and thus, improving the reliability and lifetime of the system. Currently, we are developing a sophisticated wafer scale system where Si-IF is at the heart of the platform and is connected to a two-phase thermal management unit and power platform, moreover flexible connectors are used to make the connection between Si-IF and the outside world. In this wafer scale system, solder joints are used to make connections between Si-IF and power platform as well as flexible connectors, thus it is important to investigate stresses within the joints due to temperature variation and vibration. In this paper, we investigate use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale system. Finite element analysis (FEA) modeling was utilized to understand the change in the thermomechanical stresses arising during temperature cycling for a system with the buffer layer when compared to a system with no buffer layer as well as a system where PCB pieces are embedded in the buffer layer. We present the simulation results for temperature cycling of the Si-IF attached to a substrate for all three scenarios. Temperature was varied between 125°C and −40°C and the maximum Von Mises stresses in the solder joints were extracted. FEA results show that maximum stress level is significantly lower when an elastomer layer is used as a buffer layer and embedding the PCB pieces in the buffer layer further reduces the stress levels. Moreover, we investigated use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale systems. FEA simulations show the effectiveness of an elastomeric buffer layer in damping the random vibration. The analysis shows that addition of the elastomer to the system effectively damps the input random acceleration and consequently,
{"title":"Reliability Considerations for Wafer Scale Systems","authors":"N. S. Chase, R. Irwin, Yu-Tao Yang, Haoxiang Ren, S. Iyer","doi":"10.1109/ECTC32696.2021.00025","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00025","url":null,"abstract":"With the ever-increasing complexity of wafer scale systems as well as higher computing power requirement, reliability of these systems have become a major point of concern. The wide range of organic and inorganic materials used results in large CTE mismatch and ultimately high thermomechanical stresses. Moreover, failure due to moisture ingress in harsh environments and challenges of developing novel encapsulations with high step coverage, high throughput and robust barrier properties is another issue that is receiving a lot of emphasis. To improve the performance of the wafer scale systems, we have developed silicon interconnect fabric (Si-IF) which is a heterogeneous integration platform that utilizes metal-metal thermocompression boding to integrate dielets on a Si wafer as substrate. We have shown the advantages of Si-IF compared to conventional platforms in terms of performance, power consumption and heat dissipation [2], [3]. Replacing solder joints with metal-metal joints and limited number of materials used in Si-IF, result in low thermomechanical stresses and elimination of intermetallic compound formation during operation and fabrication and thus, improving the reliability and lifetime of the system. Currently, we are developing a sophisticated wafer scale system where Si-IF is at the heart of the platform and is connected to a two-phase thermal management unit and power platform, moreover flexible connectors are used to make the connection between Si-IF and the outside world. In this wafer scale system, solder joints are used to make connections between Si-IF and power platform as well as flexible connectors, thus it is important to investigate stresses within the joints due to temperature variation and vibration. In this paper, we investigate use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale system. Finite element analysis (FEA) modeling was utilized to understand the change in the thermomechanical stresses arising during temperature cycling for a system with the buffer layer when compared to a system with no buffer layer as well as a system where PCB pieces are embedded in the buffer layer. We present the simulation results for temperature cycling of the Si-IF attached to a substrate for all three scenarios. Temperature was varied between 125°C and −40°C and the maximum Von Mises stresses in the solder joints were extracted. FEA results show that maximum stress level is significantly lower when an elastomer layer is used as a buffer layer and embedding the PCB pieces in the buffer layer further reduces the stress levels. Moreover, we investigated use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale systems. FEA simulations show the effectiveness of an elastomeric buffer layer in damping the random vibration. The analysis shows that addition of the elastomer to the system effectively damps the input random acceleration and consequently, ","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127186188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00235
M. Han, Y. Shin, K. Lim, D. Rhee
In this study, a numerical methodology to predict package warpage considering viscoelasticity with cure-kinetics during thermal process was proposed. When a package undergoes thermal condition, residual stress between layers occurs. The residual stress is caused by different coefficient of thermal expansion (CTE) and chemical reaction of materials. And it causes package warpage. Because package warpage can affect driven performance, reliability and alignment issues, it is important to predict and control package warpage for designing process and improving a performance of package. For a prediction of package warpage, a finite element method (FEM) is commonly used. With FEM it is able to calculate the warpage caused by different CTE between layers. However, because properties of materials, which have curing characteristic, evolves with curing, if cure-kinetics are not considered, it is difficult to predict package warpage properly. So a numerical approach for considering cure-kinetics of materials was developed to predict package warpage during thermal process. Using user subroutine function in ABAQUS commercial FEM software, we build generalized Maxwell material model which can represent viscoelastic material response. And we calculated degree of curing with Kamal-Sourour cure kinetic equation for each time increment. Then we made parameters for the Maxwell material model as function of degree of curing. As a result, the developed analysis model explains heat generation during curing process and change of material properties depending on degree of curing. With our analysis model, it is expected that more accurate prediction of warpage can be conducted and it leads to improvement of package performance.
{"title":"A Development of Finite Element Analysis Model of 3DIC TSV Package Warpage Considering Cure Dependent Viscoelasticity with Heat Generation","authors":"M. Han, Y. Shin, K. Lim, D. Rhee","doi":"10.1109/ECTC32696.2021.00235","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00235","url":null,"abstract":"In this study, a numerical methodology to predict package warpage considering viscoelasticity with cure-kinetics during thermal process was proposed. When a package undergoes thermal condition, residual stress between layers occurs. The residual stress is caused by different coefficient of thermal expansion (CTE) and chemical reaction of materials. And it causes package warpage. Because package warpage can affect driven performance, reliability and alignment issues, it is important to predict and control package warpage for designing process and improving a performance of package. For a prediction of package warpage, a finite element method (FEM) is commonly used. With FEM it is able to calculate the warpage caused by different CTE between layers. However, because properties of materials, which have curing characteristic, evolves with curing, if cure-kinetics are not considered, it is difficult to predict package warpage properly. So a numerical approach for considering cure-kinetics of materials was developed to predict package warpage during thermal process. Using user subroutine function in ABAQUS commercial FEM software, we build generalized Maxwell material model which can represent viscoelastic material response. And we calculated degree of curing with Kamal-Sourour cure kinetic equation for each time increment. Then we made parameters for the Maxwell material model as function of degree of curing. As a result, the developed analysis model explains heat generation during curing process and change of material properties depending on degree of curing. With our analysis model, it is expected that more accurate prediction of warpage can be conducted and it leads to improvement of package performance.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129918034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00194
Hae-in Kim, Renuka Bowrothu, Woosol Lee, Y. Yoon
In this work, a substrate integrated 3D solenoid inductor with an ultra-high quality factor (Q-factor) is demonstrated using the combination of Through Fused-silica Vias (TFVs) for low substrate loss and Copper (Cu) / Cobalt (Co) metaconductors for low conductor loss for millimeter wave (mmWave) applications. Especially, a Cu/Co metaconductor based 1 turn 3D solenoid inductor is integrated on a $300 mumathrm{m}$ thick fused-silica substrate with a small form factor of $170 mumathrm{m}times 200 mumathrm{m}$. The Cu/Co inductor shows a peak Q-factor of 204 while a solid Cu counterpart does a Q-factor of 88.9 at 28.4 GHz, showing 130% Q-factor improvement. Modeling and optimization of the inductors has been performed using a lumped element circuit model and High Frequency Structure Simulator (HFSS) simulation. Design, fabrication, and characterization of the inductors is detailed.
在这项工作中，展示了一种具有超高质量因子(q因子)的基片集成3D电磁电感器，该电感器使用低基片损耗的熔融硅通孔(TFVs)和用于毫米波(mmWave)应用的低导体损耗的铜(Cu) /钴(Co)元导体的组合。特别是，基于Cu/Co元导体的1匝三维电磁电感集成在300 mu mathm {m}$厚的熔融硅衬底上，其尺寸很小，仅为170 mu mathm {m}$乘以200 mu mathm {m}$。Cu/Co电感在28.4 GHz时的峰值q因子为204，而固体Cu电感的峰值q因子为88.9,q因子提高了130%。利用集总元件电路模型和高频结构模拟器(HFSS)进行了电感器的建模和优化。详细介绍了电感器的设计、制造和特性。
{"title":"Ultra-High Q-factor Through Fused-silica Via (TFV) Integrated 3D Solenoid Inductor for Millimeter Wave Applications","authors":"Hae-in Kim, Renuka Bowrothu, Woosol Lee, Y. Yoon","doi":"10.1109/ECTC32696.2021.00194","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00194","url":null,"abstract":"In this work, a substrate integrated 3D solenoid inductor with an ultra-high quality factor (Q-factor) is demonstrated using the combination of Through Fused-silica Vias (TFVs) for low substrate loss and Copper (Cu) / Cobalt (Co) metaconductors for low conductor loss for millimeter wave (mmWave) applications. Especially, a Cu/Co metaconductor based 1 turn 3D solenoid inductor is integrated on a $300 mumathrm{m}$ thick fused-silica substrate with a small form factor of $170 mumathrm{m}times 200 mumathrm{m}$. The Cu/Co inductor shows a peak Q-factor of 204 while a solid Cu counterpart does a Q-factor of 88.9 at 28.4 GHz, showing 130% Q-factor improvement. Modeling and optimization of the inductors has been performed using a lumped element circuit model and High Frequency Structure Simulator (HFSS) simulation. Design, fabrication, and characterization of the inductors is detailed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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