Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962958
K. Cho, Gyu-Chul Kim, Kee-Moon Chun
When low k HSQ (Hydrogen Silsesquiozane) with DOM (Direct-on-Metal) technique is employed for mass-production, an unusual HSQ-related problem of metal volume shrinkage might occur at relatively small metal patterns such as landing pads, leading to yield loss. In this work, we have set up a plausible model for the mechanism of the shrinkage, presented the results from some split experiments conducted on the basis of the model, and finally proposed some ways to solve the problem by optimizing both fabrication processes and layout design.
{"title":"A plausible model and solutions for an HSQ-related volume shrinkage of aluminum landing pad","authors":"K. Cho, Gyu-Chul Kim, Kee-Moon Chun","doi":"10.1109/ISSM.2001.962958","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962958","url":null,"abstract":"When low k HSQ (Hydrogen Silsesquiozane) with DOM (Direct-on-Metal) technique is employed for mass-production, an unusual HSQ-related problem of metal volume shrinkage might occur at relatively small metal patterns such as landing pads, leading to yield loss. In this work, we have set up a plausible model for the mechanism of the shrinkage, presented the results from some split experiments conducted on the basis of the model, and finally proposed some ways to solve the problem by optimizing both fabrication processes and layout design.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126600096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962903
T. Ishiguro, T. Ro
With the progress towards more integrated semiconductor devices and narrower wiring pitches, there has been a shift from aluminum wiring to the use of copper wiring due to its lower electrical resistance. However, the high diffusion coefficient of copper has adverse effects on the device characteristics. There is also some concern that the CMP (chemical mechanical polishing) process used to form copper wiring is a source of chemical contamination in cleanrooms. Experiments have confirmed that the copper contained in the waste fluid produced during wafer polishing is scattered around the inside of the CMP unit. Copper leaking outside the units during maintenance is safely removed by a cleanroom HEPA filter since the copper quickly oxidizes to form particles. However, the copper adheres to the shoes and gloves of the operators who maintain the CMP units and causes cross-contamination to other process areas. Because 300 mm wafers are transported automatically using FOUPs (front-opening unified pods), we anticipate that in future, different processes will be combined in cleanrooms that share the same conventional air-flow space. In this context, cross-contamination from the Cu-CMP process backside can be prevented by segregating the cleanroom so as to isolate the copper process wafer carriers.
{"title":"Cleanroom design for Cu-CMP processes","authors":"T. Ishiguro, T. Ro","doi":"10.1109/ISSM.2001.962903","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962903","url":null,"abstract":"With the progress towards more integrated semiconductor devices and narrower wiring pitches, there has been a shift from aluminum wiring to the use of copper wiring due to its lower electrical resistance. However, the high diffusion coefficient of copper has adverse effects on the device characteristics. There is also some concern that the CMP (chemical mechanical polishing) process used to form copper wiring is a source of chemical contamination in cleanrooms. Experiments have confirmed that the copper contained in the waste fluid produced during wafer polishing is scattered around the inside of the CMP unit. Copper leaking outside the units during maintenance is safely removed by a cleanroom HEPA filter since the copper quickly oxidizes to form particles. However, the copper adheres to the shoes and gloves of the operators who maintain the CMP units and causes cross-contamination to other process areas. Because 300 mm wafers are transported automatically using FOUPs (front-opening unified pods), we anticipate that in future, different processes will be combined in cleanrooms that share the same conventional air-flow space. In this context, cross-contamination from the Cu-CMP process backside can be prevented by segregating the cleanroom so as to isolate the copper process wafer carriers.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127976569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962907
C. Weißenborn, F. J. Sànchez
At present, data access technology for engineers and technicians is less dynamic and more static, and it can be difficult to obtain readily available information for just in time maintenance and communication, or to use technical schematics, photos and videos to capture expert knowledge in a mobile environment. A mobile tool was needed to provide best known method (BKM) information at the exact time of need without having to spend extra time searching for or locating the information. The Technical Electronic Knowledge Personal Assistant Capsule (TekPAC) interface for the Pocket PC is a device that: provides access to readily available electronic information; allows the user to perform tasks at locations with all schematics, photos, videos and BKMs readily available; integrates key interventions to raise performance of target audience; and provides an input and output module for knowledge capture.
目前，工程师和技术人员的数据访问技术较少动态，更多的是静态的，并且很难获得随时可用的信息，以便及时维护和通信，或者在移动环境中使用技术原理图，照片和视频来捕获专家知识。需要一种移动工具，以便在需要的确切时间提供最知名的方法(BKM)信息，而不必花费额外的时间搜索或定位信息。用于Pocket PC的Technical Electronic Knowledge Personal Assistant Capsule (TekPAC)接口是一种设备，可提供对随时可用的电子信息的访问;允许用户在所有的原理图，照片，视频和bkm随时可用的地点执行任务;整合关键干预措施以提高目标受众的绩效;并提供了知识获取的输入输出模块。
{"title":"TekPAC (Technical Electronic Knowledge Personal Assistant Capsule)","authors":"C. Weißenborn, F. J. Sànchez","doi":"10.1109/ISSM.2001.962907","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962907","url":null,"abstract":"At present, data access technology for engineers and technicians is less dynamic and more static, and it can be difficult to obtain readily available information for just in time maintenance and communication, or to use technical schematics, photos and videos to capture expert knowledge in a mobile environment. A mobile tool was needed to provide best known method (BKM) information at the exact time of need without having to spend extra time searching for or locating the information. The Technical Electronic Knowledge Personal Assistant Capsule (TekPAC) interface for the Pocket PC is a device that: provides access to readily available electronic information; allows the user to perform tasks at locations with all schematics, photos, videos and BKMs readily available; integrates key interventions to raise performance of target audience; and provides an input and output module for knowledge capture.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962934
A. Levy, S. Lakkapragada, W. Mieher, K. Bhatia, U. Whitney, M. Hankinson
Spectroscopic CD (SCD) technology provides high precision shape information with excellent correlation to established critical dimension metrology. Poly-gate wafers from over 20 lots produced in a high-volume manufacturing fab were measured and analyzed with KLA-Tencor's SCD and SEM CD tools. APC simulations on the SCD data demonstrate the potential to reduce the CD deviation from the process target. Focus-exposure process window analysis using additional shape information available with SCD shows the potential value of the more complete view for lithographic cluster tool monitoring.
{"title":"Spectroscopic CD technology for gate process control","authors":"A. Levy, S. Lakkapragada, W. Mieher, K. Bhatia, U. Whitney, M. Hankinson","doi":"10.1109/ISSM.2001.962934","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962934","url":null,"abstract":"Spectroscopic CD (SCD) technology provides high precision shape information with excellent correlation to established critical dimension metrology. Poly-gate wafers from over 20 lots produced in a high-volume manufacturing fab were measured and analyzed with KLA-Tencor's SCD and SEM CD tools. APC simulations on the SCD data demonstrate the potential to reduce the CD deviation from the process target. Focus-exposure process window analysis using additional shape information available with SCD shows the potential value of the more complete view for lithographic cluster tool monitoring.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132818318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962974
M. Hasegawa, Y. Mafune, I. Katoh
The two methods described are useful for stabilizing linewidths in photolithography without making any changes in existing processes and equipment. The methods can also be applied to the stabilization of line widths in 130-nm scale devices, which is currently an urgent need. 1) Controlling the thickness of LOCOS-SiN film can stabilize device isolation width. Also, adjusting the thickness of the resist film can standardize SiN film thickness conditions and thereby reduce deviations in linewidth that are caused by imprecise film thickness. 2) Optimizing the film thickness standard for gate oxidation film processing with a sufficient process capability can increase the range of allowable gate lengths, thereby improving process capability.
{"title":"Methods of stabilizing linewidths in photolithography for improving ASIC plant productivity","authors":"M. Hasegawa, Y. Mafune, I. Katoh","doi":"10.1109/ISSM.2001.962974","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962974","url":null,"abstract":"The two methods described are useful for stabilizing linewidths in photolithography without making any changes in existing processes and equipment. The methods can also be applied to the stabilization of line widths in 130-nm scale devices, which is currently an urgent need. 1) Controlling the thickness of LOCOS-SiN film can stabilize device isolation width. Also, adjusting the thickness of the resist film can standardize SiN film thickness conditions and thereby reduce deviations in linewidth that are caused by imprecise film thickness. 2) Optimizing the film thickness standard for gate oxidation film processing with a sufficient process capability can increase the range of allowable gate lengths, thereby improving process capability.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132077586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962935
K. Nakao, T. Asano, H. Fukushima, H. Yamamoto, A. Dip, R. Joe, D. O'Meara, R. Soave, S. Kaushal
A new concept in multi-wafer (MW) rapid thermal processing (RTP) is presented. An innovative approach to hot-wall, isothermal processing technology advances the conventional large batch environment into the realm of RTP processing. Using recent developments in heater technology along with advancements in other critical processing areas, a method for processing a lot (25 wafers) within an hour in a hot-wall RTP environment is demonstrated.
{"title":"Multi-wafer rapid isothermal processing","authors":"K. Nakao, T. Asano, H. Fukushima, H. Yamamoto, A. Dip, R. Joe, D. O'Meara, R. Soave, S. Kaushal","doi":"10.1109/ISSM.2001.962935","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962935","url":null,"abstract":"A new concept in multi-wafer (MW) rapid thermal processing (RTP) is presented. An innovative approach to hot-wall, isothermal processing technology advances the conventional large batch environment into the realm of RTP processing. Using recent developments in heater technology along with advancements in other critical processing areas, a method for processing a lot (25 wafers) within an hour in a hot-wall RTP environment is demonstrated.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963008
Y. Kaplan
The QUEST System provides a web-based platform for the standardized management, tracking and assessment of quality excursion events across an entire Fab. The system has become the pivot of Intel Corporation Fab18's quality excursion event management and is now in the process of implementation in other factories.
{"title":"The QUEST System in Intel Fab18: a web-based method for the management of quality","authors":"Y. Kaplan","doi":"10.1109/ISSM.2001.963008","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963008","url":null,"abstract":"The QUEST System provides a web-based platform for the standardized management, tracking and assessment of quality excursion events across an entire Fab. The system has become the pivot of Intel Corporation Fab18's quality excursion event management and is now in the process of implementation in other factories.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962914
Shin Hayashi, Y. Tanaka, E. Kodama
Primary productivity in the semiconductor manufacturing industry, which includes cycle time, cost and production, depends to a great extent on the capability of manufacturing administrators (MA), particularly with regard to the critical trade-off between cycle time and tool utilization. The Mahalanobis distance (MD) has significance in pattern recognition, and we have found a method to make use of the MD as the core of a manufacturing control system. By using this system, we can easily distinguish deviations from normality in respect of productivity, specify the root cause of the abnormality and decide how to prioritize the problem. As a result, we can efficiently concentrate limited resources on the root cause in the absence of a capable MA, and restore productivity on a minimum timescale.
{"title":"A new manufacturing control system using Mahalanobis distance for maximising productivity","authors":"Shin Hayashi, Y. Tanaka, E. Kodama","doi":"10.1109/ISSM.2001.962914","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962914","url":null,"abstract":"Primary productivity in the semiconductor manufacturing industry, which includes cycle time, cost and production, depends to a great extent on the capability of manufacturing administrators (MA), particularly with regard to the critical trade-off between cycle time and tool utilization. The Mahalanobis distance (MD) has significance in pattern recognition, and we have found a method to make use of the MD as the core of a manufacturing control system. By using this system, we can easily distinguish deviations from normality in respect of productivity, specify the root cause of the abnormality and decide how to prioritize the problem. As a result, we can efficiently concentrate limited resources on the root cause in the absence of a capable MA, and restore productivity on a minimum timescale.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962904
K. Andou, H. Kondo, T. Masui
300 mm semiconductor factories require the combination of different types of AMHS (Automated Material Handling System) components from different suppliers for optimal AMHS solutions. To realize it, interoperable communication specification for AMHS is required. Selete (Semiconductor Leading Edge Technologies, Inc) has developed it by discussing with member companies of Selete and cooperative AMHS vendors about implementation level requirement specifications, and confirming its interoperability by evaluating actual behaviors of AMHS components in which the above mentioned specifications are implemented. This specification contributes to reduce the cost and time of the communication interface development in AMHS vendors and semiconductor manufacturers when AMHS components from two or more vendors are combined.
300mm半导体工厂需要来自不同供应商的不同类型的AMHS(自动物料搬运系统)组件的组合，以获得最佳的AMHS解决方案。为了实现这一目标，需要有可互操作的AMHS通信规范。Selete (Semiconductor Leading Edge Technologies, Inc)通过与Selete成员公司和AMHS合作供应商讨论实现级需求规范，并通过评估实现上述规范的AMHS组件的实际行为来确认其互操作性，开发了该规范。当来自两个或多个供应商的AMHS组件合并时，该规范有助于减少AMHS供应商和半导体制造商的通信接口开发成本和时间。
{"title":"Interoperable communication specification for AMHS","authors":"K. Andou, H. Kondo, T. Masui","doi":"10.1109/ISSM.2001.962904","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962904","url":null,"abstract":"300 mm semiconductor factories require the combination of different types of AMHS (Automated Material Handling System) components from different suppliers for optimal AMHS solutions. To realize it, interoperable communication specification for AMHS is required. Selete (Semiconductor Leading Edge Technologies, Inc) has developed it by discussing with member companies of Selete and cooperative AMHS vendors about implementation level requirement specifications, and confirming its interoperability by evaluating actual behaviors of AMHS components in which the above mentioned specifications are implemented. This specification contributes to reduce the cost and time of the communication interface development in AMHS vendors and semiconductor manufacturers when AMHS components from two or more vendors are combined.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133578186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962981
M.M. Touzov, T. Fujita, T.K. Doy
This study presents a new approach to edge profile control during air back carrier Chemical Mechanical Polishing (CMP). Control of wafer edge profile proves to be difficult as different factors are reported to influence polishing characteristics. To evaluate a CMP on the wafer's edge it needs to look at polish characteristics of leading and trailing edges separately. To understand polish performance on both leading and trailing edges, and their impact on resulting wafer's edge profile a non-rotating carrier experiment had been conducted. Based on the results of the nonrotating carrier experiment a novel retaining ring design has been proposed. In the course of this study CMP of the wafer's edge evaluation for a novel retaining ring has been performed on blanket PETEOS 200 mm wafers for different retaining pressures. Edge profile evaluation provided a proof for the Pad Wave Hypothesis and helped to significantly enhance the CMP performance by increasing process stability and achieving wider process window for retaining ring pressure.
{"title":"Novel retaining ring to reduce CMP edge exclusion","authors":"M.M. Touzov, T. Fujita, T.K. Doy","doi":"10.1109/ISSM.2001.962981","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962981","url":null,"abstract":"This study presents a new approach to edge profile control during air back carrier Chemical Mechanical Polishing (CMP). Control of wafer edge profile proves to be difficult as different factors are reported to influence polishing characteristics. To evaluate a CMP on the wafer's edge it needs to look at polish characteristics of leading and trailing edges separately. To understand polish performance on both leading and trailing edges, and their impact on resulting wafer's edge profile a non-rotating carrier experiment had been conducted. Based on the results of the nonrotating carrier experiment a novel retaining ring design has been proposed. In the course of this study CMP of the wafer's edge evaluation for a novel retaining ring has been performed on blanket PETEOS 200 mm wafers for different retaining pressures. Edge profile evaluation provided a proof for the Pad Wave Hypothesis and helped to significantly enhance the CMP performance by increasing process stability and achieving wider process window for retaining ring pressure.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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