Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963007
Y. Ishii, N. Ito
Semiconductor manufacturing involves complicated operations, including repeated use of many types of equipment. Since the number of work-in-process (WIP) wafers is very large, in the tens of thousands, it is very difficult for operators to determine the priority of each product. Especially, without the use of information technology (IT), obtaining optimum use of equipment would be a near impossibility while maintaining the WIP balance. Many studies on the application of simulation dispatching to improve semiconductor fabs have been reported We customized part of a simulation/dispatching system based on operator expertise, implemented it, and obtained great improvements in our fabs.
{"title":"Simulation and dispatching systems for production fab management","authors":"Y. Ishii, N. Ito","doi":"10.1109/ISSM.2001.963007","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963007","url":null,"abstract":"Semiconductor manufacturing involves complicated operations, including repeated use of many types of equipment. Since the number of work-in-process (WIP) wafers is very large, in the tens of thousands, it is very difficult for operators to determine the priority of each product. Especially, without the use of information technology (IT), obtaining optimum use of equipment would be a near impossibility while maintaining the WIP balance. Many studies on the application of simulation dispatching to improve semiconductor fabs have been reported We customized part of a simulation/dispatching system based on operator expertise, implemented it, and obtained great improvements in our fabs.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963000
S. Kobayashi, T. Kitano, K. Takeshita, S. Sugimoto, M. Akimoto
This paper introduces the optimum drying technology after scan coating. For this method, we adopted decompression drying method and we found it an optimum method. This is the only method, which is compatible with better thickness profile (1.9%) and rapid throughput (145 sec). The important thing in the drying process is to volatilize solvent slowly and dry the volatilized thinner to make it form a laminar flow. The thickness profile of decompression drying method is not inferior to that of spin coating.
{"title":"Optimum drying method for scan coating","authors":"S. Kobayashi, T. Kitano, K. Takeshita, S. Sugimoto, M. Akimoto","doi":"10.1109/ISSM.2001.963000","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963000","url":null,"abstract":"This paper introduces the optimum drying technology after scan coating. For this method, we adopted decompression drying method and we found it an optimum method. This is the only method, which is compatible with better thickness profile (1.9%) and rapid throughput (145 sec). The important thing in the drying process is to volatilize solvent slowly and dry the volatilized thinner to make it form a laminar flow. The thickness profile of decompression drying method is not inferior to that of spin coating.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132951171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962929
S. Ito, M. Tamaoki, A. Shimazaki, S. Nadahara, K. Okumura, Y. Suzuki, A. Tanaka, M. Tsujimura
The "Wafer Ambient Control Box" has been developed for minimizing the influence of chemical contaminants such as acidic gas, basic gas, organic molecules, and also humidity. It consists of a ULPA filter, chemical filters, SPE films (dehumidifier), and a fan. We applied the Box to the Al interconnection process. The acidic gas adsorbed on the wafer causes corrosion defects. By keeping the wafer in the "Wafer Ambient Control Box", Al lines were prevented from corrosion because the chemical filter trapped the acidic gas desorbed from the wafer. We also applied the humidity controlled one to the poly-Si plug process. The poly-Si/Si contact resistance was equivalent to that processed continuously even though it was kept for 67 h before poly-Si deposition.
{"title":"Wafer ambient control for Agile FAB","authors":"S. Ito, M. Tamaoki, A. Shimazaki, S. Nadahara, K. Okumura, Y. Suzuki, A. Tanaka, M. Tsujimura","doi":"10.1109/ISSM.2001.962929","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962929","url":null,"abstract":"The \"Wafer Ambient Control Box\" has been developed for minimizing the influence of chemical contaminants such as acidic gas, basic gas, organic molecules, and also humidity. It consists of a ULPA filter, chemical filters, SPE films (dehumidifier), and a fan. We applied the Box to the Al interconnection process. The acidic gas adsorbed on the wafer causes corrosion defects. By keeping the wafer in the \"Wafer Ambient Control Box\", Al lines were prevented from corrosion because the chemical filter trapped the acidic gas desorbed from the wafer. We also applied the humidity controlled one to the poly-Si plug process. The poly-Si/Si contact resistance was equivalent to that processed continuously even though it was kept for 67 h before poly-Si deposition.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115706304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962918
Lei Yang, J. Si
This paper focuses on using a new learning algorithm, namely neural dynamic programming (NDP), to design the optimal etch time control system for a reactive ion etch process. First a predictive neural network model is built. This model represents the relation between some state variables and the resulting thickness remain. The NDP is employed to determine the optimal etch time based on the predictive film thickness remain model. Simulation results show that NDP is a viable learning optimization tool. The controlled film thickness remains have smaller variances in a few tested lots of wafers than those measured from 89 wafers during production.
{"title":"Optimal etch time control design using neuro-dynamic programming","authors":"Lei Yang, J. Si","doi":"10.1109/ISSM.2001.962918","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962918","url":null,"abstract":"This paper focuses on using a new learning algorithm, namely neural dynamic programming (NDP), to design the optimal etch time control system for a reactive ion etch process. First a predictive neural network model is built. This model represents the relation between some state variables and the resulting thickness remain. The NDP is employed to determine the optimal etch time based on the predictive film thickness remain model. Simulation results show that NDP is a viable learning optimization tool. The controlled film thickness remains have smaller variances in a few tested lots of wafers than those measured from 89 wafers during production.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114610523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962942
K. Nagai, T. Wada, K. Sajima, S. Saito, A. Ishihama
The purpose of this paper is to suppress the reverse short channel effect (RSCE) of 0.18 /spl mu/m CMOS, which leads to the increase in standby current in PLL and output buffer circuits. RSCE is due to the transient enhanced diffusion of the channel profile induced by source/drain (S/D) implantation. We propose a new process in which the boron for nMOS threshold voltage (V/sub th/) adjustment is implanted through the gate electrode after S/D activation annealing over the blanket wafer. It enables nMOS transistor to have less than 0.1 V V/sub th/ roll-up without increasing wafer cost. It can also be applied effectively in the case of less than 0.13 /spl mu/m devices, not being limited to the case of 0.18 /spl mu/m CMOS devices.
{"title":"Suppression of MOSFET reverse short channel effect by channel doping through gate electrode","authors":"K. Nagai, T. Wada, K. Sajima, S. Saito, A. Ishihama","doi":"10.1109/ISSM.2001.962942","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962942","url":null,"abstract":"The purpose of this paper is to suppress the reverse short channel effect (RSCE) of 0.18 /spl mu/m CMOS, which leads to the increase in standby current in PLL and output buffer circuits. RSCE is due to the transient enhanced diffusion of the channel profile induced by source/drain (S/D) implantation. We propose a new process in which the boron for nMOS threshold voltage (V/sub th/) adjustment is implanted through the gate electrode after S/D activation annealing over the blanket wafer. It enables nMOS transistor to have less than 0.1 V V/sub th/ roll-up without increasing wafer cost. It can also be applied effectively in the case of less than 0.13 /spl mu/m devices, not being limited to the case of 0.18 /spl mu/m CMOS devices.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116476126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962996
M. Ronney, M. van der Burgt, T. Smit, J. Rooda
The transport of wafers inside a multiprocess multiproduct wafer factory is a complex logistic process. In Philips' MOS-3 waferfab this transport is carried out by a so-called automated guided vehicle (AGV) system. In this paper a dynamic model is presented of the AGV system of MOS-3. The advantages of creating such a model are twofold. First of all, the model can be used to analyse the logistics, layout, algorithms and behaviour of the current AGV system. Secondly, the model can analyse and optimise possible changes that can be made to the AGV system in the future.
{"title":"Capacity calculation of an AGV system in a MP2 wafer fab by means of simulation","authors":"M. Ronney, M. van der Burgt, T. Smit, J. Rooda","doi":"10.1109/ISSM.2001.962996","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962996","url":null,"abstract":"The transport of wafers inside a multiprocess multiproduct wafer factory is a complex logistic process. In Philips' MOS-3 waferfab this transport is carried out by a so-called automated guided vehicle (AGV) system. In this paper a dynamic model is presented of the AGV system of MOS-3. The advantages of creating such a model are twofold. First of all, the model can be used to analyse the logistics, layout, algorithms and behaviour of the current AGV system. Secondly, the model can analyse and optimise possible changes that can be made to the AGV system in the future.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123560237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962922
Akiko Hisasue, J. Tateishi, T. Yamano, A. Shigetomi
This report describes a material management system with a function of estimated number based on MES. It is difficult to ensure adequate quantity of the required stock for each material in a development fabrication, because of the change of process flow and materials. Using the method of estimated number which utilizes the number of wafers which will be used in a production control system, we have been able to ensure adequate quantity of the required stock for each material and take measures for logistics or cost reduction.
{"title":"Material management system with the function of estimated number based on production control system","authors":"Akiko Hisasue, J. Tateishi, T. Yamano, A. Shigetomi","doi":"10.1109/ISSM.2001.962922","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962922","url":null,"abstract":"This report describes a material management system with a function of estimated number based on MES. It is difficult to ensure adequate quantity of the required stock for each material in a development fabrication, because of the change of process flow and materials. Using the method of estimated number which utilizes the number of wafers which will be used in a production control system, we have been able to ensure adequate quantity of the required stock for each material and take measures for logistics or cost reduction.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963014
R.G. Blunn, M.J. Dorough, S. Velichko
Fault tolerant modeling constraints are presented to reduce wafer test times attributed to sequential semiconductor measurement and testing (SMT) and to avoid product damage and deviation in quality during testing. The concept is expressed using the Unified Modeling Language statecharts and is further reinforced with a mathematical finite-state machine. By adhering to constraints, translation of this object-oriented model to the solution space has been successfully applied to a parametric in-line testing system (PITS) resulting in significant reduction of test time. PITS statistical data is used to support our models by comparing previous sequential implementation to our new concurrent approach.
{"title":"Concurrent fault tolerant control of semiconductor measurement and testing","authors":"R.G. Blunn, M.J. Dorough, S. Velichko","doi":"10.1109/ISSM.2001.963014","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963014","url":null,"abstract":"Fault tolerant modeling constraints are presented to reduce wafer test times attributed to sequential semiconductor measurement and testing (SMT) and to avoid product damage and deviation in quality during testing. The concept is expressed using the Unified Modeling Language statecharts and is further reinforced with a mathematical finite-state machine. By adhering to constraints, translation of this object-oriented model to the solution space has been successfully applied to a parametric in-line testing system (PITS) resulting in significant reduction of test time. PITS statistical data is used to support our models by comparing previous sequential implementation to our new concurrent approach.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127267066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962973
C. Willis, P. Foglietti, J. Artinger
A residual gas analyzer (RGA) has been employed to analyse trace gases in a LPCVD polysilicon reactor used for emitter polysilicon process. Process steps leading up to this oxidation have been characterized in terms of water and oxygen partial pressure. An alternative process of an ozonated water rinse in the preceding wet clean is proposed in order to grow a stable and reliable ultra-thin layer of chemical oxide.
{"title":"Emitter polysilicon process optimization by RGA and process proposal for interfacial oxide growth using ozonated water","authors":"C. Willis, P. Foglietti, J. Artinger","doi":"10.1109/ISSM.2001.962973","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962973","url":null,"abstract":"A residual gas analyzer (RGA) has been employed to analyse trace gases in a LPCVD polysilicon reactor used for emitter polysilicon process. Process steps leading up to this oxidation have been characterized in terms of water and oxygen partial pressure. An alternative process of an ozonated water rinse in the preceding wet clean is proposed in order to grow a stable and reliable ultra-thin layer of chemical oxide.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116144307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962983
A. Fujii, T. Muraoka, T. Yano, T. Tanaka, H. Miyoshi, M. Yoneda, K. Morimoto, A. Shigetomi
In this paper, we report that the control of generation of small particles is quite significant to enhance the yield of ULSI devices with a design rule beyond 100 nm. Observation of defects after silicon nitride film deposition on specially prepared wafers with very low number of COPs (crystal-originated particle), which generate noise signals, shows a steep increase in the number of particles below a 0.1 /spl mu/m range. We found that the behavior of a small particles depended on the ambient in which the wafers were kept before the deposition process. We suspected that tiny pieces of ice produced by freezing moisture droplets became the core for extraordinary film growth. It is important for us to keep the wafer and ambient dry before the vacuum process.
{"title":"Defect management technology for 100 nm generation","authors":"A. Fujii, T. Muraoka, T. Yano, T. Tanaka, H. Miyoshi, M. Yoneda, K. Morimoto, A. Shigetomi","doi":"10.1109/ISSM.2001.962983","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962983","url":null,"abstract":"In this paper, we report that the control of generation of small particles is quite significant to enhance the yield of ULSI devices with a design rule beyond 100 nm. Observation of defects after silicon nitride film deposition on specially prepared wafers with very low number of COPs (crystal-originated particle), which generate noise signals, shows a steep increase in the number of particles below a 0.1 /spl mu/m range. We found that the behavior of a small particles depended on the ambient in which the wafers were kept before the deposition process. We suspected that tiny pieces of ice produced by freezing moisture droplets became the core for extraordinary film growth. It is important for us to keep the wafer and ambient dry before the vacuum process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"748 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123867637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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