Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962990
Sang-mun Chon, S. Choi, Dong Chun Lee, C. Jun, Sung-gon Ryu, Sun Yong Choi
Due to shrinkage of design rule, optical in-line defect inspection with white-light source is reaching its detection limit. To overcome the limitation, a defect inspection system using UV confocal microscopy was recently introduced. In this paper, we investigated characteristics of UV confocal microscopy, which is confocal microscopy using UV light source, by analyzing TDI images captured by a defect inspection system with UV confocal microscopy. The results of this study showed that UV confocal microscopy has higher sensitivity and is more efficient for detection of 0.1 /spl mu/m-level small defects rather than white-light source or conventional microscopy.
{"title":"Characteristics of UV confocal microscopy inspection for detecting 0.1 /spl mu/m level defects","authors":"Sang-mun Chon, S. Choi, Dong Chun Lee, C. Jun, Sung-gon Ryu, Sun Yong Choi","doi":"10.1109/ISSM.2001.962990","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962990","url":null,"abstract":"Due to shrinkage of design rule, optical in-line defect inspection with white-light source is reaching its detection limit. To overcome the limitation, a defect inspection system using UV confocal microscopy was recently introduced. In this paper, we investigated characteristics of UV confocal microscopy, which is confocal microscopy using UV light source, by analyzing TDI images captured by a defect inspection system with UV confocal microscopy. The results of this study showed that UV confocal microscopy has higher sensitivity and is more efficient for detection of 0.1 /spl mu/m-level small defects rather than white-light source or conventional microscopy.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128198671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962931
N. Benesch, A. Hettwer, C. Schneider, L. Pfitzner, H. Ryssel
A cost-effective scatterometry method is presented which is suitable for integrated linewidth control and which is a supplement to conventional SEMs. The phi-scatterometry procedure is carried out directly on periodic functional patterns instead of using additional test structures. Long-term simulations of diffraction effects are not required. The measurement results are evaluated by neural networks performing classifications of pattern parameters. Thereby, fast fault detection and immediate process control is enabled. A phi-scatterometry prototype was built for flexible mobile metrology in 300-mm production environments. The measurement principle was verified with DRAM patterns having trenches in two dimensions.
{"title":"Phi-scatterometry for integrated linewidth control in DRAM manufacturing","authors":"N. Benesch, A. Hettwer, C. Schneider, L. Pfitzner, H. Ryssel","doi":"10.1109/ISSM.2001.962931","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962931","url":null,"abstract":"A cost-effective scatterometry method is presented which is suitable for integrated linewidth control and which is a supplement to conventional SEMs. The phi-scatterometry procedure is carried out directly on periodic functional patterns instead of using additional test structures. Long-term simulations of diffraction effects are not required. The measurement results are evaluated by neural networks performing classifications of pattern parameters. Thereby, fast fault detection and immediate process control is enabled. A phi-scatterometry prototype was built for flexible mobile metrology in 300-mm production environments. The measurement principle was verified with DRAM patterns having trenches in two dimensions.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126193516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSM.2001.962998
S. Gendt, M. Heyns, T. Conard, H. Hohira, O. Richard, Wilfried Vandervorst, M. Caymax, J. W. Maes, Marko Tuominen
Oxide layers of metals such as Zr and Al are possible candidates to replace SiO/sub 2/ as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and we indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al/sub 2/O/sub 3/, and ZrO/sub 2/ layer is presented. We discuss the importance of a cluster tool for this application based on those process results.
{"title":"Gate stack preparation with high-k materials in a cluster tool","authors":"S. Gendt, M. Heyns, T. Conard, H. Hohira, O. Richard, Wilfried Vandervorst, M. Caymax, J. W. Maes, Marko Tuominen","doi":"10.1109/ISSM.2001.962998","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962998","url":null,"abstract":"Oxide layers of metals such as Zr and Al are possible candidates to replace SiO/sub 2/ as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and we indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al/sub 2/O/sub 3/, and ZrO/sub 2/ layer is presented. We discuss the importance of a cluster tool for this application based on those process results.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128959054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSM.2001.962966
M. Sugimoto, M. Tanaka
This paper describes an improvement in our algorithm, which can efficiently characterize a process-induced random failure distribution and a design-induced systematic failure distribution from unknown-induced failure distributions of a memory LSI, to predict a reason for yield degradation in it. The algorithm analyzes a function "T(f) isn't greater than 1or not" related to kind and content of "f". The "f" is a divisor of distances between failure-pairs. We have expanded the algorithm, which can pick out 7 characteristic failure distributions by using relationship between the failure densities and the function "T(f)".
{"title":"Characterization algorithm of failure distribution for LSI yield improvement","authors":"M. Sugimoto, M. Tanaka","doi":"10.1109/ISSM.2001.962966","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962966","url":null,"abstract":"This paper describes an improvement in our algorithm, which can efficiently characterize a process-induced random failure distribution and a design-induced systematic failure distribution from unknown-induced failure distributions of a memory LSI, to predict a reason for yield degradation in it. The algorithm analyzes a function \"T(f) isn't greater than 1or not\" related to kind and content of \"f\". The \"f\" is a divisor of distances between failure-pairs. We have expanded the algorithm, which can pick out 7 characteristic failure distributions by using relationship between the failure densities and the function \"T(f)\".","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114633409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSM.2001.962975
C. Grenci, V. Sauers, R. King, D. Dodge, M. Schlecht, K. Gray, R. Foley
Particle control is an important objective in Al etch systems. Unquestionably, polymer buildup must be kept under control. Defects, which result from chamber flaking, typically bridge metal lines together, resulting in lower yield. Excessive polymer buildup requires a chamber wetclean, consuming manpower and equipment uptime. Currently, most metal etch process chambers in the world require a wet clean at 90 - 150 hours. This article presents measures to control polymer buildup, and a qualification procedure to ensure the cleanliness of the chamber prior to running product. It will also show how Cypress Semiconductor has improved its metal etch mean time between cleans to 350 - 450 RF hours while improving yield.
{"title":"Polymer control in aluminum etch chambers to achieve >450 hours MTBC","authors":"C. Grenci, V. Sauers, R. King, D. Dodge, M. Schlecht, K. Gray, R. Foley","doi":"10.1109/ISSM.2001.962975","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962975","url":null,"abstract":"Particle control is an important objective in Al etch systems. Unquestionably, polymer buildup must be kept under control. Defects, which result from chamber flaking, typically bridge metal lines together, resulting in lower yield. Excessive polymer buildup requires a chamber wetclean, consuming manpower and equipment uptime. Currently, most metal etch process chambers in the world require a wet clean at 90 - 150 hours. This article presents measures to control polymer buildup, and a qualification procedure to ensure the cleanliness of the chamber prior to running product. It will also show how Cypress Semiconductor has improved its metal etch mean time between cleans to 350 - 450 RF hours while improving yield.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116211771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSM.2001.962957
H. Matsushita, K. Mitsutake, Y. Arakawa, T. Ishibumi, Y. Ushiku
We performed automatic detection of lithography-related faults by characteristic factors calculated from Fail Bit Count (FBC) data. The frequency of lithography-related faults was monitored as time series data and their origin was specified by correlating machine data. We could classify lithography-related faults and evaluate their yield impact from their frequency and yield loss automatically.
{"title":"Highly sensitive inspection system for lithography-related faults in agile-fab detecting algorithm, monitoring and evaluation of yield impact","authors":"H. Matsushita, K. Mitsutake, Y. Arakawa, T. Ishibumi, Y. Ushiku","doi":"10.1109/ISSM.2001.962957","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962957","url":null,"abstract":"We performed automatic detection of lithography-related faults by characteristic factors calculated from Fail Bit Count (FBC) data. The frequency of lithography-related faults was monitored as time series data and their origin was specified by correlating machine data. We could classify lithography-related faults and evaluate their yield impact from their frequency and yield loss automatically.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125453456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSM.2001.962943
M.C. Yu, H. Huang, C. Chen, M. Wang, T. Hou, Y.M. Lin, S. Jang, C. H. Diaz, J. Sun, Y. Fang, S. Chen, C. Yu, M. Liang
We investigate the scaling limit of base oxides treated by thermally-enhanced remote plasma nitridation (TE-RPN) for ultra-thin gate dielectric formation. Under optimized RPN conditions, this work shows gate-dielectric equivalent thickness (EOT) scalability and no transconductance degradation are characteristic of processes with base oxide thickness down to 17 /spl Aring/. Thinner base oxides result in reduced EOT scalability and transconductance degradation, resulting in /spl sim/14 /spl Aring/ manufacturable EOT limit for TE-RPN gate dielectrics.
{"title":"Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation","authors":"M.C. Yu, H. Huang, C. Chen, M. Wang, T. Hou, Y.M. Lin, S. Jang, C. H. Diaz, J. Sun, Y. Fang, S. Chen, C. Yu, M. Liang","doi":"10.1109/ISSM.2001.962943","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962943","url":null,"abstract":"We investigate the scaling limit of base oxides treated by thermally-enhanced remote plasma nitridation (TE-RPN) for ultra-thin gate dielectric formation. Under optimized RPN conditions, this work shows gate-dielectric equivalent thickness (EOT) scalability and no transconductance degradation are characteristic of processes with base oxide thickness down to 17 /spl Aring/. Thinner base oxides result in reduced EOT scalability and transconductance degradation, resulting in /spl sim/14 /spl Aring/ manufacturable EOT limit for TE-RPN gate dielectrics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134448552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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