Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962948
H. Tomita, M. Sato, S. Nadahara, T. Saitoh
Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.
{"title":"Photoresist stripping using novel sulfuric/ozone process","authors":"H. Tomita, M. Sato, S. Nadahara, T. Saitoh","doi":"10.1109/ISSM.2001.962948","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962948","url":null,"abstract":"Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133441865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962976
Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho
Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.
{"title":"A study on ILD process of simple and CMP skip using polysilazane-based SOG","authors":"Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho","doi":"10.1109/ISSM.2001.962976","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962976","url":null,"abstract":"Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132844684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963020
H. Sugawara, Y. Tajima, T. Ohmi
A tetramethylammonium hydroxide (TMAH) generally used as photoresist developer for manufacturing LSIs and LCDs is recovered from developer waste (spent developer) using an electrodialysis (ED) method, and purified by ion exchange (IE) technologies. Reclaimed developer features analytically the same purity as commercial fresh one. This reclamation system can achieve a stably high TMAH recovery rate of more than 80%. Furthermore, it has the great advantages of saving operating costs, which amounts to 66.2% (for LSI) and 78.3% (for LCD) total cost reduction compared with conventional no reclamation system in a case study, as well as reducing environmental load.
{"title":"Photoresist developer reclamation technology and system","authors":"H. Sugawara, Y. Tajima, T. Ohmi","doi":"10.1109/ISSM.2001.963020","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963020","url":null,"abstract":"A tetramethylammonium hydroxide (TMAH) generally used as photoresist developer for manufacturing LSIs and LCDs is recovered from developer waste (spent developer) using an electrodialysis (ED) method, and purified by ion exchange (IE) technologies. Reclaimed developer features analytically the same purity as commercial fresh one. This reclamation system can achieve a stably high TMAH recovery rate of more than 80%. Furthermore, it has the great advantages of saving operating costs, which amounts to 66.2% (for LSI) and 78.3% (for LCD) total cost reduction compared with conventional no reclamation system in a case study, as well as reducing environmental load.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134576537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962917
D. Collins, V. Lakshman, L. Collins
We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.
{"title":"Dynamic simulator for WIP analysis in semiconductor manufacturing","authors":"D. Collins, V. Lakshman, L. Collins","doi":"10.1109/ISSM.2001.962917","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962917","url":null,"abstract":"We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962972
D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura
The gas cleaning of the hot-wall batch type Ru CVD reactor by oxygen was investigated. The cleaning mechanism is considered as follows. Below 800/spl deg/C, Ru film is oxidized and forms RuO/sub 2/ which is not volatile. But above 800/spl deg/C, RuO/sub 2/ film, which is formed at first, is oxidized again to form RuO/sub 4/. Since RuO/sub 4/ is volatile, it evaporates easily. High temperature, low pressure and high oxygen flow rate were required to obtain fast Ru etching rate. With these optimum cleaning conditions by design of experiments (DOE), 30-nm-thick Ru film was removed completely in 20 minutes. We could accomplish this in situ oxygen gas cleaning effectively in short time by using hot-wall batch type Ru CVD equipment, which has high heating and cooling rate characteristics.
{"title":"Cleaning technique of hot-wall batch type Ru CVD equipment by oxygen gas","authors":"D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura","doi":"10.1109/ISSM.2001.962972","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962972","url":null,"abstract":"The gas cleaning of the hot-wall batch type Ru CVD reactor by oxygen was investigated. The cleaning mechanism is considered as follows. Below 800/spl deg/C, Ru film is oxidized and forms RuO/sub 2/ which is not volatile. But above 800/spl deg/C, RuO/sub 2/ film, which is formed at first, is oxidized again to form RuO/sub 4/. Since RuO/sub 4/ is volatile, it evaporates easily. High temperature, low pressure and high oxygen flow rate were required to obtain fast Ru etching rate. With these optimum cleaning conditions by design of experiments (DOE), 30-nm-thick Ru film was removed completely in 20 minutes. We could accomplish this in situ oxygen gas cleaning effectively in short time by using hot-wall batch type Ru CVD equipment, which has high heating and cooling rate characteristics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123227644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962968
A. Skumanich, E. Ryabova
A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies.
{"title":"Methodology for yield analysis based on targeted defect impact studies","authors":"A. Skumanich, E. Ryabova","doi":"10.1109/ISSM.2001.962968","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962968","url":null,"abstract":"A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128390942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962949
K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput
A primary challenge in building integrated circuits with geometries of 0.13 /spl mu/m and smaller is the development of materials with low dielectric constants. The properties of the low k films must be compatible with subsequent processing for integration. The present work describes the influence of the starting materials (precursors) and of the deposition process on the electrical and mechanical properties of the low k film.
{"title":"Low k material optimization","authors":"K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput","doi":"10.1109/ISSM.2001.962949","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962949","url":null,"abstract":"A primary challenge in building integrated circuits with geometries of 0.13 /spl mu/m and smaller is the development of materials with low dielectric constants. The properties of the low k films must be compatible with subsequent processing for integration. The present work describes the influence of the starting materials (precursors) and of the deposition process on the electrical and mechanical properties of the low k film.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963027
T. Croft, H. Toeante, T. Baker
Knowing the current labor needs of your fab is an awareness; knowing the labor needs of your fab in the future is a science and an art. Keeping accurate and up-to-date labor modeling is vital to the health of a manufacturing organization, especially in a highly cost-competitive environment. AMD's Fab 25 recognizes the need to understand the labor components in our cost structure and the necessity to control this delicate element. Using both an analytical and research approach to a difficult problem, we successfully built a labor model for Fab 25.
{"title":"Labor modeling in a dynamic environment","authors":"T. Croft, H. Toeante, T. Baker","doi":"10.1109/ISSM.2001.963027","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963027","url":null,"abstract":"Knowing the current labor needs of your fab is an awareness; knowing the labor needs of your fab in the future is a science and an art. Keeping accurate and up-to-date labor modeling is vital to the health of a manufacturing organization, especially in a highly cost-competitive environment. AMD's Fab 25 recognizes the need to understand the labor components in our cost structure and the necessity to control this delicate element. Using both an analytical and research approach to a difficult problem, we successfully built a labor model for Fab 25.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127750145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963023
Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi
Clean room air contains many kinds of contaminants such as moisture and organic compounds. The device performance is influenced by them, therefore, Si wafers should not be exposed to clean room air. We have developed the next generation Si wafer transfer/stock system using out-gas free advanced resin and CDA (Clean Dry Air). The advanced resin has various advantageous properties for a Si wafer transfer box and stocker. For example, (1) out-gas free, (2) light weight, (3) high transparency, (4) high strength, etc. Using the advanced resin, we have developed a new Si wafer transfer pod, called BORP (Bottom Opening Removal Pod).
{"title":"Development of the next generation Si wafer transfer/stock system","authors":"Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi","doi":"10.1109/ISSM.2001.963023","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963023","url":null,"abstract":"Clean room air contains many kinds of contaminants such as moisture and organic compounds. The device performance is influenced by them, therefore, Si wafers should not be exposed to clean room air. We have developed the next generation Si wafer transfer/stock system using out-gas free advanced resin and CDA (Clean Dry Air). The advanced resin has various advantageous properties for a Si wafer transfer box and stocker. For example, (1) out-gas free, (2) light weight, (3) high transparency, (4) high strength, etc. Using the advanced resin, we have developed a new Si wafer transfer pod, called BORP (Bottom Opening Removal Pod).","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963002
C. Frum, Z. Sui, Hongching Shan
In this paper, we present an in-situ interferometric technique to control the trench depth for etching various type of patterned dielectric films, including silicon oxide, low-k black diamond, and low k SILK materials. We present the data on etching oxide trench wafers with various pattern density on Si substrate, black diamond film on Si, and SILK on Si, using Applied Materials' MERIE dielectric etch chambers. A good correlation between predicted etch depth using interferometric signals and SEM depth data is presented. In addition, the issues of integrating this sensor into a dielectric etch chamber are addressed.
{"title":"Interferometric techniques for dielectric trench etch applications","authors":"C. Frum, Z. Sui, Hongching Shan","doi":"10.1109/ISSM.2001.963002","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963002","url":null,"abstract":"In this paper, we present an in-situ interferometric technique to control the trench depth for etching various type of patterned dielectric films, including silicon oxide, low-k black diamond, and low k SILK materials. We present the data on etching oxide trench wafers with various pattern density on Si substrate, black diamond film on Si, and SILK on Si, using Applied Materials' MERIE dielectric etch chambers. A good correlation between predicted etch depth using interferometric signals and SEM depth data is presented. In addition, the issues of integrating this sensor into a dielectric etch chamber are addressed.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"2162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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