Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962932
Runzi Chang, C. Spanos
Chemical mechanical polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130 nm feature sizes. We present the application of a library-based specular spectroscopic scatterometry method, which is capable of getting a clear view of the profile evolution due to the oxide CMP process. This level of analysis will be crucial in building a rigorous CMP model in the near future.
{"title":"Full profile inter-layer dielectric CMP analysis","authors":"Runzi Chang, C. Spanos","doi":"10.1109/ISSM.2001.962932","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962932","url":null,"abstract":"Chemical mechanical polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130 nm feature sizes. We present the application of a library-based specular spectroscopic scatterometry method, which is capable of getting a clear view of the profile evolution due to the oxide CMP process. This level of analysis will be crucial in building a rigorous CMP model in the near future.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962991
T. Wang, T. Hsieh, Y. Wang, C.W. Liu, K. Lo, J.K. Wang, W. Lee
Chemical Mechanical Polishing (CMP) is widely used for global planarization in IC device structure. A pad conditioner is often used to remove polishing debris, and hence preventing the pad surface from glazing. The proper conditioning can assure the pad surface like new so it can hold slurry evenly for effective polishing. Diamond disks are commonly used for conditioning the CMP pads. The designs of diamond disks are critical as it determines the efficiency of the grooving action. All conventional diamond disks contain grits that are distributed randomly. A novel disk provided a regular diamond grits. They are set with a fixed diamond distance and diamond protrusion. These characteristics provide a smoothly slurry distribution and conditioning efficiency. Tungsten chemical mechanical polishing (WCMP) is used for W burden removal, but also is a challenging process due to metal-binder's corrosion on diamond disk during pad conditioning. Diamond segregation and diamond pullouts arising from metal dissolution of diamond disk not only make the conditioning inefficient, but also damage and contaminate the polished wafer surface. It is a major yield killer for deep sub-micro device. In this study, the new disk made by the novel diamond grid technology with a fixed diamond size and pitch appears feasible for in-situ WCMP application. It shows a relationship of polish performance between diamond size & diamond pitch. The higher polish performance got as diamond size decreasing and increasing working efficiency.
{"title":"A novel pad conditioning disk design of tungsten chemical mechanical polishing process for deep sub-micron device yield improvement","authors":"T. Wang, T. Hsieh, Y. Wang, C.W. Liu, K. Lo, J.K. Wang, W. Lee","doi":"10.1109/ISSM.2001.962991","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962991","url":null,"abstract":"Chemical Mechanical Polishing (CMP) is widely used for global planarization in IC device structure. A pad conditioner is often used to remove polishing debris, and hence preventing the pad surface from glazing. The proper conditioning can assure the pad surface like new so it can hold slurry evenly for effective polishing. Diamond disks are commonly used for conditioning the CMP pads. The designs of diamond disks are critical as it determines the efficiency of the grooving action. All conventional diamond disks contain grits that are distributed randomly. A novel disk provided a regular diamond grits. They are set with a fixed diamond distance and diamond protrusion. These characteristics provide a smoothly slurry distribution and conditioning efficiency. Tungsten chemical mechanical polishing (WCMP) is used for W burden removal, but also is a challenging process due to metal-binder's corrosion on diamond disk during pad conditioning. Diamond segregation and diamond pullouts arising from metal dissolution of diamond disk not only make the conditioning inefficient, but also damage and contaminate the polished wafer surface. It is a major yield killer for deep sub-micro device. In this study, the new disk made by the novel diamond grid technology with a fixed diamond size and pitch appears feasible for in-situ WCMP application. It shows a relationship of polish performance between diamond size & diamond pitch. The higher polish performance got as diamond size decreasing and increasing working efficiency.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116768364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963026
J.L. Dauphinee
In 1997, a group of senior managers from the worldwide locations of the IBM Microelectronics Division established a team to investigate and improve manufacturing operator training. Emphasis was placed on developing and implementing a sustained process with continuous improvement. The team chose both project management and process maturity disciplines to guide the development and implementation of a sustainable training process.
{"title":"Development and implementation of a sustainable operator training and certification process","authors":"J.L. Dauphinee","doi":"10.1109/ISSM.2001.963026","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963026","url":null,"abstract":"In 1997, a group of senior managers from the worldwide locations of the IBM Microelectronics Division established a team to investigate and improve manufacturing operator training. Emphasis was placed on developing and implementing a sustained process with continuous improvement. The team chose both project management and process maturity disciplines to guide the development and implementation of a sustainable training process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121181897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962946
K. Monahan, A. Engineer, Georges Falessi, M. Hankinson, Sung Jin Lee, A. Levy, M. Slessor
Previously, we developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.
{"title":"Microeconomics of accelerated shrinks in demand-limited markets","authors":"K. Monahan, A. Engineer, Georges Falessi, M. Hankinson, Sung Jin Lee, A. Levy, M. Slessor","doi":"10.1109/ISSM.2001.962946","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962946","url":null,"abstract":"Previously, we developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962925
S. Wilson
Mean time to repair, mean time to repeat failure/repair, time to first failure after PM (preventative maintenance), and tool availability - the need to link these topics to training and other performance interventions is becoming paramount. How do we know that the time a technician spends in training (or other performance intervention) is worth it? As Intel continuously strives for improvement, departments are asked to prove their impact in terms of business/factory pay-offs. This paper discusses a successful project at Intel in which training was evaluated in terms of equipment indicator improvements, namely: average availability increase across AWX (Automated Wet Station/Bench) tools of 4.25% (which equated /spl sim/8 additional hours of production time/week).Variation in availability declined by an average 4.4% across the AWX tools.
{"title":"Talking shop - linking training to factory indicators","authors":"S. Wilson","doi":"10.1109/ISSM.2001.962925","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962925","url":null,"abstract":"Mean time to repair, mean time to repeat failure/repair, time to first failure after PM (preventative maintenance), and tool availability - the need to link these topics to training and other performance interventions is becoming paramount. How do we know that the time a technician spends in training (or other performance intervention) is worth it? As Intel continuously strives for improvement, departments are asked to prove their impact in terms of business/factory pay-offs. This paper discusses a successful project at Intel in which training was evaluated in terms of equipment indicator improvements, namely: average availability increase across AWX (Automated Wet Station/Bench) tools of 4.25% (which equated /spl sim/8 additional hours of production time/week).Variation in availability declined by an average 4.4% across the AWX tools.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126857037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962921
Kong Pin, Lee Yen Fei, Ang Chee Teck
The paper presents two approaches to determine the foundry fab manufacturing production plan. The two approaches are namely, the Cycle Time Oriented (CTO) method the WIP Energy Oriented (WEO) method. The objective of CTO method is to derive a model with the consideration in the aspects of the master production plan (MPP) and cycle time (CT). On the other hand, the WEO model explores the consideration of the WIP balancing and linear wafer out (or planned wafer out) to determine the amount of stage-moves demand. The concepts and models were built and applied over a period in SSMC and therefore, giving birth to a complete study for manufacturing production plan.
{"title":"Two approaches to determine appropriated fab manufacturing production plan by cycle-time and WIP energy","authors":"Kong Pin, Lee Yen Fei, Ang Chee Teck","doi":"10.1109/ISSM.2001.962921","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962921","url":null,"abstract":"The paper presents two approaches to determine the foundry fab manufacturing production plan. The two approaches are namely, the Cycle Time Oriented (CTO) method the WIP Energy Oriented (WEO) method. The objective of CTO method is to derive a model with the consideration in the aspects of the master production plan (MPP) and cycle time (CT). On the other hand, the WEO model explores the consideration of the WIP balancing and linear wafer out (or planned wafer out) to determine the amount of stage-moves demand. The concepts and models were built and applied over a period in SSMC and therefore, giving birth to a complete study for manufacturing production plan.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"30 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131318921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962912
K. Uriga, B. Crandell
This paper addresses wafer level tracking as the key technology to achieve higher productivity in a full mini-environmentalized (M-E) manufacturing line. Texas Instruments has developed and installed the M-E and wafer level tracking control system for the new 8 inch line in Dallas and transferred the same concept to new 8 inch lines in other fabs. The wafer level tracking (WLT) system established the following: elimination of 100% of wafer scraps caused by mishandling by manufacturing technician; retention of the same working productivity in the M-E line as in legacy lines using open cassettes; provision of tracking data for wafer level fault detection. The approach, issues and achievements are discussed in this paper.
{"title":"Wafer level tracking and control to full mini-environment line","authors":"K. Uriga, B. Crandell","doi":"10.1109/ISSM.2001.962912","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962912","url":null,"abstract":"This paper addresses wafer level tracking as the key technology to achieve higher productivity in a full mini-environmentalized (M-E) manufacturing line. Texas Instruments has developed and installed the M-E and wafer level tracking control system for the new 8 inch line in Dallas and transferred the same concept to new 8 inch lines in other fabs. The wafer level tracking (WLT) system established the following: elimination of 100% of wafer scraps caused by mishandling by manufacturing technician; retention of the same working productivity in the M-E line as in legacy lines using open cassettes; provision of tracking data for wafer level fault detection. The approach, issues and achievements are discussed in this paper.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122310215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962944
T. Fujita, M. Touzov, S. Michiya, T.K. Doy
An air float carrier is developed to achieve uniform polishing with continuous air supply during polishing of the wafer. The carrier has a thin support film inside the retainer ring. Retainer pressure enables the support film to push the wafer edge down to the pad locally to control edge-polishing profile. Using this air float carrier, we try to evaluate the relationship between pressure profile measured under static condition and actual edge-polishing profile at various retainer extensions and various retainer pressures. As a result of this comparison, it has become evident that the calculated pressure profile corresponds to the actual edge-polishing profile and retainer pressure has a great influence on the actual edge-polishing profile.
{"title":"Control of edge polishing profile with air float carrier","authors":"T. Fujita, M. Touzov, S. Michiya, T.K. Doy","doi":"10.1109/ISSM.2001.962944","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962944","url":null,"abstract":"An air float carrier is developed to achieve uniform polishing with continuous air supply during polishing of the wafer. The carrier has a thin support film inside the retainer ring. Retainer pressure enables the support film to push the wafer edge down to the pad locally to control edge-polishing profile. Using this air float carrier, we try to evaluate the relationship between pressure profile measured under static condition and actual edge-polishing profile at various retainer extensions and various retainer pressures. As a result of this comparison, it has become evident that the calculated pressure profile corresponds to the actual edge-polishing profile and retainer pressure has a great influence on the actual edge-polishing profile.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115623765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962902
Y. Mikata, K. Mitsutake, T. Arikado, K. Okumura
Recently SoC devices require QTAT and low cost. Also SoC device quickly change its design so that total production amount is not so many. In this situation we propose the Agile fab to solve these problems. The basic concept of the Agile fab consists of following three ideas; (i) Small size Jab supported by virtual Jab, (ii) Multi-task and multi-functional tools, (iii) Minimization and smoothing of RPT (Raw Process Time). WIP control is important for maximum production and minimized X-factor. Multi-functional and multi-task tools make it possible to reduce the excess capacity and the excess investment. Those tools are furnace, dry etching, wet cleaning, stencil ion implantation. Reduction of RPT is achieved by the sequential process, stencil mask ion implantation process, scan-coating for insulating layers and new electro-plating process. The total RPT is reduced less than a half of conventional case. The tool numbers can be reduced to about a half using the multi-functional, multi-task tools and minimization of RPT.
{"title":"Agile fab concepts for cost effective and QTAT mini fab","authors":"Y. Mikata, K. Mitsutake, T. Arikado, K. Okumura","doi":"10.1109/ISSM.2001.962902","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962902","url":null,"abstract":"Recently SoC devices require QTAT and low cost. Also SoC device quickly change its design so that total production amount is not so many. In this situation we propose the Agile fab to solve these problems. The basic concept of the Agile fab consists of following three ideas; (i) Small size Jab supported by virtual Jab, (ii) Multi-task and multi-functional tools, (iii) Minimization and smoothing of RPT (Raw Process Time). WIP control is important for maximum production and minimized X-factor. Multi-functional and multi-task tools make it possible to reduce the excess capacity and the excess investment. Those tools are furnace, dry etching, wet cleaning, stencil ion implantation. Reduction of RPT is achieved by the sequential process, stencil mask ion implantation process, scan-coating for insulating layers and new electro-plating process. The total RPT is reduced less than a half of conventional case. The tool numbers can be reduced to about a half using the multi-functional, multi-task tools and minimization of RPT.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962971
J. Chen, L. Wei, Y. Chang, C.C. Huang
Bonding pad crystal defect was observed on wafers before die saw. To eliminate and monitor the defect, a study was conducted to investigate the effect of humidity and packaging materials (packaging sponge and lint free paper material) on pad crystal defect generation. Ionic content specification of packaging sponge material was defined through the study. A setup for routine monitoring of pad crystal defect was constructed and implemented in wafer fabrication. The pad crystal defects were F rich. Humidity (>55%) was found to be an effective acceleration factor of the defect. With a 70% humidity stress test, a F content limit of 400 ppb in packaging sponge material was concluded to prevent defect generation. Air non-permeable lint free paper was found to provide further protection of the wafers from pad crystal defect.
{"title":"Bond pad F-crystal defect control and monitoring","authors":"J. Chen, L. Wei, Y. Chang, C.C. Huang","doi":"10.1109/ISSM.2001.962971","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962971","url":null,"abstract":"Bonding pad crystal defect was observed on wafers before die saw. To eliminate and monitor the defect, a study was conducted to investigate the effect of humidity and packaging materials (packaging sponge and lint free paper material) on pad crystal defect generation. Ionic content specification of packaging sponge material was defined through the study. A setup for routine monitoring of pad crystal defect was constructed and implemented in wafer fabrication. The pad crystal defects were F rich. Humidity (>55%) was found to be an effective acceleration factor of the defect. With a 70% humidity stress test, a F content limit of 400 ppb in packaging sponge material was concluded to prevent defect generation. Air non-permeable lint free paper was found to provide further protection of the wafers from pad crystal defect.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127518562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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