Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962995
M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda
Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.
{"title":"Floor layout planning method based on self-organization","authors":"M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda","doi":"10.1109/ISSM.2001.962995","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962995","url":null,"abstract":"Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128596919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962913
A. Imai, R. Miyamoto, K. Ozawa
This paper introduces a way to build a system that supports maintenance work in the most suitable and efficient way for future semiconductor factories with changing technologies. This system not only has improved the working efficiency of a maintenance section greatly, but practical use of the proposed system attained a greater rate of equipment availability, and improvement in maintenance costs. For future growth of the semiconductor industry, greater cooperation between the semiconductor manufacturer, components maker, and equipment maker will be indispensable. We wish to promote cooperation for improvement in the equipment operation rate, including the formation of data sharing schemes using Internet technology and an intranet between semiconductor manufacturer, equipment maker, and material supplier, and common analysis, and the practical use of existing data for a new line with the assistance of this system.
{"title":"Universal architecture to improve equipment maintenance work","authors":"A. Imai, R. Miyamoto, K. Ozawa","doi":"10.1109/ISSM.2001.962913","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962913","url":null,"abstract":"This paper introduces a way to build a system that supports maintenance work in the most suitable and efficient way for future semiconductor factories with changing technologies. This system not only has improved the working efficiency of a maintenance section greatly, but practical use of the proposed system attained a greater rate of equipment availability, and improvement in maintenance costs. For future growth of the semiconductor industry, greater cooperation between the semiconductor manufacturer, components maker, and equipment maker will be indispensable. We wish to promote cooperation for improvement in the equipment operation rate, including the formation of data sharing schemes using Internet technology and an intranet between semiconductor manufacturer, equipment maker, and material supplier, and common analysis, and the practical use of existing data for a new line with the assistance of this system.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125515747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963017
K. Maruo, Y. Maeda, M. Niwano
This paper presents a high-sensitivity organic contaminants detection method for clean room air. Using a Fourier Transform Infra-Red spectroscopy (FTIR), we can detect various chemical compounds including organic contaminants in a few minutes. In addition, by combining two efficient methods: Multiple Internal Reflection (MIR) and Cold Trap (CT), the sensitivity rate of detection chemical compounds rises drastically. By conducting experiments, it has been demonstrated that this sensitivity rate reaches to the order of ppb. This method will be used as an integral part of clean room air monitoring systems.
{"title":"High-sensitive organic contaminants detecting method based on cold-trap and multiple-internal-reflection FTIR [clean room air monitoring systems]","authors":"K. Maruo, Y. Maeda, M. Niwano","doi":"10.1109/ISSM.2001.963017","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963017","url":null,"abstract":"This paper presents a high-sensitivity organic contaminants detection method for clean room air. Using a Fourier Transform Infra-Red spectroscopy (FTIR), we can detect various chemical compounds including organic contaminants in a few minutes. In addition, by combining two efficient methods: Multiple Internal Reflection (MIR) and Cold Trap (CT), the sensitivity rate of detection chemical compounds rises drastically. By conducting experiments, it has been demonstrated that this sensitivity rate reaches to the order of ppb. This method will be used as an integral part of clean room air monitoring systems.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963004
Kye-Weon Kim, Yusin Yang, Chung Sam Chun, Sang Mun Chun, Dong Chun Lee, Sun-Yong Choi, S. Choi, Sung Jin Park
In CMP(Chemical Mechanical Polishing) process, if there are defects on the polishing pad, scratches are generated on the surface of the semiconductor wafer. We developed the inspection system of defects on the chemical mechanical polishing pad. The system uses a white light source and a CCD camera in order to inspect defects. We use the threshold method in order to find defects from images captured by the CCD camera, and the system can sort defects by size.
{"title":"Development of the inspection system of defects on a CMP (Chemical Mechanical Polishing) pad","authors":"Kye-Weon Kim, Yusin Yang, Chung Sam Chun, Sang Mun Chun, Dong Chun Lee, Sun-Yong Choi, S. Choi, Sung Jin Park","doi":"10.1109/ISSM.2001.963004","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963004","url":null,"abstract":"In CMP(Chemical Mechanical Polishing) process, if there are defects on the polishing pad, scratches are generated on the surface of the semiconductor wafer. We developed the inspection system of defects on the chemical mechanical polishing pad. The system uses a white light source and a CCD camera in order to inspect defects. We use the threshold method in order to find defects from images captured by the CCD camera, and the system can sort defects by size.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"67 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122543716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962947
K. Lensing, R. Markle, B. Stirton, M. Laughery
Focuses on the current roles of metrology systems associated with a shallow trench isolation (STI) run-to-run (RtR) controller and recent advances AMD has made applying new, ODP scatterometry-based metrology to this application. It will compare industry standard metrology techniques to ODP, with the objective of identifying the STI metrology system or systems that will produce timely and reliable data streams with the largest quantity of process information at the highest possible signal to noise (S/N) ratio.
{"title":"Shallow trench isolation scatterometry metrology in a high volume fab","authors":"K. Lensing, R. Markle, B. Stirton, M. Laughery","doi":"10.1109/ISSM.2001.962947","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962947","url":null,"abstract":"Focuses on the current roles of metrology systems associated with a shallow trench isolation (STI) run-to-run (RtR) controller and recent advances AMD has made applying new, ODP scatterometry-based metrology to this application. It will compare industry standard metrology techniques to ODP, with the objective of identifying the STI metrology system or systems that will produce timely and reliable data streams with the largest quantity of process information at the highest possible signal to noise (S/N) ratio.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962976
Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho
Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.
{"title":"A study on ILD process of simple and CMP skip using polysilazane-based SOG","authors":"Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho","doi":"10.1109/ISSM.2001.962976","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962976","url":null,"abstract":"Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132844684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962985
J. Bernstein, Joohan Lee
Some applications are presented for implementing a novel laser-programmable interconnect element (MakeLink/sup TM/) formed vertically between two standard metallization layers. The average electrical resistance for the smallest link is less than 10/spl Omega/ at optimal laser energy. Life tests under accelerating DC current densities and temperatures indicated high electromigration reliability. This technology is shown to be scaleable down to 1.5 /spl mu/m pitch based on commercially available laser systems. Finite element models of various structures were simulated and the results show that there exists an acceptable process window for any scaled link. Properties such as standard CMOS process compatibility, no programming circuit, high current handling capability, hermeticity and radiation hardness, make it useful in customizable devices and to replace laser fuses for yield enhancement and other rapid customization applications.
{"title":"A laser formed MakeLink* for customization and repair","authors":"J. Bernstein, Joohan Lee","doi":"10.1109/ISSM.2001.962985","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962985","url":null,"abstract":"Some applications are presented for implementing a novel laser-programmable interconnect element (MakeLink/sup TM/) formed vertically between two standard metallization layers. The average electrical resistance for the smallest link is less than 10/spl Omega/ at optimal laser energy. Life tests under accelerating DC current densities and temperatures indicated high electromigration reliability. This technology is shown to be scaleable down to 1.5 /spl mu/m pitch based on commercially available laser systems. Finite element models of various structures were simulated and the results show that there exists an acceptable process window for any scaled link. Properties such as standard CMOS process compatibility, no programming circuit, high current handling capability, hermeticity and radiation hardness, make it useful in customizable devices and to replace laser fuses for yield enhancement and other rapid customization applications.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126380276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963020
H. Sugawara, Y. Tajima, T. Ohmi
A tetramethylammonium hydroxide (TMAH) generally used as photoresist developer for manufacturing LSIs and LCDs is recovered from developer waste (spent developer) using an electrodialysis (ED) method, and purified by ion exchange (IE) technologies. Reclaimed developer features analytically the same purity as commercial fresh one. This reclamation system can achieve a stably high TMAH recovery rate of more than 80%. Furthermore, it has the great advantages of saving operating costs, which amounts to 66.2% (for LSI) and 78.3% (for LCD) total cost reduction compared with conventional no reclamation system in a case study, as well as reducing environmental load.
{"title":"Photoresist developer reclamation technology and system","authors":"H. Sugawara, Y. Tajima, T. Ohmi","doi":"10.1109/ISSM.2001.963020","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963020","url":null,"abstract":"A tetramethylammonium hydroxide (TMAH) generally used as photoresist developer for manufacturing LSIs and LCDs is recovered from developer waste (spent developer) using an electrodialysis (ED) method, and purified by ion exchange (IE) technologies. Reclaimed developer features analytically the same purity as commercial fresh one. This reclamation system can achieve a stably high TMAH recovery rate of more than 80%. Furthermore, it has the great advantages of saving operating costs, which amounts to 66.2% (for LSI) and 78.3% (for LCD) total cost reduction compared with conventional no reclamation system in a case study, as well as reducing environmental load.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134576537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962919
T. Sada, R. A. Yuen, M. Ichikawa, M. Yamada, K. Kabata
This paper describes a simple and easy to understand technique of achieving cycle time reduction in a semiconductor fab. The technique uses a spreadsheet that calculates theoretical queue time (based on operations research queuing theory) with consideration to the negative effect of very high priority lots ("super hot lots"). The theoretical queue time is compared with actual queue times to identify factory bottlenecks and the best opportunities for cycle time improvement. When this queue time control was introduced, jab cycle time improved 24%.
{"title":"Simple tool of analysis for cycle time reduction","authors":"T. Sada, R. A. Yuen, M. Ichikawa, M. Yamada, K. Kabata","doi":"10.1109/ISSM.2001.962919","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962919","url":null,"abstract":"This paper describes a simple and easy to understand technique of achieving cycle time reduction in a semiconductor fab. The technique uses a spreadsheet that calculates theoretical queue time (based on operations research queuing theory) with consideration to the negative effect of very high priority lots (\"super hot lots\"). The theoretical queue time is compared with actual queue times to identify factory bottlenecks and the best opportunities for cycle time improvement. When this queue time control was introduced, jab cycle time improved 24%.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133525803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962948
H. Tomita, M. Sato, S. Nadahara, T. Saitoh
Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.
{"title":"Photoresist stripping using novel sulfuric/ozone process","authors":"H. Tomita, M. Sato, S. Nadahara, T. Saitoh","doi":"10.1109/ISSM.2001.962948","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962948","url":null,"abstract":"Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133441865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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