Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962932
Runzi Chang, C. Spanos
Chemical mechanical polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130 nm feature sizes. We present the application of a library-based specular spectroscopic scatterometry method, which is capable of getting a clear view of the profile evolution due to the oxide CMP process. This level of analysis will be crucial in building a rigorous CMP model in the near future.
{"title":"Full profile inter-layer dielectric CMP analysis","authors":"Runzi Chang, C. Spanos","doi":"10.1109/ISSM.2001.962932","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962932","url":null,"abstract":"Chemical mechanical polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130 nm feature sizes. We present the application of a library-based specular spectroscopic scatterometry method, which is capable of getting a clear view of the profile evolution due to the oxide CMP process. This level of analysis will be crucial in building a rigorous CMP model in the near future.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962991
T. Wang, T. Hsieh, Y. Wang, C.W. Liu, K. Lo, J.K. Wang, W. Lee
Chemical Mechanical Polishing (CMP) is widely used for global planarization in IC device structure. A pad conditioner is often used to remove polishing debris, and hence preventing the pad surface from glazing. The proper conditioning can assure the pad surface like new so it can hold slurry evenly for effective polishing. Diamond disks are commonly used for conditioning the CMP pads. The designs of diamond disks are critical as it determines the efficiency of the grooving action. All conventional diamond disks contain grits that are distributed randomly. A novel disk provided a regular diamond grits. They are set with a fixed diamond distance and diamond protrusion. These characteristics provide a smoothly slurry distribution and conditioning efficiency. Tungsten chemical mechanical polishing (WCMP) is used for W burden removal, but also is a challenging process due to metal-binder's corrosion on diamond disk during pad conditioning. Diamond segregation and diamond pullouts arising from metal dissolution of diamond disk not only make the conditioning inefficient, but also damage and contaminate the polished wafer surface. It is a major yield killer for deep sub-micro device. In this study, the new disk made by the novel diamond grid technology with a fixed diamond size and pitch appears feasible for in-situ WCMP application. It shows a relationship of polish performance between diamond size & diamond pitch. The higher polish performance got as diamond size decreasing and increasing working efficiency.
{"title":"A novel pad conditioning disk design of tungsten chemical mechanical polishing process for deep sub-micron device yield improvement","authors":"T. Wang, T. Hsieh, Y. Wang, C.W. Liu, K. Lo, J.K. Wang, W. Lee","doi":"10.1109/ISSM.2001.962991","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962991","url":null,"abstract":"Chemical Mechanical Polishing (CMP) is widely used for global planarization in IC device structure. A pad conditioner is often used to remove polishing debris, and hence preventing the pad surface from glazing. The proper conditioning can assure the pad surface like new so it can hold slurry evenly for effective polishing. Diamond disks are commonly used for conditioning the CMP pads. The designs of diamond disks are critical as it determines the efficiency of the grooving action. All conventional diamond disks contain grits that are distributed randomly. A novel disk provided a regular diamond grits. They are set with a fixed diamond distance and diamond protrusion. These characteristics provide a smoothly slurry distribution and conditioning efficiency. Tungsten chemical mechanical polishing (WCMP) is used for W burden removal, but also is a challenging process due to metal-binder's corrosion on diamond disk during pad conditioning. Diamond segregation and diamond pullouts arising from metal dissolution of diamond disk not only make the conditioning inefficient, but also damage and contaminate the polished wafer surface. It is a major yield killer for deep sub-micro device. In this study, the new disk made by the novel diamond grid technology with a fixed diamond size and pitch appears feasible for in-situ WCMP application. It shows a relationship of polish performance between diamond size & diamond pitch. The higher polish performance got as diamond size decreasing and increasing working efficiency.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116768364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963026
J.L. Dauphinee
In 1997, a group of senior managers from the worldwide locations of the IBM Microelectronics Division established a team to investigate and improve manufacturing operator training. Emphasis was placed on developing and implementing a sustained process with continuous improvement. The team chose both project management and process maturity disciplines to guide the development and implementation of a sustainable training process.
{"title":"Development and implementation of a sustainable operator training and certification process","authors":"J.L. Dauphinee","doi":"10.1109/ISSM.2001.963026","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963026","url":null,"abstract":"In 1997, a group of senior managers from the worldwide locations of the IBM Microelectronics Division established a team to investigate and improve manufacturing operator training. Emphasis was placed on developing and implementing a sustained process with continuous improvement. The team chose both project management and process maturity disciplines to guide the development and implementation of a sustainable training process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121181897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962946
K. Monahan, A. Engineer, Georges Falessi, M. Hankinson, Sung Jin Lee, A. Levy, M. Slessor
Previously, we developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.
{"title":"Microeconomics of accelerated shrinks in demand-limited markets","authors":"K. Monahan, A. Engineer, Georges Falessi, M. Hankinson, Sung Jin Lee, A. Levy, M. Slessor","doi":"10.1109/ISSM.2001.962946","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962946","url":null,"abstract":"Previously, we developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962925
S. Wilson
Mean time to repair, mean time to repeat failure/repair, time to first failure after PM (preventative maintenance), and tool availability - the need to link these topics to training and other performance interventions is becoming paramount. How do we know that the time a technician spends in training (or other performance intervention) is worth it? As Intel continuously strives for improvement, departments are asked to prove their impact in terms of business/factory pay-offs. This paper discusses a successful project at Intel in which training was evaluated in terms of equipment indicator improvements, namely: average availability increase across AWX (Automated Wet Station/Bench) tools of 4.25% (which equated /spl sim/8 additional hours of production time/week).Variation in availability declined by an average 4.4% across the AWX tools.
{"title":"Talking shop - linking training to factory indicators","authors":"S. Wilson","doi":"10.1109/ISSM.2001.962925","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962925","url":null,"abstract":"Mean time to repair, mean time to repeat failure/repair, time to first failure after PM (preventative maintenance), and tool availability - the need to link these topics to training and other performance interventions is becoming paramount. How do we know that the time a technician spends in training (or other performance intervention) is worth it? As Intel continuously strives for improvement, departments are asked to prove their impact in terms of business/factory pay-offs. This paper discusses a successful project at Intel in which training was evaluated in terms of equipment indicator improvements, namely: average availability increase across AWX (Automated Wet Station/Bench) tools of 4.25% (which equated /spl sim/8 additional hours of production time/week).Variation in availability declined by an average 4.4% across the AWX tools.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126857037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962921
Kong Pin, Lee Yen Fei, Ang Chee Teck
The paper presents two approaches to determine the foundry fab manufacturing production plan. The two approaches are namely, the Cycle Time Oriented (CTO) method the WIP Energy Oriented (WEO) method. The objective of CTO method is to derive a model with the consideration in the aspects of the master production plan (MPP) and cycle time (CT). On the other hand, the WEO model explores the consideration of the WIP balancing and linear wafer out (or planned wafer out) to determine the amount of stage-moves demand. The concepts and models were built and applied over a period in SSMC and therefore, giving birth to a complete study for manufacturing production plan.
{"title":"Two approaches to determine appropriated fab manufacturing production plan by cycle-time and WIP energy","authors":"Kong Pin, Lee Yen Fei, Ang Chee Teck","doi":"10.1109/ISSM.2001.962921","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962921","url":null,"abstract":"The paper presents two approaches to determine the foundry fab manufacturing production plan. The two approaches are namely, the Cycle Time Oriented (CTO) method the WIP Energy Oriented (WEO) method. The objective of CTO method is to derive a model with the consideration in the aspects of the master production plan (MPP) and cycle time (CT). On the other hand, the WEO model explores the consideration of the WIP balancing and linear wafer out (or planned wafer out) to determine the amount of stage-moves demand. The concepts and models were built and applied over a period in SSMC and therefore, giving birth to a complete study for manufacturing production plan.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"30 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131318921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962924
Chung-Shen Wu, Da-Yin Liao
This paper presents an effective monitor operations automation system (MOAS) which is being developed for automatic monitor management in a 300 mm mass production fab in tsmc. Continuing the previous study of on 300 mm monitor automation, it is implemented by integrating with advanced 300 mm CIM systems as well as functions. MOAS demonstrates its capability as a key driver to realize the automation of complex fab monitor operations.
{"title":"An automatic monitor management system for effective 300 mm fab operations","authors":"Chung-Shen Wu, Da-Yin Liao","doi":"10.1109/ISSM.2001.962924","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962924","url":null,"abstract":"This paper presents an effective monitor operations automation system (MOAS) which is being developed for automatic monitor management in a 300 mm mass production fab in tsmc. Continuing the previous study of on 300 mm monitor automation, it is implemented by integrating with advanced 300 mm CIM systems as well as functions. MOAS demonstrates its capability as a key driver to realize the automation of complex fab monitor operations.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124807575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962992
R. Bachrach, M. Pool, K. Genovese, J.C. Moran, M. O'Halloran, T. J. Connolly
A semiconductor fabricator is a highly complex system that hosts the process tools capable of manufacturing IC product devices based upon their process flows. A typical process flow for a 0.15 /spl mu/m logic process consists of 300 to 400 steps with 22 to 24 mask steps. A variety of equipment sets and organizational architectures are possible for any process flow. The results of a comparative analysis of two such 300 mm FAB architectures are presented in this report. The impact of equipment sets on fab Sizing, Cost, and Performance are described as a function of operating characteristics.
{"title":"Comparative analysis of 300 mm FAB architectures impact of equipment sets on wafer cost and dynamic performance","authors":"R. Bachrach, M. Pool, K. Genovese, J.C. Moran, M. O'Halloran, T. J. Connolly","doi":"10.1109/ISSM.2001.962992","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962992","url":null,"abstract":"A semiconductor fabricator is a highly complex system that hosts the process tools capable of manufacturing IC product devices based upon their process flows. A typical process flow for a 0.15 /spl mu/m logic process consists of 300 to 400 steps with 22 to 24 mask steps. A variety of equipment sets and organizational architectures are possible for any process flow. The results of a comparative analysis of two such 300 mm FAB architectures are presented in this report. The impact of equipment sets on fab Sizing, Cost, and Performance are described as a function of operating characteristics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963003
R. Noben, R. van Driel, T. Claasen-Vujcic
In order to improve cycle time in the furnace area, two alternatives are evaluated. Mini batch manufacturing and integrated metrology can both save valuable time. Dynamic simulations are used to investigate the influence of both options. The results are a cycle time improvement when going front large batch to mini batch manufacturing. The gain is up to 40% for normal lots and up to 30% for hot lots wafers. The consequence is an increase in the number of required tubes. Cycle time improvement versus costs is analysed. The cost of one hour cycle time gain is determined. Integrated metrology can save approximately 5-10% on the average cycle time.
{"title":"Cycle time advantages of mini batch manufacturing and integrated metrology in a 300 mm vertical furnace","authors":"R. Noben, R. van Driel, T. Claasen-Vujcic","doi":"10.1109/ISSM.2001.963003","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963003","url":null,"abstract":"In order to improve cycle time in the furnace area, two alternatives are evaluated. Mini batch manufacturing and integrated metrology can both save valuable time. Dynamic simulations are used to investigate the influence of both options. The results are a cycle time improvement when going front large batch to mini batch manufacturing. The gain is up to 40% for normal lots and up to 30% for hot lots wafers. The consequence is an increase in the number of required tubes. Cycle time improvement versus costs is analysed. The cost of one hour cycle time gain is determined. Integrated metrology can save approximately 5-10% on the average cycle time.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121210171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963015
S. Yajima, T. Nakano, K. Sadachi, Y. Ikura, H. Miura, A. Tomozawa
During the drastic product change from memory devices to discrete devices, we have made various technical improvements in photolithography processing corresponding to its design characteristics, as follows: (1) establishment of fine gate processing technology; (2) optimization of throughput and processing accuracy using new photoresist processing customized for each step; and (3) establishment of flexible stepper application methods aimed at products-change-free production. Consequently, we have obtained the following beneficial results: (1) processing of 0.25 /spl mu/m discrete devices has been set up without KrF lithography; (2) a 198% improvement in stepper throughput has been achieved; and (3) a 58% reduction of waiting time has been obtained.
{"title":"Throughput improvement in photolithography processing for flexible production","authors":"S. Yajima, T. Nakano, K. Sadachi, Y. Ikura, H. Miura, A. Tomozawa","doi":"10.1109/ISSM.2001.963015","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963015","url":null,"abstract":"During the drastic product change from memory devices to discrete devices, we have made various technical improvements in photolithography processing corresponding to its design characteristics, as follows: (1) establishment of fine gate processing technology; (2) optimization of throughput and processing accuracy using new photoresist processing customized for each step; and (3) establishment of flexible stepper application methods aimed at products-change-free production. Consequently, we have obtained the following beneficial results: (1) processing of 0.25 /spl mu/m discrete devices has been set up without KrF lithography; (2) a 198% improvement in stepper throughput has been achieved; and (3) a 58% reduction of waiting time has been obtained.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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