Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962980
A. Shimazaki, H. Sakurai, K. Nishiki, S. Nadahara
It was revealed that Ru chemical vapor deposition (CVD) furnace affected cleanliness of "ball room" type cleanroom. Ru airborne contamination behaves as mists or molecules unlike Fe contamination which behaves as particles. Ru contamination is accumulated in the cleanroom and it is easy to spread and to circulate as airborne contamination in the cleanroom. Completely closed system of Ru CVD furnace should be developed to shut out Ru contamination. It was found that activated carbon filter (AC) was effective to trap this Ru airborne contamination for mini-environment system of the manufacturing equipments in the "ball room" type cleanroom for production.
{"title":"Controlling Ru airborne contamination in cleanroom","authors":"A. Shimazaki, H. Sakurai, K. Nishiki, S. Nadahara","doi":"10.1109/ISSM.2001.962980","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962980","url":null,"abstract":"It was revealed that Ru chemical vapor deposition (CVD) furnace affected cleanliness of \"ball room\" type cleanroom. Ru airborne contamination behaves as mists or molecules unlike Fe contamination which behaves as particles. Ru contamination is accumulated in the cleanroom and it is easy to spread and to circulate as airborne contamination in the cleanroom. Completely closed system of Ru CVD furnace should be developed to shut out Ru contamination. It was found that activated carbon filter (AC) was effective to trap this Ru airborne contamination for mini-environment system of the manufacturing equipments in the \"ball room\" type cleanroom for production.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126389318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962909
C. Spanos, P. Jula, R. Leachman
Metrology tools and practices are expected to migrate from off-line to inline and ultimately to in situ. Economic models are needed to study the costs and benefits of introducing new metrology technologies and to compare alternative metrology practices. Several qualitative and quantitative models are presented in this paper to study the elements of revenue and cost associated with different metrology tools and practices. Comparisons between in situ, inline and off-line metrology systems are made. Monte Carlo simulation models are used to study each system under different scenarios.
{"title":"The economic impact of choosing off-line, inline or in situ metrology deployment in semiconductor manufacturing","authors":"C. Spanos, P. Jula, R. Leachman","doi":"10.1109/ISSM.2001.962909","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962909","url":null,"abstract":"Metrology tools and practices are expected to migrate from off-line to inline and ultimately to in situ. Economic models are needed to study the costs and benefits of introducing new metrology technologies and to compare alternative metrology practices. Several qualitative and quantitative models are presented in this paper to study the elements of revenue and cost associated with different metrology tools and practices. Comparisons between in situ, inline and off-line metrology systems are made. Monte Carlo simulation models are used to study each system under different scenarios.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962928
T. Nakamura
Because it minimizes the spaces between transistors, the aspect ratio of shallow trench isolation (STI) becomes large and it gets difficult to fill STI by conventional LP-CVD TEOS SiO/sub 2/ film without void formation. A high-density plasma deposition process has been evaluated for better STI fill instead of LP-CVD, however, the new equipment costs more than that for LP-CVD. This paper describes a new technique, a pulse pressure chemical vapor deposition (CVD) method for STI fill without forming any voids by using conventional LP-CVD equipment. Pulse pressure enables a uniform source gas supply to the STI trench and a conformal film deposition without voids.
由于晶体管之间的空间最小化，使得浅沟槽隔离(STI)的宽高比变大，传统的LP-CVD TEOS SiO/sub /薄膜很难在不形成空洞的情况下填充STI。高密度等离子体沉积工艺已被评估为更好的STI填充而不是LP-CVD，然而，新设备的成本高于LP-CVD。本文介绍了脉冲压力化学气相沉积(CVD)技术在常规LP-CVD设备上不形成任何空隙的情况下进行STI填充的新技术。脉冲压力能够为STI沟槽提供均匀的气源，并实现无空洞的保形膜沉积。
{"title":"Novel pulse pressure CVD for void free STI trench TEOS fill","authors":"T. Nakamura","doi":"10.1109/ISSM.2001.962928","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962928","url":null,"abstract":"Because it minimizes the spaces between transistors, the aspect ratio of shallow trench isolation (STI) becomes large and it gets difficult to fill STI by conventional LP-CVD TEOS SiO/sub 2/ film without void formation. A high-density plasma deposition process has been evaluated for better STI fill instead of LP-CVD, however, the new equipment costs more than that for LP-CVD. This paper describes a new technique, a pulse pressure chemical vapor deposition (CVD) method for STI fill without forming any voids by using conventional LP-CVD equipment. Pulse pressure enables a uniform source gas supply to the STI trench and a conformal film deposition without voids.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131306882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962945
K. Kuhn, D. Mei, I. Post, J. Neirynck
Scaling shallow trench isolation (STI) from the 0.18 /spl mu/m to 0.13 /spl mu/m generation has offered many new challenges for semiconductor manufacturing. Two are discussed in this paper. The first is delivering a capable gapfill process for high aspect ratio trenches while maintaining isolation punchthrough margin (as well as low junction capacitance). The second is trading off NMOS mobility degradation generated by the use of compressive HDP films against the improved gapfill, wet-etch, and polish properties of these films.
{"title":"Scaling challenges for 0.13 /spl mu/m generation shallow trench isolation","authors":"K. Kuhn, D. Mei, I. Post, J. Neirynck","doi":"10.1109/ISSM.2001.962945","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962945","url":null,"abstract":"Scaling shallow trench isolation (STI) from the 0.18 /spl mu/m to 0.13 /spl mu/m generation has offered many new challenges for semiconductor manufacturing. Two are discussed in this paper. The first is delivering a capable gapfill process for high aspect ratio trenches while maintaining isolation punchthrough margin (as well as low junction capacitance). The second is trading off NMOS mobility degradation generated by the use of compressive HDP films against the improved gapfill, wet-etch, and polish properties of these films.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131867383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963018
N. Mori, Y. Imakawa, T. Fujimori, I. Ootake, O. Suenaga, T. Ohmi, H. Itoh, M. Takahashi
The energy balance in vertical oxidation furnaces in a semiconductor fab under full scale operation was measured for the heat loads for cooling water, exhaust air and clean room air, which have not yet fully been reported. The results showed that the heat generated from the furnaces was removed with ratio of 64% by cooling water, 14% by exhausting air and 22% by clean room air, indicating very similar values measured in a laboratory scale operation reported by the authors at ISSM'99. Based on these results, the amount of energy saving was estimated by applying the energy saving methods proposed at ISSM'99. More than 35% of energy consumption can be reduced, which corresponds to more than 50% reduction of CO/sub 2/ release or 50% operation cost reduction compared to the current system.
{"title":"A fact-finding survey on the heat generation from processing equipment at a semiconductor fab under operation","authors":"N. Mori, Y. Imakawa, T. Fujimori, I. Ootake, O. Suenaga, T. Ohmi, H. Itoh, M. Takahashi","doi":"10.1109/ISSM.2001.963018","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963018","url":null,"abstract":"The energy balance in vertical oxidation furnaces in a semiconductor fab under full scale operation was measured for the heat loads for cooling water, exhaust air and clean room air, which have not yet fully been reported. The results showed that the heat generated from the furnaces was removed with ratio of 64% by cooling water, 14% by exhausting air and 22% by clean room air, indicating very similar values measured in a laboratory scale operation reported by the authors at ISSM'99. Based on these results, the amount of energy saving was estimated by applying the energy saving methods proposed at ISSM'99. More than 35% of energy consumption can be reduced, which corresponds to more than 50% reduction of CO/sub 2/ release or 50% operation cost reduction compared to the current system.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130528134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962935
K. Nakao, T. Asano, H. Fukushima, H. Yamamoto, A. Dip, R. Joe, D. O'Meara, R. Soave, S. Kaushal
A new concept in multi-wafer (MW) rapid thermal processing (RTP) is presented. An innovative approach to hot-wall, isothermal processing technology advances the conventional large batch environment into the realm of RTP processing. Using recent developments in heater technology along with advancements in other critical processing areas, a method for processing a lot (25 wafers) within an hour in a hot-wall RTP environment is demonstrated.
{"title":"Multi-wafer rapid isothermal processing","authors":"K. Nakao, T. Asano, H. Fukushima, H. Yamamoto, A. Dip, R. Joe, D. O'Meara, R. Soave, S. Kaushal","doi":"10.1109/ISSM.2001.962935","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962935","url":null,"abstract":"A new concept in multi-wafer (MW) rapid thermal processing (RTP) is presented. An innovative approach to hot-wall, isothermal processing technology advances the conventional large batch environment into the realm of RTP processing. Using recent developments in heater technology along with advancements in other critical processing areas, a method for processing a lot (25 wafers) within an hour in a hot-wall RTP environment is demonstrated.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963008
Y. Kaplan
The QUEST System provides a web-based platform for the standardized management, tracking and assessment of quality excursion events across an entire Fab. The system has become the pivot of Intel Corporation Fab18's quality excursion event management and is now in the process of implementation in other factories.
{"title":"The QUEST System in Intel Fab18: a web-based method for the management of quality","authors":"Y. Kaplan","doi":"10.1109/ISSM.2001.963008","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963008","url":null,"abstract":"The QUEST System provides a web-based platform for the standardized management, tracking and assessment of quality excursion events across an entire Fab. The system has become the pivot of Intel Corporation Fab18's quality excursion event management and is now in the process of implementation in other factories.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962914
Shin Hayashi, Y. Tanaka, E. Kodama
Primary productivity in the semiconductor manufacturing industry, which includes cycle time, cost and production, depends to a great extent on the capability of manufacturing administrators (MA), particularly with regard to the critical trade-off between cycle time and tool utilization. The Mahalanobis distance (MD) has significance in pattern recognition, and we have found a method to make use of the MD as the core of a manufacturing control system. By using this system, we can easily distinguish deviations from normality in respect of productivity, specify the root cause of the abnormality and decide how to prioritize the problem. As a result, we can efficiently concentrate limited resources on the root cause in the absence of a capable MA, and restore productivity on a minimum timescale.
{"title":"A new manufacturing control system using Mahalanobis distance for maximising productivity","authors":"Shin Hayashi, Y. Tanaka, E. Kodama","doi":"10.1109/ISSM.2001.962914","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962914","url":null,"abstract":"Primary productivity in the semiconductor manufacturing industry, which includes cycle time, cost and production, depends to a great extent on the capability of manufacturing administrators (MA), particularly with regard to the critical trade-off between cycle time and tool utilization. The Mahalanobis distance (MD) has significance in pattern recognition, and we have found a method to make use of the MD as the core of a manufacturing control system. By using this system, we can easily distinguish deviations from normality in respect of productivity, specify the root cause of the abnormality and decide how to prioritize the problem. As a result, we can efficiently concentrate limited resources on the root cause in the absence of a capable MA, and restore productivity on a minimum timescale.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962904
K. Andou, H. Kondo, T. Masui
300 mm semiconductor factories require the combination of different types of AMHS (Automated Material Handling System) components from different suppliers for optimal AMHS solutions. To realize it, interoperable communication specification for AMHS is required. Selete (Semiconductor Leading Edge Technologies, Inc) has developed it by discussing with member companies of Selete and cooperative AMHS vendors about implementation level requirement specifications, and confirming its interoperability by evaluating actual behaviors of AMHS components in which the above mentioned specifications are implemented. This specification contributes to reduce the cost and time of the communication interface development in AMHS vendors and semiconductor manufacturers when AMHS components from two or more vendors are combined.
300mm半导体工厂需要来自不同供应商的不同类型的AMHS(自动物料搬运系统)组件的组合，以获得最佳的AMHS解决方案。为了实现这一目标，需要有可互操作的AMHS通信规范。Selete (Semiconductor Leading Edge Technologies, Inc)通过与Selete成员公司和AMHS合作供应商讨论实现级需求规范，并通过评估实现上述规范的AMHS组件的实际行为来确认其互操作性，开发了该规范。当来自两个或多个供应商的AMHS组件合并时，该规范有助于减少AMHS供应商和半导体制造商的通信接口开发成本和时间。
{"title":"Interoperable communication specification for AMHS","authors":"K. Andou, H. Kondo, T. Masui","doi":"10.1109/ISSM.2001.962904","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962904","url":null,"abstract":"300 mm semiconductor factories require the combination of different types of AMHS (Automated Material Handling System) components from different suppliers for optimal AMHS solutions. To realize it, interoperable communication specification for AMHS is required. Selete (Semiconductor Leading Edge Technologies, Inc) has developed it by discussing with member companies of Selete and cooperative AMHS vendors about implementation level requirement specifications, and confirming its interoperability by evaluating actual behaviors of AMHS components in which the above mentioned specifications are implemented. This specification contributes to reduce the cost and time of the communication interface development in AMHS vendors and semiconductor manufacturers when AMHS components from two or more vendors are combined.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133578186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962981
M.M. Touzov, T. Fujita, T.K. Doy
This study presents a new approach to edge profile control during air back carrier Chemical Mechanical Polishing (CMP). Control of wafer edge profile proves to be difficult as different factors are reported to influence polishing characteristics. To evaluate a CMP on the wafer's edge it needs to look at polish characteristics of leading and trailing edges separately. To understand polish performance on both leading and trailing edges, and their impact on resulting wafer's edge profile a non-rotating carrier experiment had been conducted. Based on the results of the nonrotating carrier experiment a novel retaining ring design has been proposed. In the course of this study CMP of the wafer's edge evaluation for a novel retaining ring has been performed on blanket PETEOS 200 mm wafers for different retaining pressures. Edge profile evaluation provided a proof for the Pad Wave Hypothesis and helped to significantly enhance the CMP performance by increasing process stability and achieving wider process window for retaining ring pressure.
{"title":"Novel retaining ring to reduce CMP edge exclusion","authors":"M.M. Touzov, T. Fujita, T.K. Doy","doi":"10.1109/ISSM.2001.962981","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962981","url":null,"abstract":"This study presents a new approach to edge profile control during air back carrier Chemical Mechanical Polishing (CMP). Control of wafer edge profile proves to be difficult as different factors are reported to influence polishing characteristics. To evaluate a CMP on the wafer's edge it needs to look at polish characteristics of leading and trailing edges separately. To understand polish performance on both leading and trailing edges, and their impact on resulting wafer's edge profile a non-rotating carrier experiment had been conducted. Based on the results of the nonrotating carrier experiment a novel retaining ring design has been proposed. In the course of this study CMP of the wafer's edge evaluation for a novel retaining ring has been performed on blanket PETEOS 200 mm wafers for different retaining pressures. Edge profile evaluation provided a proof for the Pad Wave Hypothesis and helped to significantly enhance the CMP performance by increasing process stability and achieving wider process window for retaining ring pressure.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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