Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729911
E. Aydil, D. Marra
Plasma etching of silicon dioxide using fluorocarbon gas containing discharges is an important process in integrated circuit manufacturing. Except for subtle differences, many gas mixtures that contain fluorocarbon gases such as CnFzn+2 (n>O) and CHF3 exhibit similar etching behavior.lT2 During etching with these gases, a thin steady state layer that contains fluorocarbon moieties forms on the ~urface."~ Even in presence of such a layer, thin films of silicon, silicon dioxide and silicon nitride can be etched with rates as large as several thousands of Ang~tromdmin.~.~ However, under conditions that favor fluorocarbon polymerization, such as low energy ion bombardment, a continuous layer of a fluorocarbon film can deposit on the surface and inhibit the etching of the underlying film.'-7 It has been suggested and widely adopted that the etch inhibition results when the thin steady-state fluorocarbon layer that forms during etching becomes too thick to allow the etchant and the etching products to diffuse through this layer.3'436,7 The nature of these steady-state and etch-inhibiting overlayers has been the subject of many studies and vigorous debate over the last two decades. The conditions that favor etch inhibition on various films have been discovered by trial and error. For example, it is well known that the addition of HZ to the etching gas tends to promote the formation of an etch inhibiting film whereas an increase in ion bombardment and ion flux to the surface decreases the tendency of these layers to grow. The formation of the etch inhibiting layer can also depend on the film being etched. For example, in the presence of ion bombardment, the etch-inhibiting layer forms easier on Si than on silicon dioxide and this fact has been exploited to etch silicon dioxide selectively over Si.*
{"title":"Nature Of The Silicon And Silicon Dioxide Surfaces During Plasma Etching With Fluorocarbon Containing Discharges","authors":"E. Aydil, D. Marra","doi":"10.1109/IMNC.1998.729911","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729911","url":null,"abstract":"Plasma etching of silicon dioxide using fluorocarbon gas containing discharges is an important process in integrated circuit manufacturing. Except for subtle differences, many gas mixtures that contain fluorocarbon gases such as CnFzn+2 (n>O) and CHF3 exhibit similar etching behavior.lT2 During etching with these gases, a thin steady state layer that contains fluorocarbon moieties forms on the ~urface.\"~ Even in presence of such a layer, thin films of silicon, silicon dioxide and silicon nitride can be etched with rates as large as several thousands of Ang~tromdmin.~.~ However, under conditions that favor fluorocarbon polymerization, such as low energy ion bombardment, a continuous layer of a fluorocarbon film can deposit on the surface and inhibit the etching of the underlying film.'-7 It has been suggested and widely adopted that the etch inhibition results when the thin steady-state fluorocarbon layer that forms during etching becomes too thick to allow the etchant and the etching products to diffuse through this layer.3'436,7 The nature of these steady-state and etch-inhibiting overlayers has been the subject of many studies and vigorous debate over the last two decades. The conditions that favor etch inhibition on various films have been discovered by trial and error. For example, it is well known that the addition of HZ to the etching gas tends to promote the formation of an etch inhibiting film whereas an increase in ion bombardment and ion flux to the surface decreases the tendency of these layers to grow. The formation of the etch inhibiting layer can also depend on the film being etched. For example, in the presence of ion bombardment, the etch-inhibiting layer forms easier on Si than on silicon dioxide and this fact has been exploited to etch silicon dioxide selectively over Si.*","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730030
Sangwoong Lee, Sangjun Park, D. Cho
tract :new micromachining technology using (1 1 1)-oriented silicon is developed. The technology utilizes reactive ion etching (RIE) for patterning of microstructures to be released from the substrate, followed h y KOH wet etching of bulk silicon under the patterns to release the microstructures. The advantage of technique is that the microstructures are of single crystalline silicon. Furthermore, unlike bulk ranisotropic etching that can fabricate patterns limited by crystallographic directions, this technique can pattern vertical-walled, arbitrarily-shaped patterns. The pattern depth is limited by RIE, but the recent deep RIE processes can fabricate structures from sub-pn to 500pm depth. This compares favorably with polysilicon micromachining which is generally limited to a thickness of < 10pm. The release of microstructure is accomplished by an aqueous alkaline etch, and the gap between the substrate and microstructure is precisely controlled to almost any distance by RIE. The release etch utilize the high etch selectivity of { I 1 I} planes to (100) and {I IO} planes, and therefore, large plates can be released without additional etch holes, and with smooth structure undersurface and smooth substrate support surfaces . To understand the process, consider the two equilateral triangles bounded by {I 1I} planes of (1 11)oriented silicon as shown in Figure 1. Note that the various {I 1I } planes are tilted at f 19.47' angles from the vertical as indicated. Now consider a pattern opening shown in Figure 2. The pattern is micromachined using RIE processes, and partial nitride passivation performed as shown in Figure 3. If this structure is wet etched in an aqueous alkaline etchant, the pattern is released as in Figure 4. Due to the space limitation, a detailed flow sequence is not shown. Figure 5 shows fabricated single crystalline microbridges. Figure 5 (a) shows a released bridge. The dimensions are: length 55pm, width 20pm, and thickness 4 p . The gap to the substrate is 2pm. Figure 5 (b) shows a bridge with dimensions: 260pm length, 50pm width, and ,4pm thickness. The SEM shows that 260pm x 50pm is released, but that the bridge is stuck to the substrate because of the stiction caused by wet etching. This problem can be improved by the use of sublimation or super critical drying techniques, or by simply making the gap larger. Also note that because the micromachining technology relies on RIE for shape patterning and crystallography-dependent anisotropic etching, all shapes are sharply defined and all surfaces are clear. Other shapes including comb drives can be easily fabricated using this technique. This paper developed a new micromachining technology using (1 11)-oriented silicon for the first time. The technology combines the advantages of dry RIE processes and crystallography of silicon to fabricate sharply-defined, arbitrarily-shaped, released, single-crystalline silicon microstructures. This technology offers much potential as an alternati
{"title":"A New Micromachining Technology Using","authors":"Sangwoong Lee, Sangjun Park, D. Cho","doi":"10.1109/IMNC.1998.730030","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730030","url":null,"abstract":"tract :new micromachining technology using (1 1 1)-oriented silicon is developed. The technology utilizes reactive ion etching (RIE) for patterning of microstructures to be released from the substrate, followed h y KOH wet etching of bulk silicon under the patterns to release the microstructures. The advantage of technique is that the microstructures are of single crystalline silicon. Furthermore, unlike bulk ranisotropic etching that can fabricate patterns limited by crystallographic directions, this technique can pattern vertical-walled, arbitrarily-shaped patterns. The pattern depth is limited by RIE, but the recent deep RIE processes can fabricate structures from sub-pn to 500pm depth. This compares favorably with polysilicon micromachining which is generally limited to a thickness of < 10pm. The release of microstructure is accomplished by an aqueous alkaline etch, and the gap between the substrate and microstructure is precisely controlled to almost any distance by RIE. The release etch utilize the high etch selectivity of { I 1 I} planes to (100) and {I IO} planes, and therefore, large plates can be released without additional etch holes, and with smooth structure undersurface and smooth substrate support surfaces . To understand the process, consider the two equilateral triangles bounded by {I 1I} planes of (1 11)oriented silicon as shown in Figure 1. Note that the various {I 1I } planes are tilted at f 19.47' angles from the vertical as indicated. Now consider a pattern opening shown in Figure 2. The pattern is micromachined using RIE processes, and partial nitride passivation performed as shown in Figure 3. If this structure is wet etched in an aqueous alkaline etchant, the pattern is released as in Figure 4. Due to the space limitation, a detailed flow sequence is not shown. Figure 5 shows fabricated single crystalline microbridges. Figure 5 (a) shows a released bridge. The dimensions are: length 55pm, width 20pm, and thickness 4 p . The gap to the substrate is 2pm. Figure 5 (b) shows a bridge with dimensions: 260pm length, 50pm width, and ,4pm thickness. The SEM shows that 260pm x 50pm is released, but that the bridge is stuck to the substrate because of the stiction caused by wet etching. This problem can be improved by the use of sublimation or super critical drying techniques, or by simply making the gap larger. Also note that because the micromachining technology relies on RIE for shape patterning and crystallography-dependent anisotropic etching, all shapes are sharply defined and all surfaces are clear. Other shapes including comb drives can be easily fabricated using this technique. This paper developed a new micromachining technology using (1 11)-oriented silicon for the first time. The technology combines the advantages of dry RIE processes and crystallography of silicon to fabricate sharply-defined, arbitrarily-shaped, released, single-crystalline silicon microstructures. This technology offers much potential as an alternati","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125192347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730100
S.K. Jung, B. Choi, S.I. Kim, C.K. Hyun, B. Min, S. Hwang, J. Park, Y. Kim, E. Kim, S. Min
Single electron tunneling and its application to future VLSI systems has been an important subject extensively studied for the last decade [l]. Many types of materials and ideas have been applied to fabricate and implement single electron devices operating at high temperatures. The self-assembled quantum dot (SAQD) system is one of the attractive candidates for single electron devices since high quality Coulomb islands can be obtained in one-step growth processes. Furthermore, the characteristic energy scale of the devices would enhance because the quantum energy is expected to be added to the classical charging energy. on InGaAs SAQD's. lever-arms with nm spacings. staircases at 77 K and higher temperatures. Figure 1 (a) and (b) show an AFM photos of typical SAQD single electron devices fabricated by the lever-arm technique. The InGaAs SAQD's we have used were grown by an MOCVD technique and the typical diameter of the dots is approximately 20 nm [2]. The aluminum lever-arms with spacings from 200 to 40 nm were fabricated by a standard ebeam exposure and a lift-off process. Figure 2 (a) and (b) show the 77 K current-voltage (I V) and its differential conductance - voltage characteristics.(dUdV - V) of lever - arm device with the gap of 40 nm. Several staircases are clearly identified in both the I-V and the dVdV-V. dI/dV-V of the device with the gap of 150 nm. Clear staircases are also seen. These staircases are originated from the single electron tunneling through SAQD's located in the shortest current path between two lever - arms. In conclusion, self-assembled guantum dot single electron devices are made by the lever-arm technique with the minimum gap spacing of 40 nm and clear staircases are observed in the I-V characteristics. The result of more complicated devices with multiple lever-arms will also be presented at the conference.
{"title":"Self-Assembled Quantum Dot Single Electron Devices","authors":"S.K. Jung, B. Choi, S.I. Kim, C.K. Hyun, B. Min, S. Hwang, J. Park, Y. Kim, E. Kim, S. Min","doi":"10.1109/IMNC.1998.730100","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730100","url":null,"abstract":"Single electron tunneling and its application to future VLSI systems has been an important subject extensively studied for the last decade [l]. Many types of materials and ideas have been applied to fabricate and implement single electron devices operating at high temperatures. The self-assembled quantum dot (SAQD) system is one of the attractive candidates for single electron devices since high quality Coulomb islands can be obtained in one-step growth processes. Furthermore, the characteristic energy scale of the devices would enhance because the quantum energy is expected to be added to the classical charging energy. on InGaAs SAQD's. lever-arms with nm spacings. staircases at 77 K and higher temperatures. Figure 1 (a) and (b) show an AFM photos of typical SAQD single electron devices fabricated by the lever-arm technique. The InGaAs SAQD's we have used were grown by an MOCVD technique and the typical diameter of the dots is approximately 20 nm [2]. The aluminum lever-arms with spacings from 200 to 40 nm were fabricated by a standard ebeam exposure and a lift-off process. Figure 2 (a) and (b) show the 77 K current-voltage (I V) and its differential conductance - voltage characteristics.(dUdV - V) of lever - arm device with the gap of 40 nm. Several staircases are clearly identified in both the I-V and the dVdV-V. dI/dV-V of the device with the gap of 150 nm. Clear staircases are also seen. These staircases are originated from the single electron tunneling through SAQD's located in the shortest current path between two lever - arms. In conclusion, self-assembled guantum dot single electron devices are made by the lever-arm technique with the minimum gap spacing of 40 nm and clear staircases are observed in the I-V characteristics. The result of more complicated devices with multiple lever-arms will also be presented at the conference.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115673365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729996
S. Nakao, J. Miyazaki, K. Tsujita, W. Wakamiya
{"title":"Measuring Odd Component Of Aberration Function Utilizing Alternating PSM","authors":"S. Nakao, J. Miyazaki, K. Tsujita, W. Wakamiya","doi":"10.1109/IMNC.1998.729996","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729996","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116648176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729989
O. Toublan, D. Boutin, P. Schiavone
{"title":"Determination Of The CD Dispersion And Proximity Bias Across The Lens Field By Electrical Linewidth Measurements","authors":"O. Toublan, D. Boutin, P. Schiavone","doi":"10.1109/IMNC.1998.729989","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729989","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730081
Y. Mitsuoka, K. Nakajima, N. Chiba, H. Muramatsu, T. Ataka
The interest in extremely small solid-state devices and high-density data storage has increased rapidly. To realize such applications, new techniques for fabricating nanometer-scale structures are important, because the conventional optical lithography has an insufficient resolution limited by the wavelength of the light and the numerical aperture of the lenses. In addition to electron beam lithography, scanning probe techniques such as scanning tunneling microscopy (STM)’) and atomic force microscopy (AFM)’) have been investigated to perform surface modifications in a simple way. Near-field optical lithography has a potential to fabricate nanometer-scale patterns more rapidly than the techniques based on STM or AFM. Scanning near-field optical microscopy (SNOM) is a useful method to investigate the possibility of near-field optical lithography for nanometer-scale fabrication. The schematic diagram of our SNOM3) system for the fabrication is shown in Fig. 1. An optical fiber probe has an aperture with a subwavelength at the apex. The optical fiber probe is bent and vibrated vertically to control the distance between the sample and the probe tip. The light source is an Ar ion laser (A = 488 nm) or a He-Cd laser (A = 442 nm). Commercial photoresist, which is sensitive to g line (A = 436 nm), is coated on a Si wafer by a spin-coater. The photoresist film is exposed by the light emitted by the aperture of the optical fiber probe. Changing the incident light intensity or the scanning speed controls the exposure conditions. The exposed photoresist film is developed and observed by AFM. Figure 2 shows the AFM image of the positive photoresist film. The groove width in the photoresit film is about 100 nm. It is nearly equal to the aperture size of the optical fiber probe. In Fig. 3, an aluminum line pattern with the width of 100 nm on a Si wafer was fabricated by the lift-off technique. We have demonstrated that subwavelength patterns can be fabricated using SNOM. These results show the possibility of near-field optical lithography for fabricating nanometer-scale structures.
{"title":"Nanofabrication Using Scanning Near-Field Optical Microscopy","authors":"Y. Mitsuoka, K. Nakajima, N. Chiba, H. Muramatsu, T. Ataka","doi":"10.1109/IMNC.1998.730081","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730081","url":null,"abstract":"The interest in extremely small solid-state devices and high-density data storage has increased rapidly. To realize such applications, new techniques for fabricating nanometer-scale structures are important, because the conventional optical lithography has an insufficient resolution limited by the wavelength of the light and the numerical aperture of the lenses. In addition to electron beam lithography, scanning probe techniques such as scanning tunneling microscopy (STM)’) and atomic force microscopy (AFM)’) have been investigated to perform surface modifications in a simple way. Near-field optical lithography has a potential to fabricate nanometer-scale patterns more rapidly than the techniques based on STM or AFM. Scanning near-field optical microscopy (SNOM) is a useful method to investigate the possibility of near-field optical lithography for nanometer-scale fabrication. The schematic diagram of our SNOM3) system for the fabrication is shown in Fig. 1. An optical fiber probe has an aperture with a subwavelength at the apex. The optical fiber probe is bent and vibrated vertically to control the distance between the sample and the probe tip. The light source is an Ar ion laser (A = 488 nm) or a He-Cd laser (A = 442 nm). Commercial photoresist, which is sensitive to g line (A = 436 nm), is coated on a Si wafer by a spin-coater. The photoresist film is exposed by the light emitted by the aperture of the optical fiber probe. Changing the incident light intensity or the scanning speed controls the exposure conditions. The exposed photoresist film is developed and observed by AFM. Figure 2 shows the AFM image of the positive photoresist film. The groove width in the photoresit film is about 100 nm. It is nearly equal to the aperture size of the optical fiber probe. In Fig. 3, an aluminum line pattern with the width of 100 nm on a Si wafer was fabricated by the lift-off technique. We have demonstrated that subwavelength patterns can be fabricated using SNOM. These results show the possibility of near-field optical lithography for fabricating nanometer-scale structures.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122184583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730099
Geunsook Park, Sangyeon Han, Hyungcheol Shin
11. Device Fabrication The ultra-thin SO1 film was formed by thermal oxidation of SIMOX wafers. The thickness of the recessed top-silicon layer was about 41nm. The edge region was formed by reactive ion etching, Then, the gate oxide was thermally grown to a thickness of about 14nm. Poly-silicon sidewall was formed by LPCVD and RIE etchback (Fig. 2). The thickness of the remained poly-silicon at the sidewall was determined by RIE etchback time. The poly-silicon remained at the side wall was patterned by E-beam lithography to form a nano-dot (Fig. 3). The poly-silicon dot acts as the floating gate for the storage of electrons. Interpoly oxide was deposited to a thickness of about 50nm. And then poly-silicon was deposited, and control gate was pattemed optically. As shown in Figure I@), oxide on top of the channel was very thick, whereas the gate oxide on the edge was thin. So, the inversion layer is formed only at the side edge. Both devices with dot and without dot were fabricated.
{"title":"A Nano-Structure Memory With SOI Edge Channel And A Nano Dot","authors":"Geunsook Park, Sangyeon Han, Hyungcheol Shin","doi":"10.1109/IMNC.1998.730099","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730099","url":null,"abstract":"11. Device Fabrication The ultra-thin SO1 film was formed by thermal oxidation of SIMOX wafers. The thickness of the recessed top-silicon layer was about 41nm. The edge region was formed by reactive ion etching, Then, the gate oxide was thermally grown to a thickness of about 14nm. Poly-silicon sidewall was formed by LPCVD and RIE etchback (Fig. 2). The thickness of the remained poly-silicon at the sidewall was determined by RIE etchback time. The poly-silicon remained at the side wall was patterned by E-beam lithography to form a nano-dot (Fig. 3). The poly-silicon dot acts as the floating gate for the storage of electrons. Interpoly oxide was deposited to a thickness of about 50nm. And then poly-silicon was deposited, and control gate was pattemed optically. As shown in Figure I@), oxide on top of the channel was very thick, whereas the gate oxide on the edge was thin. So, the inversion layer is formed only at the side edge. Both devices with dot and without dot were fabricated.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115252995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729973
A. Ray-Chaudhuri
{"title":"Progress In The Development Of Extreme Ultraviolet Lithography Exposure Systems","authors":"A. Ray-Chaudhuri","doi":"10.1109/IMNC.1998.729973","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729973","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125736992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730065
J. Park, Y.H. Lee, J. Bae, G. Yeom, J. Song
{"title":"MoSi(N) As A Diffusion Barrier Between Cu And Si","authors":"J. Park, Y.H. Lee, J. Bae, G. Yeom, J. Song","doi":"10.1109/IMNC.1998.730065","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730065","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128172115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729962
Y. Oh
{"title":"Development Of Silicon Based Inertial Sensor In SAIT","authors":"Y. Oh","doi":"10.1109/IMNC.1998.729962","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729962","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114255826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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