Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729968
Kyu‐Ho Hwang, Yong-Jin Song, Sang-Gook Kim
As shown in voltages are the actuators. Ir of the individual corresponding When there is n3 are fully tilted, according to ths between the Fig. 1, a TFAMA module consists of the active matrix, where the image signal applied, the cantilever-type piezoelectric actuators, and the reflection mirrors, on top of order to use the TFAMA module as a display device, the variation of the tilting angle mirror pixel need to be expressed as the change in light intensity of the point on the projected screen. Figure 2 shows the light modulation principle of TFAMA. tilting of mirror pixels, no light goes out through the light stop. When the mirror pixels .‘ut1 light goes out to the screen. By controlling the tilting angle of the mirror pixel signal voltage applied to the corresponding actuator, 256 steps of gray levels in brightest and the darkest can be generated on the screen.
{"title":"Micromachined Thin-Film Actuated Mirror Array For High-Brightness Projection Displays","authors":"Kyu‐Ho Hwang, Yong-Jin Song, Sang-Gook Kim","doi":"10.1109/IMNC.1998.729968","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729968","url":null,"abstract":"As shown in voltages are the actuators. Ir of the individual corresponding When there is n3 are fully tilted, according to ths between the Fig. 1, a TFAMA module consists of the active matrix, where the image signal applied, the cantilever-type piezoelectric actuators, and the reflection mirrors, on top of order to use the TFAMA module as a display device, the variation of the tilting angle mirror pixel need to be expressed as the change in light intensity of the point on the projected screen. Figure 2 shows the light modulation principle of TFAMA. tilting of mirror pixels, no light goes out through the light stop. When the mirror pixels .‘ut1 light goes out to the screen. By controlling the tilting angle of the mirror pixel signal voltage applied to the corresponding actuator, 256 steps of gray levels in brightest and the darkest can be generated on the screen.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730061
S. Song, S. Lee, B. Ryum, E. Yoon
Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon have many applications in integrated circuit processing such as device isolation and self-aligned processes to enhance the integrated circuit performance as well as level of integration. However, in order for SEG to be applied for device fabrication, to the extent of production technology, reasonably high growth rate, high-quality epitaxial layers are prerequisite. Various facets were observed in the overgrown Si regions and it is known that the control of facet formation is important for subsequent device fabrication. (1 13) facets were primarily observed on (001) Si wafers, when SEG was made on Si window regions at high temperatures [1,2]. The mask patterns were along <110> direction. As SEG continued, some of SEG Si started to overgrow over the mask and (1 11) facets began to appear [2]. Recently, a (1 IO) facet was reported in SEG silicon due to the stress induced at the overgrown silicon [3], however, the detailed mechanism for the (1 IO) facet formation is not known.
{"title":"Facet Formation In Selectively Overgrown Silicon By Reduced Pressure Chemical Vapor Deposition","authors":"S. Song, S. Lee, B. Ryum, E. Yoon","doi":"10.1109/IMNC.1998.730061","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730061","url":null,"abstract":"Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon have many applications in integrated circuit processing such as device isolation and self-aligned processes to enhance the integrated circuit performance as well as level of integration. However, in order for SEG to be applied for device fabrication, to the extent of production technology, reasonably high growth rate, high-quality epitaxial layers are prerequisite. Various facets were observed in the overgrown Si regions and it is known that the control of facet formation is important for subsequent device fabrication. (1 13) facets were primarily observed on (001) Si wafers, when SEG was made on Si window regions at high temperatures [1,2]. The mask patterns were along <110> direction. As SEG continued, some of SEG Si started to overgrow over the mask and (1 11) facets began to appear [2]. Recently, a (1 IO) facet was reported in SEG silicon due to the stress induced at the overgrown silicon [3], however, the detailed mechanism for the (1 IO) facet formation is not known.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133550557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729959
C. Kim
Need for Education Evolved from the IC fabrication community, MEMS lacks a firm foundation in mechanical engineering. Most of the current microdevices are in concept not much more than miniaturized versions of known devices, while the physical behavior is quite different in microscale. For MEMS to fulfill its full potential, engineers need to be trained for microscale engineering. The Ph.D. program in MEMS, a formal major field in the Mechanical and Aerospace Engineering Department of UCLA. was established to address the above issue.
{"title":"Microelectromechancial Systems (MEMS) At The UCLA Micromanufacturing Lab","authors":"C. Kim","doi":"10.1109/IMNC.1998.729959","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729959","url":null,"abstract":"Need for Education Evolved from the IC fabrication community, MEMS lacks a firm foundation in mechanical engineering. Most of the current microdevices are in concept not much more than miniaturized versions of known devices, while the physical behavior is quite different in microscale. For MEMS to fulfill its full potential, engineers need to be trained for microscale engineering. The Ph.D. program in MEMS, a formal major field in the Mechanical and Aerospace Engineering Department of UCLA. was established to address the above issue.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"25 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730091
C. Hahn, Young Ju Park, Kyung-Hyun Park, Chan Kyung Hyun, E. Kim, S. Min, J. Park
{"title":"Selectively Formed InAs Quantum Dot Arrays For Device Application","authors":"C. Hahn, Young Ju Park, Kyung-Hyun Park, Chan Kyung Hyun, E. Kim, S. Min, J. Park","doi":"10.1109/IMNC.1998.730091","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730091","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123464989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729994
D. Cha, J. Kye, N. Seong, H. Kang, H. Cho, J. Moon
{"title":"Patterning of Sub-0.18/spl mu/m Logic Gates with Phase-Edge PSM","authors":"D. Cha, J. Kye, N. Seong, H. Kang, H. Cho, J. Moon","doi":"10.1109/IMNC.1998.729994","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729994","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122204767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730011
Ilgweon Kim, Hyungsik Kim, Jongho Lee, Hyungcheol Shin
11. Experimental Quantum dot fabrication was performed in a conventional low-pressure chemical-vapor deposition (LPCVD) reactor using 50% SiH, in helium as the source gas. The substrates used were 150" p-type (100) silicon wafers having either Si0,layer thermally grown by dry oxidation or Si,N, layer deposited by LPCVD. Several split experiments were carried out to evaluate the effect of substrate chemical treatment with 1% HF solution, the substrate film type, and deposition temperature. The average height and density of quantum dots were measured by AFM and top view SEM. The evaluation of substrate roughness was also carried out by AFM. The deposition temperature was varied from 600°C to 640°C and the deposition time was varied from 15sec to 90sec.
{"title":"Fabrication Of Silicon Quantum Dots On Oxide And Nitride","authors":"Ilgweon Kim, Hyungsik Kim, Jongho Lee, Hyungcheol Shin","doi":"10.1109/IMNC.1998.730011","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730011","url":null,"abstract":"11. Experimental Quantum dot fabrication was performed in a conventional low-pressure chemical-vapor deposition (LPCVD) reactor using 50% SiH, in helium as the source gas. The substrates used were 150\" p-type (100) silicon wafers having either Si0,layer thermally grown by dry oxidation or Si,N, layer deposited by LPCVD. Several split experiments were carried out to evaluate the effect of substrate chemical treatment with 1% HF solution, the substrate film type, and deposition temperature. The average height and density of quantum dots were measured by AFM and top view SEM. The evaluation of substrate roughness was also carried out by AFM. The deposition temperature was varied from 600°C to 640°C and the deposition time was varied from 15sec to 90sec.","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
AbsWact The monolithic inkjet printhead usrng a newly suggested singye crystalline silicon for a heahng resistor was proposed and fabricated by a process integrahon The fabricated heating resistor was Characterized and ink drop ejection experiment was successfully performed. The heabng resistor was fabricated by FIPOS(Ful1 Isolahon by Porous Oxidized Silicon) not using inaplantahon or epitav but using a newly devised p+/n' double diffusion method The heatir?g resistor is thermally and electncally isolated from silicon substrate by FIPOS(21 using the p+/n' double dfluusron method The fabricahon using the sngle cvstalline silicon as a hea frng resistor was szmpler than conventional process because of using thermally grown oxide as a passivahon layer An jlSiCslTa).[ 11 The
摘要:提出了一种新型单晶硅加热电阻单片喷墨打印头，并采用工艺集成技术制作了该单片喷墨打印头，对所制备的加热电阻进行了表征，成功地进行了墨滴喷射实验。采用FIPOS(Ful1 Isolahon by Porous Oxidized Silicon)法制备了一种新型的p+/n'双扩散法，而不是采用内扩散法和外延法。通过FIPOS技术，该电阻器在热学和电学上都与硅衬底隔离(21使用p+/n'双流控法)。由于使用热生长氧化物作为钝化层，因此使用单晶硅作为钝化电阻的制造比传统工艺更简单。[11]
{"title":"A New Monolithic Inkjet Printhead Using Single Crystalline Silicon For A Heating Resistor","authors":"Choon-Sup Lee, Jae-Duk Lee, Jun‐Bo Yoon, Jae-Kwan Kirri, Hoon-Ju Chung, Chul‐Hi Han","doi":"10.1109/IMNC.1998.730036","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730036","url":null,"abstract":"AbsWact The monolithic inkjet printhead usrng a newly suggested singye crystalline silicon for a heahng resistor was proposed and fabricated by a process integrahon The fabricated heating resistor was Characterized and ink drop ejection experiment was successfully performed. The heabng resistor was fabricated by FIPOS(Ful1 Isolahon by Porous Oxidized Silicon) not using inaplantahon or epitav but using a newly devised p+/n' double diffusion method The heatir?g resistor is thermally and electncally isolated from silicon substrate by FIPOS(21 using the p+/n' double dfluusron method The fabricahon using the sngle cvstalline silicon as a hea frng resistor was szmpler than conventional process because of using thermally grown oxide as a passivahon layer An jlSiCslTa).[ 11 The","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128816440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.730106
K. Ishikawa, M. Yoshimura, K. Ueda
{"title":"Direct Lithography On Hydrogen-Terminated Silicon Surface Using Two-Dimensional Hydrogen Analysis","authors":"K. Ishikawa, M. Yoshimura, K. Ueda","doi":"10.1109/IMNC.1998.730106","DOIUrl":"https://doi.org/10.1109/IMNC.1998.730106","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729981
J.-B. Yoon, Chul‐Hi Han, E. Yoon, C. kim
ed a novel and high-yield process to fabricate electroplated 3D microI concept as shown in Figure 1, we decompose the 3D micro-coil, which integrated inductor in other words, into two parts, the bottom conductor bridges, and form the single-body air bridges during only one his does not mean the air bridges are made by the conventional way, f posts (or vias) and upper conductor lines vertically, and hence is a
{"title":"Novel Fabrication Of Electroplated 3D Micro-Coils Using 3D Photolithography Of Thick Photoresist","authors":"J.-B. Yoon, Chul‐Hi Han, E. Yoon, C. kim","doi":"10.1109/IMNC.1998.729981","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729981","url":null,"abstract":"ed a novel and high-yield process to fabricate electroplated 3D microI concept as shown in Figure 1, we decompose the 3D micro-coil, which integrated inductor in other words, into two parts, the bottom conductor bridges, and form the single-body air bridges during only one his does not mean the air bridges are made by the conventional way, f posts (or vias) and upper conductor lines vertically, and hence is a","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123004960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-07-13DOI: 10.1109/IMNC.1998.729970
D. Sasaguri, T. Asano
{"title":"A New Fabrication Process Of Field Emitter Arrays Using Silicon Delamination By Hydrogen Ion Implantation","authors":"D. Sasaguri, T. Asano","doi":"10.1109/IMNC.1998.729970","DOIUrl":"https://doi.org/10.1109/IMNC.1998.729970","url":null,"abstract":"","PeriodicalId":356908,"journal":{"name":"Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130945405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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