Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393715
Y. Su, R. Guo, Shi-Chung Chang
As IC design and manufacturing complexities continue to increase exponentially, new collaboration mechanisms are required between IC design house and foundry. By conducting field interviews and empirical study, this research summarizes different engineering collaboration mechanisms under different stages of process technology. There are several findings: 1) The collaboration is mostly required when the design house develops advanced products and the foundry needs driving product house develop advanced processes; 2) The major effort of collaboration in advanced and developing processes is to find the critical failure modes in order to dramatically improve the yield of new process technology; 3) It is critical to have right experts from both parties; and 4) The migration from low yield toward high yield requires improvement through both product design tuning and process tuning. Partnership and close interactions are required for quick problem solving.
{"title":"Inter-firm collaboration mechanism in process development and product design between foundry and fabless design house","authors":"Y. Su, R. Guo, Shi-Chung Chang","doi":"10.1109/SMTW.2004.1393715","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393715","url":null,"abstract":"As IC design and manufacturing complexities continue to increase exponentially, new collaboration mechanisms are required between IC design house and foundry. By conducting field interviews and empirical study, this research summarizes different engineering collaboration mechanisms under different stages of process technology. There are several findings: 1) The collaboration is mostly required when the design house develops advanced products and the foundry needs driving product house develop advanced processes; 2) The major effort of collaboration in advanced and developing processes is to find the critical failure modes in order to dramatically improve the yield of new process technology; 3) It is critical to have right experts from both parties; and 4) The migration from low yield toward high yield requires improvement through both product design tuning and process tuning. Partnership and close interactions are required for quick problem solving.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131622906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393700
E. Wu
{"title":"The outlook for electronic systems and semiconductors","authors":"E. Wu","doi":"10.1109/SMTW.2004.1393700","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393700","url":null,"abstract":"","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128168138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393754
R. Liou, T. Cheng, Chung-I Chang, Tings Wang, S. Fu, T. Dziura
The feasibility of measuring four profile parameters, i.e,, total etch depth, critical dimension (CD), thickness of remaining poly hard mask, and sidewall angle, for the metal-0 trench of DRAM by a single technique was investigated in this study. Broadband spectroscopic ellipsometry was used to provide non-destructive profile information. The results prove its capability for providing the required profile information, traditionally measured on 4 different metrology tools, by a single measurement. This capability could significantly simplify the process flow for metal-0 trench.
{"title":"Feasibility of measuring four profile parameters for metal-0 trench of DRAM by spectroscopic ellipsometry based profile technology","authors":"R. Liou, T. Cheng, Chung-I Chang, Tings Wang, S. Fu, T. Dziura","doi":"10.1109/SMTW.2004.1393754","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393754","url":null,"abstract":"The feasibility of measuring four profile parameters, i.e,, total etch depth, critical dimension (CD), thickness of remaining poly hard mask, and sidewall angle, for the metal-0 trench of DRAM by a single technique was investigated in this study. Broadband spectroscopic ellipsometry was used to provide non-destructive profile information. The results prove its capability for providing the required profile information, traditionally measured on 4 different metrology tools, by a single measurement. This capability could significantly simplify the process flow for metal-0 trench.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114220124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393699
H. Iwai
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In This work, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.
{"title":"Future of CMOS technology","authors":"H. Iwai","doi":"10.1109/SMTW.2004.1393699","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393699","url":null,"abstract":"Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In This work, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393724
Zhi-Ting Ke, Cheng-Shih Lee, Keng-Huei Shen, E. Chang
This work is to study the dry-film photoresist to form patterns for flip-chip bumps on 300 mm wafers. The so-called "double-deck metal seed layer" process was also applied in this study by using sputtered 1000 /spl Aring/ Ti (Titanium) and 5000 /spl Aring/ Cu (Copper) metal layers. By welding the metal and solder electroplating technology on the chip of the integrated circuits, Cu/Ni/solder alloy fill up hole under bumps metallization after solder re-flowing at 220/spl deg/C. This research optimizes the parameters of the dry-film photoresist, lithography technology, metal sputtering technology and metal electroplating technology.
本工作是研究干膜光刻胶在300mm晶圆上形成倒装凸点图案。本研究还采用了所谓的“双层金属种子层”工艺，使用溅射1000 /spl的Aring/ Ti (Titanium)和5000 /spl的Aring/ Cu (Copper)金属层。通过在集成电路芯片上焊接金属和电镀焊锡技术，在220/spl℃下焊锡回流后，Cu/Ni/焊锡合金填补了凹凸金属化下的空洞。本研究对干膜光刻胶、光刻工艺、金属溅射工艺和金属电镀工艺的参数进行了优化。
{"title":"A study of the fabrication of flip-chip bumps using dry-film photoresist process on 300 mm wafer","authors":"Zhi-Ting Ke, Cheng-Shih Lee, Keng-Huei Shen, E. Chang","doi":"10.1109/SMTW.2004.1393724","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393724","url":null,"abstract":"This work is to study the dry-film photoresist to form patterns for flip-chip bumps on 300 mm wafers. The so-called \"double-deck metal seed layer\" process was also applied in this study by using sputtered 1000 /spl Aring/ Ti (Titanium) and 5000 /spl Aring/ Cu (Copper) metal layers. By welding the metal and solder electroplating technology on the chip of the integrated circuits, Cu/Ni/solder alloy fill up hole under bumps metallization after solder re-flowing at 220/spl deg/C. This research optimizes the parameters of the dry-film photoresist, lithography technology, metal sputtering technology and metal electroplating technology.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393746
Haw-Jyue Luo, S.R. Wang, C. Chen, Hung-En Tai, Chen-Fu Chien, Pei-Nong Chen
The rapid innovation of new process technologies in the semiconductor industry, especially 12 inches Fab, along with continuously growing amounts of data, it is difficult to find root cause when problems occur in some process steps. It causes large amount of wafer scrapping. The analysis methods of traditional EDA system rely on experience of senior engineers. They need to define the suspected process step by their experience and then perform analysis. The analysis methods consume large amounts of human resources in order to determine the root cause of process and yield excursions. Hence, it is important that a knowledge retention method be incorporated to improve the efficiency of root cause analysis. Data mining, a new data analysis method that combines information science and technology of statistical analysis, is developed recently. The new generation data analysis method includes statistical, information science and mathematical calculation to find correlation between the target parameter, for example yield and other parameters. It will provide important clue to the analyzer. In addition, it also provides a direction to find root cause rapidly. It is difficult to find the correlation between the target parameter and other parameters by traditional statistical analysis method, and data mining can solve the blind point of the traditional method. This article discusses the design of how to define the relation between all data sources of semiconductor industry based on the experience of senior engineers. And it installs the relation to data mining analysis, it performs the analysis to identify relationship among all data sources. So, engineers can find the root cause of process issue in a short period of time
{"title":"Using process experienced correlation table to improve the accuracy and reliability of data mining for yield improvement","authors":"Haw-Jyue Luo, S.R. Wang, C. Chen, Hung-En Tai, Chen-Fu Chien, Pei-Nong Chen","doi":"10.1109/SMTW.2004.1393746","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393746","url":null,"abstract":"The rapid innovation of new process technologies in the semiconductor industry, especially 12 inches Fab, along with continuously growing amounts of data, it is difficult to find root cause when problems occur in some process steps. It causes large amount of wafer scrapping. The analysis methods of traditional EDA system rely on experience of senior engineers. They need to define the suspected process step by their experience and then perform analysis. The analysis methods consume large amounts of human resources in order to determine the root cause of process and yield excursions. Hence, it is important that a knowledge retention method be incorporated to improve the efficiency of root cause analysis. Data mining, a new data analysis method that combines information science and technology of statistical analysis, is developed recently. The new generation data analysis method includes statistical, information science and mathematical calculation to find correlation between the target parameter, for example yield and other parameters. It will provide important clue to the analyzer. In addition, it also provides a direction to find root cause rapidly. It is difficult to find the correlation between the target parameter and other parameters by traditional statistical analysis method, and data mining can solve the blind point of the traditional method. This article discusses the design of how to define the relation between all data sources of semiconductor industry based on the experience of senior engineers. And it installs the relation to data mining analysis, it performs the analysis to identify relationship among all data sources. So, engineers can find the root cause of process issue in a short period of time","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126000129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393758
Pei-Nong Chen, Chen-Fu Chien, Sheng-Jen Wang, Chien-chung Chen, Haw-Jyue Luo
When a new equipment or process is released, it is critical to ensure it behave as expected and stay in normal condition. The study proposes a research framework in which a statistical model is constructed for newly released equipment and process monitoring. An empirical study is conducted in a DRAM fabrication facility for validation. Based on the model, a best set of sample test items which discriminates the newly released equipment is selected and a group of normal equipments is obtained. Thus, the alarm signals can be triggered in an early warning system.
{"title":"Developing statistical models in an early warning system and its empirical study","authors":"Pei-Nong Chen, Chen-Fu Chien, Sheng-Jen Wang, Chien-chung Chen, Haw-Jyue Luo","doi":"10.1109/SMTW.2004.1393758","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393758","url":null,"abstract":"When a new equipment or process is released, it is critical to ensure it behave as expected and stay in normal condition. The study proposes a research framework in which a statistical model is constructed for newly released equipment and process monitoring. An empirical study is conducted in a DRAM fabrication facility for validation. Based on the model, a best set of sample test items which discriminates the newly released equipment is selected and a group of normal equipments is obtained. Thus, the alarm signals can be triggered in an early warning system.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393755
Wen-Yao Chang, Tzu-Chi Wang, Yuan-Pin Shin
Predictive maintenance and increase on equipment effectiveness could be carried out by the equipment condition monitoring system (ECMS). The designing procedures of ECMS from failure analysis, monitoring method, monitoring steps, to maintenance strategy are presented in this paper. The maintenance strategies could be divided into three kind of category and four level architectures. Six kinds of monitoring methods, such as chiller performance coefficient monitoring, element efficiency monitoring, performance monitoring, data limit monitoring, vibration monitoring and current signature monitoring, are also discussed in this paper
{"title":"Real-time fault detection and condition monitoring system for chiller","authors":"Wen-Yao Chang, Tzu-Chi Wang, Yuan-Pin Shin","doi":"10.1109/SMTW.2004.1393755","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393755","url":null,"abstract":"Predictive maintenance and increase on equipment effectiveness could be carried out by the equipment condition monitoring system (ECMS). The designing procedures of ECMS from failure analysis, monitoring method, monitoring steps, to maintenance strategy are presented in this paper. The maintenance strategies could be divided into three kind of category and four level architectures. Six kinds of monitoring methods, such as chiller performance coefficient monitoring, element efficiency monitoring, performance monitoring, data limit monitoring, vibration monitoring and current signature monitoring, are also discussed in this paper","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128104164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393743
Chun-Hao Li, M. Tsai, R. Chen, Chen-Hau Lee, Sheng-Wen Hong
This packaging method QFN could reduce thermal-resistance, less size for packaging and weight, suitable for medium or small pads IC with high speed and high frequency applications for products. By such packaging process, QFN ICs need to separate for mounting on the different applications of printed-circuit boards, cutting the strips by saw machine would be fine now for mass production, but there are something worse, including IC crack easy, stress releasing problem, space wasting...and so on. So this paper focus on the result of laser cutting on QFN IC strips by using diode pumped solid state laser system, and describe the detail effect of laser parameters, it would tell us the technology of laser cutting for QFN with excellent good results, the new development for laser applications should be worth for semiconductor industry
{"title":"Cutting for QFN packaging by diode pumping solid state laser system","authors":"Chun-Hao Li, M. Tsai, R. Chen, Chen-Hau Lee, Sheng-Wen Hong","doi":"10.1109/SMTW.2004.1393743","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393743","url":null,"abstract":"This packaging method QFN could reduce thermal-resistance, less size for packaging and weight, suitable for medium or small pads IC with high speed and high frequency applications for products. By such packaging process, QFN ICs need to separate for mounting on the different applications of printed-circuit boards, cutting the strips by saw machine would be fine now for mass production, but there are something worse, including IC crack easy, stress releasing problem, space wasting...and so on. So this paper focus on the result of laser cutting on QFN IC strips by using diode pumped solid state laser system, and describe the detail effect of laser parameters, it would tell us the technology of laser cutting for QFN with excellent good results, the new development for laser applications should be worth for semiconductor industry","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131195758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393706
J. Chang, Yung Cheng
When investing high cost to setup a 300 mm FAB transportation automation (3% of overall 300 mm FAB capital according to ITRS 2003), we always review the performance and KPl of this huge investment to make sure that the investment could gain sufficient ROI (return of investment) from 300 mm FAB automation operation productivity. When we are approaching ITRS's AMHS matrix - average FAB wide transportation should be 8 minutes; maximum FAB wide FOUP transportation should be 15 minutes. We found that just-in-time integrated system design could easily gain more 300 mm full-automation productivity than expensive AMHS investment.
{"title":"Just-in-time AMHS delivery for 300 mm FAB","authors":"J. Chang, Yung Cheng","doi":"10.1109/SMTW.2004.1393706","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393706","url":null,"abstract":"When investing high cost to setup a 300 mm FAB transportation automation (3% of overall 300 mm FAB capital according to ITRS 2003), we always review the performance and KPl of this huge investment to make sure that the investment could gain sufficient ROI (return of investment) from 300 mm FAB automation operation productivity. When we are approaching ITRS's AMHS matrix - average FAB wide transportation should be 8 minutes; maximum FAB wide FOUP transportation should be 15 minutes. We found that just-in-time integrated system design could easily gain more 300 mm full-automation productivity than expensive AMHS investment.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121205396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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