Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393728
Yi-Pin Fang, Y. Chou, Shu Hu, G. Hwang
A simple method, based on overlapping the dosage distribution of the discretely electron beam written nano-dots, was employed to fabricate nano-structure containing narrow constrictions. From the appropriately designed electron beam process, the electron dosage in the overlapping region is just above the threshold exposure dosage of the negative electronbeam resist. A Si-based nano-dot with two narrow tunnel junctions called single electron transistor was formed after dry etching and thermal oxidation process since the overlapping region is much narrower than the diameter of the nano-dot. The electric characteristic of the SET was found to be consistent with the expected behavior of electron transport through a gated quantum dot. Also, the characteristic phase diagrams of double dot structure were obtained by independently sweeping two gates. The honeycomb lattice of the conductance resonances in the phase diagram was modeled using a capacitance equivalent circuit and the electronic behavior of the double dot device was discussed from measured charging diagram comparing with the model.
{"title":"A simple method to fabricate single electron devices","authors":"Yi-Pin Fang, Y. Chou, Shu Hu, G. Hwang","doi":"10.1109/SMTW.2004.1393728","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393728","url":null,"abstract":"A simple method, based on overlapping the dosage distribution of the discretely electron beam written nano-dots, was employed to fabricate nano-structure containing narrow constrictions. From the appropriately designed electron beam process, the electron dosage in the overlapping region is just above the threshold exposure dosage of the negative electronbeam resist. A Si-based nano-dot with two narrow tunnel junctions called single electron transistor was formed after dry etching and thermal oxidation process since the overlapping region is much narrower than the diameter of the nano-dot. The electric characteristic of the SET was found to be consistent with the expected behavior of electron transport through a gated quantum dot. Also, the characteristic phase diagrams of double dot structure were obtained by independently sweeping two gates. The honeycomb lattice of the conductance resonances in the phase diagram was modeled using a capacitance equivalent circuit and the electronic behavior of the double dot device was discussed from measured charging diagram comparing with the model.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393741
L. Hsu
Increasing market pressures force design and manufacturing communities to come up with innovative and flexible design and manufacturing solutions to control cost and time to market. This work shows that optical maskless lithography (OML), requiring no mask at all, has lowest cost and shortest design-to-wafer times while keeping transparency to mask-based optical lithography and allowing for resolution enhancement via known low-k/sub 1/ imaging methods such as hard phase shifting and strong OPC.
{"title":"Optical maskless lithography for fast and low-cost design to wafer","authors":"L. Hsu","doi":"10.1109/SMTW.2004.1393741","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393741","url":null,"abstract":"Increasing market pressures force design and manufacturing communities to come up with innovative and flexible design and manufacturing solutions to control cost and time to market. This work shows that optical maskless lithography (OML), requiring no mask at all, has lowest cost and shortest design-to-wafer times while keeping transparency to mask-based optical lithography and allowing for resolution enhancement via known low-k/sub 1/ imaging methods such as hard phase shifting and strong OPC.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"223 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120871881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393748
S. Tseng, Shu-li Chen, J. Chang, Chien-Chang Chen, Mei-Ling Chen
As semiconductor manufacturing technology is becoming increasingly complex, hundreds of tools and process steps need to be strictly controlled and managed in the production line. The review of past wafer scrap history has revealed that one major scrap category was caused by inadvertent human error inducing un-intended change of the recipe setting in production tools. In order to get better production line yield and to assure wafer manufacturing quality, it is mandatory to prevent such human errors. Consequently, an effective recipe control and management methodology through a preventive system approach is required. At UMC, we have developed a recipe control and management system (RCMS) for this purpose. This work presents an overview of this RCMS system and management approaches. The latter includes supporting systems such as a recipe change co-sign system, job-in-cancel function, alarm disposition request (ADR), advanced pre-checking scheme on newly releasing a product for mass production, and post auditing reports on RCMS execution performance review. The RCMS and supporting systems together have provided a comprehensive & effective measure on recipe control and management in a preventive and foolproof manner.
{"title":"An effective recipe control and management system (RCMS) deployed in semiconductor manufacturing","authors":"S. Tseng, Shu-li Chen, J. Chang, Chien-Chang Chen, Mei-Ling Chen","doi":"10.1109/SMTW.2004.1393748","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393748","url":null,"abstract":"As semiconductor manufacturing technology is becoming increasingly complex, hundreds of tools and process steps need to be strictly controlled and managed in the production line. The review of past wafer scrap history has revealed that one major scrap category was caused by inadvertent human error inducing un-intended change of the recipe setting in production tools. In order to get better production line yield and to assure wafer manufacturing quality, it is mandatory to prevent such human errors. Consequently, an effective recipe control and management methodology through a preventive system approach is required. At UMC, we have developed a recipe control and management system (RCMS) for this purpose. This work presents an overview of this RCMS system and management approaches. The latter includes supporting systems such as a recipe change co-sign system, job-in-cancel function, alarm disposition request (ADR), advanced pre-checking scheme on newly releasing a product for mass production, and post auditing reports on RCMS execution performance review. The RCMS and supporting systems together have provided a comprehensive & effective measure on recipe control and management in a preventive and foolproof manner.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121333519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393762
Chun-Hung Tsai, Yu-Chung Lin, C. Hsu, Rong-Tian Cheng, C. Chang, Yung-Chao Lin, Po-Jen Chao
This paper discusses considerations in choosing a chemical supply system for semiconductor fabs. We investigate the characteristics of three major supply systems, drum, lorry and dilution system. The initial costs and footprints are totally different among them. Based on the cost analysis, this paper provides a simple criterion of using the lorry supply system. Besides discussion, information of leading fabs in each field is benchmarked in this paper
{"title":"Management considerations in choosing a chemical supply system","authors":"Chun-Hung Tsai, Yu-Chung Lin, C. Hsu, Rong-Tian Cheng, C. Chang, Yung-Chao Lin, Po-Jen Chao","doi":"10.1109/SMTW.2004.1393762","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393762","url":null,"abstract":"This paper discusses considerations in choosing a chemical supply system for semiconductor fabs. We investigate the characteristics of three major supply systems, drum, lorry and dilution system. The initial costs and footprints are totally different among them. Based on the cost analysis, this paper provides a simple criterion of using the lorry supply system. Besides discussion, information of leading fabs in each field is benchmarked in this paper","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122687880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393727
P. Chen, S.W. Lee, M. Lee, C. Liu, M. Tsai
High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated. This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75%. The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layers on these new buffers prove to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.
{"title":"Thin relaxed SiGe layers for strained Si CMOS","authors":"P. Chen, S.W. Lee, M. Lee, C. Liu, M. Tsai","doi":"10.1109/SMTW.2004.1393727","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393727","url":null,"abstract":"High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated. This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75%. The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layers on these new buffers prove to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122802053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393736
Maolong Chen, T. Yen, B. Coonan
Process control in semiconductor manufacturing has sought to improve yield, increase tool productivity and reduce manufacturing costs through the analysis of tool sensor outputs. Statistical process control (SPC) utilizes statistical algorithms to detect excursion events, but here a novel fault detection and classification (FDC) approach based upon a pattern recognition algorithm is presented. This FDC method from Straatum/spl trade/ is real-time, outputting a chamber status metric known as the plasma index. The system is in place at ProMOS Technologies Inc, 200 mm manufacturing facility on various semiconductor tools - this document presents its implementation on a number of Tokyo/spl trade/ DRM/spl trade/ oxide etch tools and includes a number of case studies.
{"title":"Real-time fault detection and classification for manufacturing etch tools","authors":"Maolong Chen, T. Yen, B. Coonan","doi":"10.1109/SMTW.2004.1393736","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393736","url":null,"abstract":"Process control in semiconductor manufacturing has sought to improve yield, increase tool productivity and reduce manufacturing costs through the analysis of tool sensor outputs. Statistical process control (SPC) utilizes statistical algorithms to detect excursion events, but here a novel fault detection and classification (FDC) approach based upon a pattern recognition algorithm is presented. This FDC method from Straatum/spl trade/ is real-time, outputting a chamber status metric known as the plasma index. The system is in place at ProMOS Technologies Inc, 200 mm manufacturing facility on various semiconductor tools - this document presents its implementation on a number of Tokyo/spl trade/ DRM/spl trade/ oxide etch tools and includes a number of case studies.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128720010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393730
C. Wu, Chong-Chang Liu, J. Lee, Szu-Hong Yang, S. Kuo
A new recipe was studied for floating gate etching of flash technology. The scheme for defining floating gate was BARC/SIN/POLY. The main etching step etched through BARC and stopped on SlN, and over etching step etched SIN completely and stopped on poly. Because the selectivity of BARC/SIN was very low with fluorine based recipe, the main step might etch through SIN and make poly loss too much. Four optimum parameters and O/sub 2/ was adopted in main etching step to increase the selectivity. Moreover, to reduce poly loss, high polymer gas CH/sub 3/F was added in over etching step. The result showed appropriate CH/sub 3/F/CF/sub 4/ ratio was positive to reduce poly loss. The modified recipe also was tested on the structure wafer and the product. The modified recipe got less poly loss than that of original recipe, and there was no difference on the shape of floating gate for both recipes. The electrical result also showed comparable performance to original CHF/sub 3/ based recipe.
{"title":"Study of floating gate nitride etch with high selectivity on flash technology","authors":"C. Wu, Chong-Chang Liu, J. Lee, Szu-Hong Yang, S. Kuo","doi":"10.1109/SMTW.2004.1393730","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393730","url":null,"abstract":"A new recipe was studied for floating gate etching of flash technology. The scheme for defining floating gate was BARC/SIN/POLY. The main etching step etched through BARC and stopped on SlN, and over etching step etched SIN completely and stopped on poly. Because the selectivity of BARC/SIN was very low with fluorine based recipe, the main step might etch through SIN and make poly loss too much. Four optimum parameters and O/sub 2/ was adopted in main etching step to increase the selectivity. Moreover, to reduce poly loss, high polymer gas CH/sub 3/F was added in over etching step. The result showed appropriate CH/sub 3/F/CF/sub 4/ ratio was positive to reduce poly loss. The modified recipe also was tested on the structure wafer and the product. The modified recipe got less poly loss than that of original recipe, and there was no difference on the shape of floating gate for both recipes. The electrical result also showed comparable performance to original CHF/sub 3/ based recipe.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125544132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393721
L. Lin, J.Y. Chen, E. Chou, Y. Miura, S. Chang, J. Chiu
One new defect classification method called RDC (real-time defect classification) is used to manage killer defects in 300 mm DRAM production line after defect inspection by separating killer defects from all detected defects. Such method is proven to effectively monitor the trend of killer defects which help process engineer and integration engineer to enhance production yield by the watch of killer defect from RDC.
{"title":"Effective methodology for killer defect management in 300 mm DRAM fab","authors":"L. Lin, J.Y. Chen, E. Chou, Y. Miura, S. Chang, J. Chiu","doi":"10.1109/SMTW.2004.1393721","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393721","url":null,"abstract":"One new defect classification method called RDC (real-time defect classification) is used to manage killer defects in 300 mm DRAM production line after defect inspection by separating killer defects from all detected defects. Such method is proven to effectively monitor the trend of killer defects which help process engineer and integration engineer to enhance production yield by the watch of killer defect from RDC.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125820458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hsin-Chang Lee, Chia-Jen Chen, H. Hsieh, L. Berger, W. Saule, P. Dreß, T. Gairing
Progress towards 65 nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2 nm 3/spl sigma/ (dense lines) for 65 nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 4.8 nm 3/spl sigma/ to 3.9 nm 3/spl sigma/ (/spl cong/20%) on a state-of-the-art production mask is achieved for the chrome layer (ASI, after strip inspection).
{"title":"Global CD uniformity improvement for CAR masks by adaptive post-exposure bake with CD measurement feedback","authors":"Hsin-Chang Lee, Chia-Jen Chen, H. Hsieh, L. Berger, W. Saule, P. Dreß, T. Gairing","doi":"10.1117/12.557714","DOIUrl":"https://doi.org/10.1117/12.557714","url":null,"abstract":"Progress towards 65 nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2 nm 3/spl sigma/ (dense lines) for 65 nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 4.8 nm 3/spl sigma/ to 3.9 nm 3/spl sigma/ (/spl cong/20%) on a state-of-the-art production mask is achieved for the chrome layer (ASI, after strip inspection).","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133144535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-07-01DOI: 10.1109/SMTW.2004.1393737
Sheng-Jyh Shiul, Cheng-Ching Yu, S. Shen, A. Sul
The modeling and multivariable control of the multi-zone CMP are studied in this work. In the process control notation, the manipulated variables are the three pressures applied to each zone. Therefore, this is a 60/spl times/3 non-square multivariable control problem. The singular value decomposition (SVD) is used to design a non-square feedback controller. The proposed control system is test on incoming wafers with different surface profiles. Results show that achievable performance can be maintained using the proposed SVD controller.
{"title":"Multivariable control of multi-zone chemical mechanical polishing","authors":"Sheng-Jyh Shiul, Cheng-Ching Yu, S. Shen, A. Sul","doi":"10.1109/SMTW.2004.1393737","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393737","url":null,"abstract":"The modeling and multivariable control of the multi-zone CMP are studied in this work. In the process control notation, the manipulated variables are the three pressures applied to each zone. Therefore, this is a 60/spl times/3 non-square multivariable control problem. The singular value decomposition (SVD) is used to design a non-square feedback controller. The proposed control system is test on incoming wafers with different surface profiles. Results show that achievable performance can be maintained using the proposed SVD controller.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133011838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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