Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393705
Shi-Chung Chang, Yu-Ting Lin, Yi-Ju Chang, Shy-Kang Jeng, B. Hsieh
AbsiracfGExploiting the knowledge-based sofmare agent technology, this paper presents a design and its prototype implementation for learning agent-based semiconductor tool group dispatching. Core to the agent-based dispatching are decision and sequence tree-bused howledge representation models, the learning and acquisition mechanisms of dispatching policy and integration with fab information system and management. Protofype implementation and test experiments over an industry compatible environment demonstrate both feasibility and potential effectiveness of the learning sofmare agent to support tool group dispatching.
{"title":"Learning software agent design for semiconductor tool group dispatching","authors":"Shi-Chung Chang, Yu-Ting Lin, Yi-Ju Chang, Shy-Kang Jeng, B. Hsieh","doi":"10.1109/SMTW.2004.1393705","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393705","url":null,"abstract":"AbsiracfGExploiting the knowledge-based sofmare agent technology, this paper presents a design and its prototype implementation for learning agent-based semiconductor tool group dispatching. Core to the agent-based dispatching are decision and sequence tree-bused howledge representation models, the learning and acquisition mechanisms of dispatching policy and integration with fab information system and management. Protofype implementation and test experiments over an industry compatible environment demonstrate both feasibility and potential effectiveness of the learning sofmare agent to support tool group dispatching.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114602042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393747
L. Lin, F. Kuo, C. Lee, C. Broughton, R. Yang, J. Liao, J. Wang
PowerChip (PSC) Fab 12A is a newly built 300 mm DRAM fab in Taiwan. PSC Fab 12A has identified that blank wafer defect monitoring is not adequate at 300 mm due to high test wafer cost and reduced process tool productivity. Aditionally, integration defects and some tool-induced defects do not occur on blank test wafers. For these reasons PSC 12A wanted to investigate using patterned product wafers for tool monitoring. This work describes how a patterned wafer tool monitor method was implemented for ion implantation process tools using a KLA-Tencor AIT fusion darkfield defect inspection tool. The method included the use of automatic defect classification (iADC) to provide high signal to noise for the defects of interest.
PowerChip (PSC) Fab 12A是在台湾新建的300毫米DRAM晶圆厂。PSC Fab 12A已经确定，由于高测试晶圆成本和工艺工具生产率降低，在300毫米的空白晶圆缺陷监测是不够的。此外，集成缺陷和一些工具缺陷不会发生在空白测试晶圆上。由于这些原因，PSC 12A希望研究使用图案产品晶圆进行工具监控。这项工作描述了如何使用KLA-Tencor AIT融合暗场缺陷检测工具实现离子注入过程工具的图案晶圆工具监测方法。该方法包括使用自动缺陷分类(iADC)为感兴趣的缺陷提供高噪声信号。
{"title":"Defect tool monitoring of process equipment by AIT fusion","authors":"L. Lin, F. Kuo, C. Lee, C. Broughton, R. Yang, J. Liao, J. Wang","doi":"10.1109/SMTW.2004.1393747","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393747","url":null,"abstract":"PowerChip (PSC) Fab 12A is a newly built 300 mm DRAM fab in Taiwan. PSC Fab 12A has identified that blank wafer defect monitoring is not adequate at 300 mm due to high test wafer cost and reduced process tool productivity. Aditionally, integration defects and some tool-induced defects do not occur on blank test wafers. For these reasons PSC 12A wanted to investigate using patterned product wafers for tool monitoring. This work describes how a patterned wafer tool monitor method was implemented for ion implantation process tools using a KLA-Tencor AIT fusion darkfield defect inspection tool. The method included the use of automatic defect classification (iADC) to provide high signal to noise for the defects of interest.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128281036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393763
E. Liu, Chun-Cheng Yi
The ever changing and the more competitive hi-tech environment, the business units always have the profit and product as first priority. But normally the wishes are not always come true, some outrages can prohibit the managers to reach their business goal. One of the example is the semiconductor business are very good in 1999. No one will expect that there will be a power outage (once in a 10 years Taipower history in Hsin Chu area). The following is the 100 years catastrophic earthquake in September 21. Around the world, there are lots of catastrophic events like Iraq wars, 911 terrorist attack and nature disaster, which might impact the business. The question that is raised by senior managers is: (1) are the events predictable? (2) any strategies to control the damages? (3) does the events cause crisis or opportunity? This work discusses game theory developed by John Von Neumman and Oskar Morgenstern on the strategic management to combine with the theory of risk management to see any opportunity that a business can turn the risk into opportunity. The game theory includes: (1) how to be insight in the chaos (2) decision model in the uncertainty (3) cost-effectiveness analysis in the risk control. Four risk management strategies are adopted as (1) risk avoidance (2) risk mitigation (3) risk transfer and (4) risk reduction are assessed in different scenarios by using the game theory. It is a new logic regarding to implement the strategic management methodology in risk management which intend to help senior managers to use their business habit which include concerns of the risk in their decision making process. And the paper will provide some ideas of planning and implementation of the risk management strategies in the decision making process.
{"title":"Risk management strategy for semiconductor fabs - started from game theory","authors":"E. Liu, Chun-Cheng Yi","doi":"10.1109/SMTW.2004.1393763","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393763","url":null,"abstract":"The ever changing and the more competitive hi-tech environment, the business units always have the profit and product as first priority. But normally the wishes are not always come true, some outrages can prohibit the managers to reach their business goal. One of the example is the semiconductor business are very good in 1999. No one will expect that there will be a power outage (once in a 10 years Taipower history in Hsin Chu area). The following is the 100 years catastrophic earthquake in September 21. Around the world, there are lots of catastrophic events like Iraq wars, 911 terrorist attack and nature disaster, which might impact the business. The question that is raised by senior managers is: (1) are the events predictable? (2) any strategies to control the damages? (3) does the events cause crisis or opportunity? This work discusses game theory developed by John Von Neumman and Oskar Morgenstern on the strategic management to combine with the theory of risk management to see any opportunity that a business can turn the risk into opportunity. The game theory includes: (1) how to be insight in the chaos (2) decision model in the uncertainty (3) cost-effectiveness analysis in the risk control. Four risk management strategies are adopted as (1) risk avoidance (2) risk mitigation (3) risk transfer and (4) risk reduction are assessed in different scenarios by using the game theory. It is a new logic regarding to implement the strategic management methodology in risk management which intend to help senior managers to use their business habit which include concerns of the risk in their decision making process. And the paper will provide some ideas of planning and implementation of the risk management strategies in the decision making process.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393765
L. Wang, B. Bridgman, G. Klein, Liying Wu, J. Darilek
We observed junction leakage caused by cobalt silicide defects in high-density and high-performance VLSI semiconductor production. We found the cobalt silicide defects were formed due to a small amount of oxygen present during the cobalt silicide film formation. Strict control of silicide process to prevent cobalt silicide formation in the presence of oxygen has effectively reduced the defects and improved shallow junction leakage characteristics.
{"title":"Study of junction leakage caused by cobalt silicide defects","authors":"L. Wang, B. Bridgman, G. Klein, Liying Wu, J. Darilek","doi":"10.1109/SMTW.2004.1393765","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393765","url":null,"abstract":"We observed junction leakage caused by cobalt silicide defects in high-density and high-performance VLSI semiconductor production. We found the cobalt silicide defects were formed due to a small amount of oxygen present during the cobalt silicide film formation. Strict control of silicide process to prevent cobalt silicide formation in the presence of oxygen has effectively reduced the defects and improved shallow junction leakage characteristics.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"30 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120882529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393753
F. Chang, Hsien-Ching Huang, Szu-Hung Yang, S. Kuo
In thick metal process with ultra low pattern density, the defined metal line easily suffered metal corrosion defect and passivation swelling defect (can not detect Cl element) issue. Poor metal sidewall profile or the profile with much polymer remaining was the suspected root cause of metal corrosion defect. The defect showed the reliability concern, so an improved method was necessary to reduce the defect. For improving the corrosion defect, dry etch recipe and strip procedure optimization showed be the solution to reduce the defect. Dry etch recipe was the major focus because the evidence showed poor sidewall profile would trap more polymer by-product. Thus, dry etch recipe developing specially focused on metal sidewall profile improvement and polymer by-product reduction. The optimized etch recipe passed corrosion test, even at high RF hours of dry etchers. Optical microscope inspection also couldn't detect any swelling defect. All testing items including WAT (wafer acceptance test) and yield got comparable or even better result to the condition before improvement. The paper mainly described how to improve metal corrosion and passivation swelling defect. It also provided some hints to understand the two kinds of defects further.
{"title":"Metal corrosion and passivation swelling defect study of ultra low pattern density thick metal etch process","authors":"F. Chang, Hsien-Ching Huang, Szu-Hung Yang, S. Kuo","doi":"10.1109/SMTW.2004.1393753","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393753","url":null,"abstract":"In thick metal process with ultra low pattern density, the defined metal line easily suffered metal corrosion defect and passivation swelling defect (can not detect Cl element) issue. Poor metal sidewall profile or the profile with much polymer remaining was the suspected root cause of metal corrosion defect. The defect showed the reliability concern, so an improved method was necessary to reduce the defect. For improving the corrosion defect, dry etch recipe and strip procedure optimization showed be the solution to reduce the defect. Dry etch recipe was the major focus because the evidence showed poor sidewall profile would trap more polymer by-product. Thus, dry etch recipe developing specially focused on metal sidewall profile improvement and polymer by-product reduction. The optimized etch recipe passed corrosion test, even at high RF hours of dry etchers. Optical microscope inspection also couldn't detect any swelling defect. All testing items including WAT (wafer acceptance test) and yield got comparable or even better result to the condition before improvement. The paper mainly described how to improve metal corrosion and passivation swelling defect. It also provided some hints to understand the two kinds of defects further.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131835481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393698
D. Yang
Observation and analysis of the global IC industrial evolution indicates good opportunity for Taiwan to become the SoC implementation center in the world to meet the emerging demand for outsourcing of SoC products and solutions-to leverage and to follow the success of IC/PC manufacturing outsourcing business in Taiwan.
{"title":"The outsourcing of SoC product development: Taiwan as the global center for SoC implementation","authors":"D. Yang","doi":"10.1109/SMTW.2004.1393698","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393698","url":null,"abstract":"Observation and analysis of the global IC industrial evolution indicates good opportunity for Taiwan to become the SoC implementation center in the world to meet the emerging demand for outsourcing of SoC products and solutions-to leverage and to follow the success of IC/PC manufacturing outsourcing business in Taiwan.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128121409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393722
Yi-Ko-Chen, S. Tso, Chung-I Chang, Tings Wang
Defects coming from backend metal process always impact device yield seriously, and it is hard to be repaired in the DRAM manufacturing. A good inline monitor mechanism is a key factor to have a fast and stable yield improvement. Most of defect monitors take measurements on some major process layers, due to the limit capacity of inspection tool and cost issue. Sampling monitor has a potential risk to miss some killer defect and cause yield drop. How to effectively find the killer and use an inline monitor mechanism to stop the impact tool or process is very important. This work addresses how to use the defect sampling inspection to control well the metal layer baseline defect and combine with the inline advanced process control (APC) mechanism to in-situ control the killer defects on the non-sampled wafer or non-monitored layer.
{"title":"An efficient yield enhancement from inline defect control and in-situ advanced process control","authors":"Yi-Ko-Chen, S. Tso, Chung-I Chang, Tings Wang","doi":"10.1109/SMTW.2004.1393722","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393722","url":null,"abstract":"Defects coming from backend metal process always impact device yield seriously, and it is hard to be repaired in the DRAM manufacturing. A good inline monitor mechanism is a key factor to have a fast and stable yield improvement. Most of defect monitors take measurements on some major process layers, due to the limit capacity of inspection tool and cost issue. Sampling monitor has a potential risk to miss some killer defect and cause yield drop. How to effectively find the killer and use an inline monitor mechanism to stop the impact tool or process is very important. This work addresses how to use the defect sampling inspection to control well the metal layer baseline defect and combine with the inline advanced process control (APC) mechanism to in-situ control the killer defects on the non-sampled wafer or non-monitored layer.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393756
C. Liao, T. Duh, T. Yang, S. Lan, C.W. Liu, T.T. Yang, J. Hsu, H.Y. Shao
A /spl pi/ technology (= particle-enhanced isolation) was proposed to employ energetic proton beams on the already-manufactured mixed-mode IC wafers (prior to packaging) for the suppression of undesirable substrate coupling (C. P. Liao et al., April 4, 2000). However, up to this day the physics behind this proton-caused defect phase is never clear. An effective 1-level defect model is constructed using experimental results and existing single-trap-level theory (Moll J. L. 1964) and TRIM (or SRIM) (http://www.srim.org/) code-simulated parameters. The found effective single trap level (E/spl tau/) is at about +0.24 eV in n-Si and at -0.34 eV in p-Si, measuring from the center of the energy band-gap.
A /spl pi/技术(=粒子增强隔离)被提议在已经制造的混合模式IC晶圆上(在封装之前)使用高能质子束来抑制不良的衬底耦合(c.p. Liao等人，2000年4月4日)。然而，直到今天，质子引起的缺陷阶段背后的物理原理还不清楚。利用实验结果和现有的单阱级理论(Moll J. L. 1964)以及TRIM(或SRIM) (http://www.srim.org/)代码模拟参数，构建了有效的一级缺陷模型。发现的有效单阱能级(E/spl tau/)在n-Si中约为+0.24 eV，在p-Si中约为-0.34 eV，从能带隙中心测量。
{"title":"An effective one-trap-level CAD model for the general SOC integration platform - particle-beam stand (PBS) - when modeling proton-caused local semi-insulating regions","authors":"C. Liao, T. Duh, T. Yang, S. Lan, C.W. Liu, T.T. Yang, J. Hsu, H.Y. Shao","doi":"10.1109/SMTW.2004.1393756","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393756","url":null,"abstract":"A /spl pi/ technology (= particle-enhanced isolation) was proposed to employ energetic proton beams on the already-manufactured mixed-mode IC wafers (prior to packaging) for the suppression of undesirable substrate coupling (C. P. Liao et al., April 4, 2000). However, up to this day the physics behind this proton-caused defect phase is never clear. An effective 1-level defect model is constructed using experimental results and existing single-trap-level theory (Moll J. L. 1964) and TRIM (or SRIM) (http://www.srim.org/) code-simulated parameters. The found effective single trap level (E/spl tau/) is at about +0.24 eV in n-Si and at -0.34 eV in p-Si, measuring from the center of the energy band-gap.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115243959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393740
L. Hsu
In case of plasma etch for hard mask dual-doped polysilicon gate application, interferometry endpoint (IEP) technique provided additional margin for protecting the thin gate dielectric as opposed to optical emission spectroscopy (OES) method. This article proposed a theoretical model to simulate the interferometric signal for the etching process control. A good correlation was found between the fitting data and practical IEP signal. This model would be helpful to analyze the potential incoming variations that might affect the endpoint control. The presence of underlaying field oxide in device wafer could be a dominant factor to shift the IEP curve.
{"title":"An optical interference model to analyze interferometry endpoint signal for process control of polysilicon gate etch","authors":"L. Hsu","doi":"10.1109/SMTW.2004.1393740","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393740","url":null,"abstract":"In case of plasma etch for hard mask dual-doped polysilicon gate application, interferometry endpoint (IEP) technique provided additional margin for protecting the thin gate dielectric as opposed to optical emission spectroscopy (OES) method. This article proposed a theoretical model to simulate the interferometric signal for the etching process control. A good correlation was found between the fitting data and practical IEP signal. This model would be helpful to analyze the potential incoming variations that might affect the endpoint control. The presence of underlaying field oxide in device wafer could be a dominant factor to shift the IEP curve.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128175107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393729
T. Kang, Chih-Cheng Wang, B. Tsui, Yuan-Hsin Li
Experiments indicate that higher HfO/sub 2//oxide etching selectivity in IPA/HF solution as compared to DI water/HF solution. Although DI water/HF solution is acceptable for some HfO/sub 2/ and CVD oxide films, from an integration point of view, the process window is smaller than IPA/HF solution. It is believed that adequately damaged HfO/sub 2/ and annealed CVD oxides will result in considerably high HfO/sub 2//CVD oxide etching selectivity in IPA/HF solution.
{"title":"Selectivity investigation of HfO/sub 2/ to oxide using wet etching","authors":"T. Kang, Chih-Cheng Wang, B. Tsui, Yuan-Hsin Li","doi":"10.1109/SMTW.2004.1393729","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393729","url":null,"abstract":"Experiments indicate that higher HfO/sub 2//oxide etching selectivity in IPA/HF solution as compared to DI water/HF solution. Although DI water/HF solution is acceptable for some HfO/sub 2/ and CVD oxide films, from an integration point of view, the process window is smaller than IPA/HF solution. It is believed that adequately damaged HfO/sub 2/ and annealed CVD oxides will result in considerably high HfO/sub 2//CVD oxide etching selectivity in IPA/HF solution.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114685523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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