Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509503
M. Kudoh, Y. Hoshi, S. Momota, T. Fujihira, K. Sakurai
The effect of the structure of current sensing IGBT on the temperature dependence of current sensing ratio has been investigated to improve the accuracy of over-current protection in intelligent power modules. The operation physics of the current sensing IGBT analyzed by computer simulation and experimental results of the improved performance of the current sensing IGBT are presented.
{"title":"Current sensing IGBT for future intelligent power module","authors":"M. Kudoh, Y. Hoshi, S. Momota, T. Fujihira, K. Sakurai","doi":"10.1109/ISPSD.1996.509503","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509503","url":null,"abstract":"The effect of the structure of current sensing IGBT on the temperature dependence of current sensing ratio has been investigated to improve the accuracy of over-current protection in intelligent power modules. The operation physics of the current sensing IGBT analyzed by computer simulation and experimental results of the improved performance of the current sensing IGBT are presented.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122897245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509494
M. Yamaguchi, T. Ogura, H. Ninomiya, H. Ohashi
A 4.5 kV IGBT mode turn-off thyristor (IGTT) with optimized mode-transition for realizing a low power loss, that is, a low forward voltage drop (V/sub f/) and a low turn-off loss (E/sub off/) is described for the first time. The device concept of optimizing the vertical carrier distribution was demonstrated by the IGBT mode turn-off operation combined with the proton(H/sup +/)-irradiation technique. The E/sub off/ value of 18 mJ/cm/sup 2/ was attained with V/sub f/ of 2.1 V at an anode current density of 25 A/cm/sup 2/. This value of E/sub off/ is 30 to 35% smaller than that for conventional MOS-gated thyristors. As a result, the trade-off relation between V/sub f/ and E/sub off/ is greatly improved for 4.5 kV devices.
{"title":"Mode-transition optimized 4.5 kV IGTT (IGBT mode turn-off thyristor)","authors":"M. Yamaguchi, T. Ogura, H. Ninomiya, H. Ohashi","doi":"10.1109/ISPSD.1996.509494","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509494","url":null,"abstract":"A 4.5 kV IGBT mode turn-off thyristor (IGTT) with optimized mode-transition for realizing a low power loss, that is, a low forward voltage drop (V/sub f/) and a low turn-off loss (E/sub off/) is described for the first time. The device concept of optimizing the vertical carrier distribution was demonstrated by the IGBT mode turn-off operation combined with the proton(H/sup +/)-irradiation technique. The E/sub off/ value of 18 mJ/cm/sup 2/ was attained with V/sub f/ of 2.1 V at an anode current density of 25 A/cm/sup 2/. This value of E/sub off/ is 30 to 35% smaller than that for conventional MOS-gated thyristors. As a result, the trade-off relation between V/sub f/ and E/sub off/ is greatly improved for 4.5 kV devices.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121461974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509459
D. Alok, B. J. Baliga
High voltage (700 V), planar, 6H-SiC N/sup +/-P junction diodes have been successfully fabricated by nitrogen implantation at room temperature using a deposited and patterned silicon dioxide layer as the mask. The diodes showed excellent rectification and were able to operate at temperatures as high as 250/spl deg/C with leakage current density less than 1/spl times/10/sup -4/ A/cm/sup 2/. The dominant current conduction mechanism during forward bias was found to be recombination in the depletion region. The forward voltage drop of these diodes at 100 A/cm/sup 2/ was found to be high (13.5 V) due to the large parasitic series resistance of the thick p-type substrate. The series resistance was found to decrease with increasing temperature due to improved ionization of the dopant in the P-type substrate leading to a reduction in forward drop.
{"title":"Nitrogen implanted high voltage, planar, 6H-SiC N/sup +/-P junction diodes","authors":"D. Alok, B. J. Baliga","doi":"10.1109/ISPSD.1996.509459","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509459","url":null,"abstract":"High voltage (700 V), planar, 6H-SiC N/sup +/-P junction diodes have been successfully fabricated by nitrogen implantation at room temperature using a deposited and patterned silicon dioxide layer as the mask. The diodes showed excellent rectification and were able to operate at temperatures as high as 250/spl deg/C with leakage current density less than 1/spl times/10/sup -4/ A/cm/sup 2/. The dominant current conduction mechanism during forward bias was found to be recombination in the depletion region. The forward voltage drop of these diodes at 100 A/cm/sup 2/ was found to be high (13.5 V) due to the large parasitic series resistance of the thick p-type substrate. The series resistance was found to decrease with increasing temperature due to improved ionization of the dopant in the P-type substrate leading to a reduction in forward drop.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129006517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509464
N. Iwamuro, Y. Harada, T. Iwaana, Y. Hoshi, Y. Seki
2nd generation dual gate MOS thyristor (2nd gen.-DGMOS) with 900 V blocking capability are presented to realize an extremely excellent trade-off characteristic between an on-state voltage drop and a turn-off loss with a high turn-off capability and to overcome the IGBT's characteristics for the first time. A superior on-state voltage drop (Von) of 1.29 V at 10 A(71.3 A/cm/sup 2/) with the turn-off loss (Eoff) of 101 /spl mu/J is successfully achieved. These values of Von, Eoff indicate the much superior trade-off characteristic to the IGBT. Furthermore, it should be noted that the 2nd gen.-DGMOS achieves better turn-off capability of approximately 500 A/cm/sup 2/ in a voltage resonant circuit, which is 3.0 times higher than that of the conventional DGMOS.
{"title":"2nd generation dual gate MOS thyristor","authors":"N. Iwamuro, Y. Harada, T. Iwaana, Y. Hoshi, Y. Seki","doi":"10.1109/ISPSD.1996.509464","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509464","url":null,"abstract":"2nd generation dual gate MOS thyristor (2nd gen.-DGMOS) with 900 V blocking capability are presented to realize an extremely excellent trade-off characteristic between an on-state voltage drop and a turn-off loss with a high turn-off capability and to overcome the IGBT's characteristics for the first time. A superior on-state voltage drop (Von) of 1.29 V at 10 A(71.3 A/cm/sup 2/) with the turn-off loss (Eoff) of 101 /spl mu/J is successfully achieved. These values of Von, Eoff indicate the much superior trade-off characteristic to the IGBT. Furthermore, it should be noted that the 2nd gen.-DGMOS achieves better turn-off capability of approximately 500 A/cm/sup 2/ in a voltage resonant circuit, which is 3.0 times higher than that of the conventional DGMOS.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121302112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509507
S. Shinohara, T. Suzuki, K. Tanino, H. Kobayashi, Y. Hasegawa
A new 8 mm-profile power module for high-frequency applications is described. This module exhibits low inductances of less than 4 nH for the terminals and a low thermal resistance of 0.234/spl deg/W/cm/sup 2/, providing less assembly time by using a unique double-layered and terminal-integrated AlN substrate. Paralleled MOSFETs in this module demonstrate 500 V-50 A switching at 10 MHz.
{"title":"A novel low-profile power module aimed at high-frequency applications","authors":"S. Shinohara, T. Suzuki, K. Tanino, H. Kobayashi, Y. Hasegawa","doi":"10.1109/ISPSD.1996.509507","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509507","url":null,"abstract":"A new 8 mm-profile power module for high-frequency applications is described. This module exhibits low inductances of less than 4 nH for the terminals and a low thermal resistance of 0.234/spl deg/W/cm/sup 2/, providing less assembly time by using a unique double-layered and terminal-integrated AlN substrate. Paralleled MOSFETs in this module demonstrate 500 V-50 A switching at 10 MHz.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509451
T. Efland, D. Skelton, S. Keller, K. Frank, Q. Mai
In this paper, results are discussed from work completed on logic level low voltage power PMOS switches. The devices were fabricated using base line 7 V rated PMOS from an existing scaleable technology and applying power device design techniques to the structure. The goals were to demonstrate area efficient high current low on resistance switches with fast switching and robust performance in an SO8 form factor. Device performance achieved was R/sub dscn/=65 m/spl Omega/@V/sub gs/=-5.0 V, I/sub ds/=-6 A with UIS switching up to 40 A at V/sub dd/=-6 V; this device is shown alongside an 80% shrunk version. A 40 m/spl Omega/ @ V/sub gs/=-5.0 V, I/sub ds/=-12 A version was demonstrated and is also reported in this work. Competitive R/sub sp/ was characterized for both N and P channel 7 V rated devices.
{"title":"VLSI CMOS fabrication modules combine with power device methods to produce 40 m/spl Omega/ and 65 m/spl Omega/, 7 V logic level P-power FETs","authors":"T. Efland, D. Skelton, S. Keller, K. Frank, Q. Mai","doi":"10.1109/ISPSD.1996.509451","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509451","url":null,"abstract":"In this paper, results are discussed from work completed on logic level low voltage power PMOS switches. The devices were fabricated using base line 7 V rated PMOS from an existing scaleable technology and applying power device design techniques to the structure. The goals were to demonstrate area efficient high current low on resistance switches with fast switching and robust performance in an SO8 form factor. Device performance achieved was R/sub dscn/=65 m/spl Omega/@V/sub gs/=-5.0 V, I/sub ds/=-6 A with UIS switching up to 40 A at V/sub dd/=-6 V; this device is shown alongside an 80% shrunk version. A 40 m/spl Omega/ @ V/sub gs/=-5.0 V, I/sub ds/=-12 A version was demonstrated and is also reported in this work. Competitive R/sub sp/ was characterized for both N and P channel 7 V rated devices.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124285116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509450
S. Manzini, C. Contiero
The degradation induced by hot-electrons is investigated in small-size lateral and vertical DMOS transistors with voltage rating from 16 to 60 V integrable in a multi-power Bipolar-CMOS-DMOS mixed process with 1.2 /spl mu/m minimum lithography. Dedicated hot-electron tests are necessary to define the maximum operating drain and gate voltage of the devices. An empirical extrapolation model and a simplified scheme for accelerated qualification/reliability tests are proposed allowing one to define the hot-electron-limited safe operating area of DMOS transistors. A quasi-static extension of the model accounts for the hot-electron-induced degradation under a variety of dynamic bias-stress conditions.
{"title":"Hot-electron-induced degradation in high-voltage submicron DMOS transistors","authors":"S. Manzini, C. Contiero","doi":"10.1109/ISPSD.1996.509450","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509450","url":null,"abstract":"The degradation induced by hot-electrons is investigated in small-size lateral and vertical DMOS transistors with voltage rating from 16 to 60 V integrable in a multi-power Bipolar-CMOS-DMOS mixed process with 1.2 /spl mu/m minimum lithography. Dedicated hot-electron tests are necessary to define the maximum operating drain and gate voltage of the devices. An empirical extrapolation model and a simplified scheme for accelerated qualification/reliability tests are proposed allowing one to define the hot-electron-limited safe operating area of DMOS transistors. A quasi-static extension of the model accounts for the hot-electron-induced degradation under a variety of dynamic bias-stress conditions.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509453
K. Nakamura, T. Minato, T. Takahashi, H. Nakamura, M. Harada
We have investigated trench MOS gate power devices that utilize trench gate oxide over 20 nm in thickness. Our results show, for the first time, that the leakage characteristics of trench MOS capacitors have a particular local maximum in the leakage current. We call leakage characteristics of a trench MOS capacitor "camel's hump" leakage current. Moreover, the dielectric breakdown of the silicon dioxide (SiO/sub 2/) film in the trench occurs after a specific point. Experiments conducted affirm that the keen convex corner at the trench top edge is the main factor for determining the electrical property of a thick trench MOS gate oxide, and this fact is supported by numerical device simulation. The leakage current can be suppressed by utilizing chemical dry etching (CDE), followed by sacrificial high-temperature oxidation prior to gate oxidation. These factors are considered vital for the development of trench MOS gate power devices.
{"title":"Evaluation of thick silicon dioxides grown on trench MOS gate structures","authors":"K. Nakamura, T. Minato, T. Takahashi, H. Nakamura, M. Harada","doi":"10.1109/ISPSD.1996.509453","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509453","url":null,"abstract":"We have investigated trench MOS gate power devices that utilize trench gate oxide over 20 nm in thickness. Our results show, for the first time, that the leakage characteristics of trench MOS capacitors have a particular local maximum in the leakage current. We call leakage characteristics of a trench MOS capacitor \"camel's hump\" leakage current. Moreover, the dielectric breakdown of the silicon dioxide (SiO/sub 2/) film in the trench occurs after a specific point. Experiments conducted affirm that the keen convex corner at the trench top edge is the main factor for determining the electrical property of a thick trench MOS gate oxide, and this fact is supported by numerical device simulation. The leakage current can be suppressed by utilizing chemical dry etching (CDE), followed by sacrificial high-temperature oxidation prior to gate oxidation. These factors are considered vital for the development of trench MOS gate power devices.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509496
H. Satoh, Y. Shimoda
The dynamics of surge response, which influences surge-handling capability, for thyristor lightning surge protection devices were investigated by a two-dimensional numerical device simulation. Maximum power dissipation appears in the open-base avalanche transistor operation at turn-on. The power dissipation increases by a few orders of magnitude with increase in the input surge. On the other hand, turn-on time is shorter and changes by less than one order of magnitude, caused by the field-aiding effect. As a result, the energy dissipation, which converts to self-heating and influences surge-handling capability, increases with increase in the input surge. To improve surge-handling capability by designing for low energy dissipation, fast switching time is effective for the open-base avalanche transistor which has narrow base width and uses a thin substrate with large carrier lifetime.
{"title":"Two-dimensional analysis of surge response in thyristor lightning surge protection devices","authors":"H. Satoh, Y. Shimoda","doi":"10.1109/ISPSD.1996.509496","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509496","url":null,"abstract":"The dynamics of surge response, which influences surge-handling capability, for thyristor lightning surge protection devices were investigated by a two-dimensional numerical device simulation. Maximum power dissipation appears in the open-base avalanche transistor operation at turn-on. The power dissipation increases by a few orders of magnitude with increase in the input surge. On the other hand, turn-on time is shorter and changes by less than one order of magnitude, caused by the field-aiding effect. As a result, the energy dissipation, which converts to self-heating and influences surge-handling capability, increases with increase in the input surge. To improve surge-handling capability by designing for low energy dissipation, fast switching time is effective for the open-base avalanche transistor which has narrow base width and uses a thin substrate with large carrier lifetime.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114675499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509493
J. Sakano, H. Kobayashi, M. Nagusu, M. Mori
A novel Insulated Gate Controlled Thyristor (IGCT) is described. The IGCT has a MOSFET that controls the thyristor current, and a thyristor with floating p-base for a low on-state voltage drop. The 4 kV IGCT is fabricated using optimized field limiting rings and field plates, and shows a very low on-state voltage drop of 4.4 V, while that of a 4 kV IGRT is 5.6 V. However, the maximum controllable current of the IGCT is lower than that of the IGBT. The low on-state voltage drop and a high maximum controllable current have been accomplished by optimizing the p-base structure.
{"title":"4 kV insulated gate controlled thyristor with low on-state voltage drop","authors":"J. Sakano, H. Kobayashi, M. Nagusu, M. Mori","doi":"10.1109/ISPSD.1996.509493","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509493","url":null,"abstract":"A novel Insulated Gate Controlled Thyristor (IGCT) is described. The IGCT has a MOSFET that controls the thyristor current, and a thyristor with floating p-base for a low on-state voltage drop. The 4 kV IGCT is fabricated using optimized field limiting rings and field plates, and shows a very low on-state voltage drop of 4.4 V, while that of a 4 kV IGRT is 5.6 V. However, the maximum controllable current of the IGCT is lower than that of the IGBT. The low on-state voltage drop and a high maximum controllable current have been accomplished by optimizing the p-base structure.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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