Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509511
S. Tu, G. Tam, P. Tam, H. Tsoi, A. Taomoto
High-speed IGBTs fabricated using direct wafer bonding and implanted N+ buffer layer are described and analyzed in this paper. The trade-off between on-state voltage drop and turn-off fall time can be controlled by varying the N+ implant dose prior to the wafer bonding process. 800 V IGBTs with switching time less than 100 nanoseconds and V/sub ce(sat)/ as low as 1.4 V at 100 A/cm/sup 2/ have been obtained. This excellent performance is achieved without utilizing any conventional lifetime control techniques.
本文描述和分析了直接晶圆键合和注入N+缓冲层制备高速igbt的方法。在晶圆键合过程之前，可以通过改变N+植入剂量来控制导通状态电压降和关断下降时间之间的权衡。已经获得了开关时间小于100纳秒的800 V igbt，在100 A/cm/sup 2/下的V/sub (sat)/低至1.4 V。这种优异的性能是在不使用任何传统寿命控制技术的情况下实现的。
{"title":"Analysis of direct wafer bond IGBTs with heavily doped N+ buffer layer","authors":"S. Tu, G. Tam, P. Tam, H. Tsoi, A. Taomoto","doi":"10.1109/ISPSD.1996.509511","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509511","url":null,"abstract":"High-speed IGBTs fabricated using direct wafer bonding and implanted N+ buffer layer are described and analyzed in this paper. The trade-off between on-state voltage drop and turn-off fall time can be controlled by varying the N+ implant dose prior to the wafer bonding process. 800 V IGBTs with switching time less than 100 nanoseconds and V/sub ce(sat)/ as low as 1.4 V at 100 A/cm/sup 2/ have been obtained. This excellent performance is achieved without utilizing any conventional lifetime control techniques.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121174308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509500
S. Sridhar, B. J. Baliga
A new EST structure, in which the lateral N-channel MOSFET is isolated from the thyristor by using SIMOX technology to eliminate the parasitic thyristor, is presented. This structure exhibits high voltage current saturation beyond the breakdown voltage of the lateral N-channel MOSFET. It is shown with the aid of two-dimensional numerical simulations that the proposed SIMEST has a lower on-state voltage drop than the conventional EST and the IGBT, and an FBSOA comparable to that of an IGBT with identical design rules. Experimental results on the SIMEST fabricated with a 9 mask SIMOX Smart Power process are presented.
{"title":"The SIMEST: a new EST structure without parasitic thyristor achieved using SIMOX technology","authors":"S. Sridhar, B. J. Baliga","doi":"10.1109/ISPSD.1996.509500","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509500","url":null,"abstract":"A new EST structure, in which the lateral N-channel MOSFET is isolated from the thyristor by using SIMOX technology to eliminate the parasitic thyristor, is presented. This structure exhibits high voltage current saturation beyond the breakdown voltage of the lateral N-channel MOSFET. It is shown with the aid of two-dimensional numerical simulations that the proposed SIMEST has a lower on-state voltage drop than the conventional EST and the IGBT, and an FBSOA comparable to that of an IGBT with identical design rules. Experimental results on the SIMEST fabricated with a 9 mask SIMOX Smart Power process are presented.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509512
Y. Murakami, Y. Nakajima, T. Hayashi, T. Mihara
A normally-off bipolar-mode FET having a V/sub DSS/ of 700 V with n/sup +/-n/sup -/-n/sup +/ structure has been developed. The transistor has a new type trench-MOS structure. N/sup +/-source and n/sup -/-channel are sandwiched by deep trench-MOS structures whose potential is fixed to the ground. They act virtually as the gates of a long-channel JFET. The p-gate contacts with every insulating film, which controls the channel conditions by the potential of p-type inversion layer. When the gate is shorted, the channel withstands up to the avalanche condition. Furthermore, it has a V/sub DSO/ of about 400 V.
{"title":"Grounded-trench-MOS structure assisted normally-off bipolar-mode power FET","authors":"Y. Murakami, Y. Nakajima, T. Hayashi, T. Mihara","doi":"10.1109/ISPSD.1996.509512","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509512","url":null,"abstract":"A normally-off bipolar-mode FET having a V/sub DSS/ of 700 V with n/sup +/-n/sup -/-n/sup +/ structure has been developed. The transistor has a new type trench-MOS structure. N/sup +/-source and n/sup -/-channel are sandwiched by deep trench-MOS structures whose potential is fixed to the ground. They act virtually as the gates of a long-channel JFET. The p-gate contacts with every insulating film, which controls the channel conditions by the potential of p-type inversion layer. When the gate is shorted, the channel withstands up to the avalanche condition. Furthermore, it has a V/sub DSO/ of about 400 V.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115061555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509470
J. Evans, G. Amaratunga
This paper presents a new description of the operation of a power MOSFET which is aimed at assisting in the design of devices which operate at high current densities. We analyse the charge balances within a power MOSFET (DMOS or UMOS) and show how these conspire to dictate the operation of the device. We report on the manufacture of a UMOS device with 0.8 /spl mu/m cells with 0.4 /spl mu/m trench widths=540/spl times/10/sup 6/ cells/in/sup 2/.
{"title":"The behaviour of very high current density power MOSFETs","authors":"J. Evans, G. Amaratunga","doi":"10.1109/ISPSD.1996.509470","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509470","url":null,"abstract":"This paper presents a new description of the operation of a power MOSFET which is aimed at assisting in the design of devices which operate at high current densities. We analyse the charge balances within a power MOSFET (DMOS or UMOS) and show how these conspire to dictate the operation of the device. We report on the manufacture of a UMOS device with 0.8 /spl mu/m cells with 0.4 /spl mu/m trench widths=540/spl times/10/sup 6/ cells/in/sup 2/.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509466
M. Otsuki, M. Kirisawa, K. Sakurai
This paper describes the experimental results of new Dual Gate MOS Thyristor (DGMOS), which can be fabricated with the same process technology as IGBT. In order to investigate the mechanism of turn-off failure in a large chip, which occurs lower current density compared with smaller chip, 9.0/spl times/7.2 mm 600 V-DGMOS with internal gate interconnection have been evaluated. The inhomogenious current distribution is the major reason of turn-off failure. In order to realize higher current handling capability, the formation of lower resistance gate interconnection is one of the key technologies as well as developing the new cell structure which has higher latch-up immunity.
{"title":"A study on current handling capability of dual gate MOS thyristor (DGMOS)","authors":"M. Otsuki, M. Kirisawa, K. Sakurai","doi":"10.1109/ISPSD.1996.509466","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509466","url":null,"abstract":"This paper describes the experimental results of new Dual Gate MOS Thyristor (DGMOS), which can be fabricated with the same process technology as IGBT. In order to investigate the mechanism of turn-off failure in a large chip, which occurs lower current density compared with smaller chip, 9.0/spl times/7.2 mm 600 V-DGMOS with internal gate interconnection have been evaluated. The inhomogenious current distribution is the major reason of turn-off failure. In order to realize higher current handling capability, the formation of lower resistance gate interconnection is one of the key technologies as well as developing the new cell structure which has higher latch-up immunity.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129443469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509509
D. Burns, I. Deram, J. Mello, J. Morgan, I. Wan, F. Robb
High-voltage NPT-IGBTs (non-punchthrough IGBTs) offer reasonable on-state voltages, high short-circuit ruggedness, and minimal turn-off losses without lifetime killing. In addition, NPT-IGBTs have the potential to reduce fabrication costs as compared to conventional epitaxial IGBTs because they are fabricated on low cost bulk silicon substrates, while conventional IGBTs utilize thick, expensive epitaxial layers. The key to realizing this potential cost savings, however, is the development of a manufacturable thin-wafer back end process flow. This paper will discuss NPT-IGBT process optimization, aimed at increased manufacturability. Starting material specifications, backside process optimization, and thin-wafer manufacturability issues are addressed.
{"title":"NPT-IGBT-optimizing for manufacturability","authors":"D. Burns, I. Deram, J. Mello, J. Morgan, I. Wan, F. Robb","doi":"10.1109/ISPSD.1996.509509","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509509","url":null,"abstract":"High-voltage NPT-IGBTs (non-punchthrough IGBTs) offer reasonable on-state voltages, high short-circuit ruggedness, and minimal turn-off losses without lifetime killing. In addition, NPT-IGBTs have the potential to reduce fabrication costs as compared to conventional epitaxial IGBTs because they are fabricated on low cost bulk silicon substrates, while conventional IGBTs utilize thick, expensive epitaxial layers. The key to realizing this potential cost savings, however, is the development of a manufacturable thin-wafer back end process flow. This paper will discuss NPT-IGBT process optimization, aimed at increased manufacturability. Starting material specifications, backside process optimization, and thin-wafer manufacturability issues are addressed.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122692430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509454
N. Thapar, B. Jayant Baliga
In the conventional fabrication process of trench MOS-gate power devices, the isolation of polysilicon gate from the source metal is achieved by the local oxidation of polysilicon within the refilled trenches. This isolation scheme results in the formation of "Birds Beak" due to the unwanted oxidation of the silicon at the corners near mouth of the trenches. The formation of the birds beak imposes many critical design constraints on the fabrication of trench MOS-gate power devices. Fabrication process steps required to eliminate the birds beak and overcome these constraints are described in this paper. Trench MOS-gate power devices fabricated using the birds beak "free" gate isolation process have the highest channel density. The elimination of the birds beak also simplifies the fabrication of all the self-aligned and triple diffused trench MOS-gate power devices.
{"title":"Elimination of the \"Birds Beak\" in trench MOS-gate power semiconductor devices","authors":"N. Thapar, B. Jayant Baliga","doi":"10.1109/ISPSD.1996.509454","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509454","url":null,"abstract":"In the conventional fabrication process of trench MOS-gate power devices, the isolation of polysilicon gate from the source metal is achieved by the local oxidation of polysilicon within the refilled trenches. This isolation scheme results in the formation of \"Birds Beak\" due to the unwanted oxidation of the silicon at the corners near mouth of the trenches. The formation of the birds beak imposes many critical design constraints on the fabrication of trench MOS-gate power devices. Fabrication process steps required to eliminate the birds beak and overcome these constraints are described in this paper. Trench MOS-gate power devices fabricated using the birds beak \"free\" gate isolation process have the highest channel density. The elimination of the birds beak also simplifies the fabrication of all the self-aligned and triple diffused trench MOS-gate power devices.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509449
M. Aliahmad, C. Salama
This paper presents a 30 V line driver for telecommunication applications. The circuit (0.3 mm/sup 2/ in area) is implemented in a 5 V 0.8 /spl mu/m BiCMOS process using 30 V extended-drain MOS devices fully compatible with low voltage technology. The design uses a Quasi-Current Mirror output stage and is capable of delivering up to 30 mA to the load with an idle current of less than 1 mA. The line driver exhibits a bandwidth of 2 MHz with a phase margin of 45.
{"title":"A 30 V line driver in submicron BiCMOS technology","authors":"M. Aliahmad, C. Salama","doi":"10.1109/ISPSD.1996.509449","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509449","url":null,"abstract":"This paper presents a 30 V line driver for telecommunication applications. The circuit (0.3 mm/sup 2/ in area) is implemented in a 5 V 0.8 /spl mu/m BiCMOS process using 30 V extended-drain MOS devices fully compatible with low voltage technology. The design uses a Quasi-Current Mirror output stage and is capable of delivering up to 30 mA to the load with an idle current of less than 1 mA. The line driver exhibits a bandwidth of 2 MHz with a phase margin of 45.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124318231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509510
Y. Konishi, Y. Onishi, S. Momota, K. Sakurai
Application of local lifetime control by helium ion irradiation was studied to improve an IGBT's performance. Light ion irradiation enables the formation of recombination layers in silicon power devices at favorable area by accommodation of ion accelerative voltage, resulting in reduction of turn-off power dissipation loss. In a practical application of the ion irradiation, relatively large scattering of performance could take place because of the relatively large scattering of Si wafer thickness. However, over 20% reduction of the turn-off loss was successfully achieved without a large scattering of trade-off characteristics by an irradiation method which utilizes the defects formed by the passing ions for the first time.
{"title":"Optimized local lifetime control for the superior IGBTs","authors":"Y. Konishi, Y. Onishi, S. Momota, K. Sakurai","doi":"10.1109/ISPSD.1996.509510","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509510","url":null,"abstract":"Application of local lifetime control by helium ion irradiation was studied to improve an IGBT's performance. Light ion irradiation enables the formation of recombination layers in silicon power devices at favorable area by accommodation of ion accelerative voltage, resulting in reduction of turn-off power dissipation loss. In a practical application of the ion irradiation, relatively large scattering of performance could take place because of the relatively large scattering of Si wafer thickness. However, over 20% reduction of the turn-off loss was successfully achieved without a large scattering of trade-off characteristics by an irradiation method which utilizes the defects formed by the passing ions for the first time.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133706923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509456
E. Arnold, T. Letavic, S. Merchant, H. Bhimnathwala
High-temperature off-state and on-state characteristics of bulk-Si and thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically. The off-state leakage current in the SOI devices was only 1.5 nA//spl mu/m at 300/spl deg/C. The increase of on-resistance with temperature in the SOI devices is smaller than in the bulk-Si devices because of the heavier doping dictated by the RESURF principle. The reverse recovery time of the SOI device shows only slight temperature dependence. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications.
{"title":"High-temperature performance of SOI and bulk-silicon RESURF LDMOS transistors","authors":"E. Arnold, T. Letavic, S. Merchant, H. Bhimnathwala","doi":"10.1109/ISPSD.1996.509456","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509456","url":null,"abstract":"High-temperature off-state and on-state characteristics of bulk-Si and thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically. The off-state leakage current in the SOI devices was only 1.5 nA//spl mu/m at 300/spl deg/C. The increase of on-resistance with temperature in the SOI devices is smaller than in the bulk-Si devices because of the heavier doping dictated by the RESURF principle. The reverse recovery time of the SOI device shows only slight temperature dependence. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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