Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509469
K. Watabe, H. Akiyama, T. Terashima, S. Nobuto, M. Yamawaki, T. Hirao
We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 /spl mu/m CMOS process.
{"title":"A 0.8 /spl mu/m high voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI","authors":"K. Watabe, H. Akiyama, T. Terashima, S. Nobuto, M. Yamawaki, T. Hirao","doi":"10.1109/ISPSD.1996.509469","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509469","url":null,"abstract":"We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 /spl mu/m CMOS process.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129978307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509479
Jai Ho Choi, K. Saito, T. Yokota, A. Watanabe
A high-energy Al implantation technique has been developed for the fabrication of high-power semiconductor devices. By using an implantation energy of 0.5 MeV or higher with a dosage of 1/spl times/10/sup 15/ atoms/cm/sup 2/, we obtained a p-region profile without using a film to prevent out-diffusion.
{"title":"High-energy Al implantation techniques for power semiconductor devices","authors":"Jai Ho Choi, K. Saito, T. Yokota, A. Watanabe","doi":"10.1109/ISPSD.1996.509479","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509479","url":null,"abstract":"A high-energy Al implantation technique has been developed for the fabrication of high-power semiconductor devices. By using an implantation energy of 0.5 MeV or higher with a dosage of 1/spl times/10/sup 15/ atoms/cm/sup 2/, we obtained a p-region profile without using a film to prevent out-diffusion.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129712334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509480
H. Schulze, M. Ruff, B. Baur, F. Pfirsch, H. Kabza, U. Kellner
Light triggered 8 kV thyristors with a new type of integrated breakover diode were fabricated. This breakover diode is realized by a well-defined curvature of the junction between the p-base and the n-base. For this purpose, a "masked" Al diffusion is used. Five amplifying gate stages guarantee a safe turn-on behavior also in the case of overvoltage triggering. Additionally, a novel resistor structure, which is also controlled by the masked Al diffusion, was integrated between the amplifying gate stages.
{"title":"Light triggered 8 kV thyristors with a new type of integrated breakover diode","authors":"H. Schulze, M. Ruff, B. Baur, F. Pfirsch, H. Kabza, U. Kellner","doi":"10.1109/ISPSD.1996.509480","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509480","url":null,"abstract":"Light triggered 8 kV thyristors with a new type of integrated breakover diode were fabricated. This breakover diode is realized by a well-defined curvature of the junction between the p-base and the n-base. For this purpose, a \"masked\" Al diffusion is used. Five amplifying gate stages guarantee a safe turn-on behavior also in the case of overvoltage triggering. Additionally, a novel resistor structure, which is also controlled by the masked Al diffusion, was integrated between the amplifying gate stages.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"133 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131957456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509492
D. Križaj, S. Amon, G. Charitat
An innovative junction termination structure for efficient improvement of planar pn junction breakdown properties is studied. It is composed of a high-resistivity layer, connected to the anode junction and winding around it in a spiral fashion. Leakage current through the diffused resistor results in the spread of potential along the spiral resistor and reduction of high electric field at the junction curvature region. An optimized design with decaying spiral width and increasing spacing between the spiral turns leads to close to ideal breakdown voltages as confirmed by device modeling as well as experimental results.
{"title":"Diffused spiral junction termination structure: modeling and realization","authors":"D. Križaj, S. Amon, G. Charitat","doi":"10.1109/ISPSD.1996.509492","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509492","url":null,"abstract":"An innovative junction termination structure for efficient improvement of planar pn junction breakdown properties is studied. It is composed of a high-resistivity layer, connected to the anode junction and winding around it in a spiral fashion. Leakage current through the diffused resistor results in the spread of potential along the spiral resistor and reduction of high electric field at the junction curvature region. An optimized design with decaying spiral width and increasing spacing between the spiral turns leads to close to ideal breakdown voltages as confirmed by device modeling as well as experimental results.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"531 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123361402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509495
S. Eicher, F. Bauer, A. Weber, H. Zeller, W. Fichtner
A new type of full scale 4.5 kV/3 kA GTO has been developed, fabricated, and electrically characterized. The device utilizes a punchthrough concept with a buffer layer. To avoid the requirement of excessive gate currents for turn-on, the new GTO has a homogeneous anode layer without shorts. The anode has a very low efficiency, which allows efficient extraction of charge during turn-off. With the buffer layer, the new device has a significantly reduced wafer thickness as compared to conventional devices without buffer. This reduces switching as well as on-state losses. The turn-off losses of the best devices were reduced to one third of those of conventional GTOs and, at the same time, the on-state losses were decreased by more than one third.
{"title":"Punchthrough type GTO with buffer layer and homogeneous low efficiency anode structure","authors":"S. Eicher, F. Bauer, A. Weber, H. Zeller, W. Fichtner","doi":"10.1109/ISPSD.1996.509495","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509495","url":null,"abstract":"A new type of full scale 4.5 kV/3 kA GTO has been developed, fabricated, and electrically characterized. The device utilizes a punchthrough concept with a buffer layer. To avoid the requirement of excessive gate currents for turn-on, the new GTO has a homogeneous anode layer without shorts. The anode has a very low efficiency, which allows efficient extraction of charge during turn-off. With the buffer layer, the new device has a significantly reduced wafer thickness as compared to conventional devices without buffer. This reduces switching as well as on-state losses. The turn-off losses of the best devices were reduced to one third of those of conventional GTOs and, at the same time, the on-state losses were decreased by more than one third.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"693 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509483
M. A. Shibib
Experimental results of a lateral high voltage NPN transistor based on a lateral DMOS structure fabricated in a low cost power BiCMOS technology are presented. Common-emitter current gain of typical devices were about 300 for the lateral devices compared to about 100 for a vertical device. The lateral NPN devices had emitter to collector breakdown voltages of 30 and 70 volts depending on the length of the collector region.
{"title":"Experimental investigation of high voltage and high current gain of a lateral bipolar transistor based on a lateral DMOS structure","authors":"M. A. Shibib","doi":"10.1109/ISPSD.1996.509483","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509483","url":null,"abstract":"Experimental results of a lateral high voltage NPN transistor based on a lateral DMOS structure fabricated in a low cost power BiCMOS technology are presented. Common-emitter current gain of typical devices were about 300 for the lateral devices compared to about 100 for a vertical device. The lateral NPN devices had emitter to collector breakdown voltages of 30 and 70 volts depending on the length of the collector region.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509508
F. Bauer, H. Dettmer, W. Fichtner, H. Lendenmann, T. Stockmeier, U. Thiemann
A new high voltage IGBT concept with a blocking capability exceeding 4.5 kV is presented in this paper. The device features a conventional planar DMOS cell design. To compensate for the lack of injection enhancement at the cathode, the n-base width is minimized for the required blocking voltage employing a punchthrough design. To avoid the problems related to anode shorts embedded in highly conductive stopping layers, low injection efficiency of the p+emitter at the anode is realized with a homogeneous, transparent emitter layer. The properties of the emitter and buffer layers determine the injection efficiency of the anode and the electrical characteristics of the high voltage IGBTs. Experimental devices were demonstrated switching inductive loads at up to 70 A/cm/sup 2/ at 3 kV without using snubbers. These devices have short circuit ruggedness and endure peak power densities of 2 MW/cm/sup 2/ for several microseconds.
{"title":"Design considerations and characteristics of rugged punchthrough (PT) IGBTs with 4.5 kV blocking capability","authors":"F. Bauer, H. Dettmer, W. Fichtner, H. Lendenmann, T. Stockmeier, U. Thiemann","doi":"10.1109/ISPSD.1996.509508","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509508","url":null,"abstract":"A new high voltage IGBT concept with a blocking capability exceeding 4.5 kV is presented in this paper. The device features a conventional planar DMOS cell design. To compensate for the lack of injection enhancement at the cathode, the n-base width is minimized for the required blocking voltage employing a punchthrough design. To avoid the problems related to anode shorts embedded in highly conductive stopping layers, low injection efficiency of the p+emitter at the anode is realized with a homogeneous, transparent emitter layer. The properties of the emitter and buffer layers determine the injection efficiency of the anode and the electrical characteristics of the high voltage IGBTs. Experimental devices were demonstrated switching inductive loads at up to 70 A/cm/sup 2/ at 3 kV without using snubbers. These devices have short circuit ruggedness and endure peak power densities of 2 MW/cm/sup 2/ for several microseconds.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114267249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509460
R. Raghunathan, B. J. Baliga
Various edge termination techniques for silicon carbide power devices were investigated for their effectiveness in improving the breakdown characteristics using the Scanning Electron Microscope (SEM) in the Electron Beam Induced Current (EBIC) mode. This paper reports an EBIC analysis of the experimentally obtained results for three termination techniques: (a) Floating Metal field Ring (FMR) (b) REsistive Schottky barrier field Plate (RESP) (c) Argon Ion Implant termination. Argon Ion Implant termination was found to be most effective in spreading the depletion boundary at the surface. EBIC analysis on the RESP terminated diodes revealed that insufficient sheet resistance of the RESP layer caused an early breakdown in these diodes. FMR terminated diodes exhibited spreading of the depletion region beyond that indicated by numerical simulations without surface charge. Simulations performed to study the effect of negative surface charge indicate that a charge density of more than 1/spl times/10/sup 11/ cm/sup -2/ was required to cause substantial spreading of the depletion edge.
{"title":"EBIC investigation of edge termination techniques for silicon carbide power devices","authors":"R. Raghunathan, B. J. Baliga","doi":"10.1109/ISPSD.1996.509460","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509460","url":null,"abstract":"Various edge termination techniques for silicon carbide power devices were investigated for their effectiveness in improving the breakdown characteristics using the Scanning Electron Microscope (SEM) in the Electron Beam Induced Current (EBIC) mode. This paper reports an EBIC analysis of the experimentally obtained results for three termination techniques: (a) Floating Metal field Ring (FMR) (b) REsistive Schottky barrier field Plate (RESP) (c) Argon Ion Implant termination. Argon Ion Implant termination was found to be most effective in spreading the depletion boundary at the surface. EBIC analysis on the RESP terminated diodes revealed that insufficient sheet resistance of the RESP layer caused an early breakdown in these diodes. FMR terminated diodes exhibited spreading of the depletion region beyond that indicated by numerical simulations without surface charge. Simulations performed to study the effect of negative surface charge indicate that a charge density of more than 1/spl times/10/sup 11/ cm/sup -2/ was required to cause substantial spreading of the depletion edge.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509506
J. Onuki, M. Satou, S. Murakami, T. Morita, T. Yatsuo
To realize large-area, high-power devices, low temperature diffusion bonding between Al electrodes on both sides of the device and Au-plated Mo internal electrode foils has been investigated. Bonding was feasible below 573 K due to the formation of Au-Al intermetallic compound. Substantial reduction of the mounting force while keeping contact uniform was also possible. Reliability of the bond type devices is predicted from metallurgical viewpoint.
{"title":"A new low temperature diffusion bonding technology between large-area, high-power devices and internal Mo electrodes using Au-Al films","authors":"J. Onuki, M. Satou, S. Murakami, T. Morita, T. Yatsuo","doi":"10.1109/ISPSD.1996.509506","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509506","url":null,"abstract":"To realize large-area, high-power devices, low temperature diffusion bonding between Al electrodes on both sides of the device and Au-plated Mo internal electrode foils has been investigated. Bonding was feasible below 573 K due to the formation of Au-Al intermetallic compound. Substantial reduction of the mounting force while keeping contact uniform was also possible. Reliability of the bond type devices is predicted from metallurgical viewpoint.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125787891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509498
K. Lilja, W. Fichtner
An insulated-gate controlled thyristor is presented which has a saturating on-state current characteristic and a stable homogeneous current distribution during turn-on and turn-off. The design of the device and a proposed fabrication-process is discussed. The new device has the robust qualities of the IGBT (current saturation, homogeneous current distribution, insulated gate control), and the four-layer thyristor structure allows for a strong reduction in losses compared to the IGBT. A comparison by simulation for high-voltage devices shows that the losses can be reduced by a factor of 2-3 at 3 kV switching and by a factor of 4 at 6 kV switching, as compared to an optimized planar IGBT structure. We also show simulations comparing the stability of these devices against dynamic avalanche-induced current filamentation instabilities.
{"title":"A filamentation-free insulated-gate controlled thyristor and comparisons to the IGBT","authors":"K. Lilja, W. Fichtner","doi":"10.1109/ISPSD.1996.509498","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509498","url":null,"abstract":"An insulated-gate controlled thyristor is presented which has a saturating on-state current characteristic and a stable homogeneous current distribution during turn-on and turn-off. The design of the device and a proposed fabrication-process is discussed. The new device has the robust qualities of the IGBT (current saturation, homogeneous current distribution, insulated gate control), and the four-layer thyristor structure allows for a strong reduction in losses compared to the IGBT. A comparison by simulation for high-voltage devices shows that the losses can be reduced by a factor of 2-3 at 3 kV switching and by a factor of 4 at 6 kV switching, as compared to an optimized planar IGBT structure. We also show simulations comparing the stability of these devices against dynamic avalanche-induced current filamentation instabilities.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"397 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：