Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509492
D. Križaj, S. Amon, G. Charitat
An innovative junction termination structure for efficient improvement of planar pn junction breakdown properties is studied. It is composed of a high-resistivity layer, connected to the anode junction and winding around it in a spiral fashion. Leakage current through the diffused resistor results in the spread of potential along the spiral resistor and reduction of high electric field at the junction curvature region. An optimized design with decaying spiral width and increasing spacing between the spiral turns leads to close to ideal breakdown voltages as confirmed by device modeling as well as experimental results.
{"title":"Diffused spiral junction termination structure: modeling and realization","authors":"D. Križaj, S. Amon, G. Charitat","doi":"10.1109/ISPSD.1996.509492","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509492","url":null,"abstract":"An innovative junction termination structure for efficient improvement of planar pn junction breakdown properties is studied. It is composed of a high-resistivity layer, connected to the anode junction and winding around it in a spiral fashion. Leakage current through the diffused resistor results in the spread of potential along the spiral resistor and reduction of high electric field at the junction curvature region. An optimized design with decaying spiral width and increasing spacing between the spiral turns leads to close to ideal breakdown voltages as confirmed by device modeling as well as experimental results.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"531 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123361402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509495
S. Eicher, F. Bauer, A. Weber, H. Zeller, W. Fichtner
A new type of full scale 4.5 kV/3 kA GTO has been developed, fabricated, and electrically characterized. The device utilizes a punchthrough concept with a buffer layer. To avoid the requirement of excessive gate currents for turn-on, the new GTO has a homogeneous anode layer without shorts. The anode has a very low efficiency, which allows efficient extraction of charge during turn-off. With the buffer layer, the new device has a significantly reduced wafer thickness as compared to conventional devices without buffer. This reduces switching as well as on-state losses. The turn-off losses of the best devices were reduced to one third of those of conventional GTOs and, at the same time, the on-state losses were decreased by more than one third.
{"title":"Punchthrough type GTO with buffer layer and homogeneous low efficiency anode structure","authors":"S. Eicher, F. Bauer, A. Weber, H. Zeller, W. Fichtner","doi":"10.1109/ISPSD.1996.509495","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509495","url":null,"abstract":"A new type of full scale 4.5 kV/3 kA GTO has been developed, fabricated, and electrically characterized. The device utilizes a punchthrough concept with a buffer layer. To avoid the requirement of excessive gate currents for turn-on, the new GTO has a homogeneous anode layer without shorts. The anode has a very low efficiency, which allows efficient extraction of charge during turn-off. With the buffer layer, the new device has a significantly reduced wafer thickness as compared to conventional devices without buffer. This reduces switching as well as on-state losses. The turn-off losses of the best devices were reduced to one third of those of conventional GTOs and, at the same time, the on-state losses were decreased by more than one third.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"693 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509482
Nungpyo Hong, Yong-Woo Lee, Pil-Gyu Im, D. Cho, Jin-woong Hong
The high temperature-low expansion type epoxy resin used for molding material of power semiconductor elements is irradiated with an electron beam. It is found that the insulating characteristics of the molding material varied with electron beam irradiation conditions. The insulating characteristics of the molding material, such as dielectric breakdown voltage and volume resistivity, are investigated as a function of electron beam dose. As a result, the specimen which is irradiated with 4 Mrad has exhibited a high breakdown voltage and volume resistivity.
{"title":"The effect of electron beam irradiation on insulating characteristics of molding compound for power semiconductor modules","authors":"Nungpyo Hong, Yong-Woo Lee, Pil-Gyu Im, D. Cho, Jin-woong Hong","doi":"10.1109/ISPSD.1996.509482","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509482","url":null,"abstract":"The high temperature-low expansion type epoxy resin used for molding material of power semiconductor elements is irradiated with an electron beam. It is found that the insulating characteristics of the molding material varied with electron beam irradiation conditions. The insulating characteristics of the molding material, such as dielectric breakdown voltage and volume resistivity, are investigated as a function of electron beam dose. As a result, the specimen which is irradiated with 4 Mrad has exhibited a high breakdown voltage and volume resistivity.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"570 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509474
P. Dupuy, J. Dorkel, P. Tounsi, L. Borucki
This paper recalls how the two-port network theory can be introduced to solve the 3D heat flow equation in a multilayered plane structure. In this paper we present two pieces of software based on the application of this theory, which are used to analyze the thermal behavior of SmartMos circuits with a fairly good accuracy and short computational times. Finally, an illustration is given and some comparisons are made with experiments and an FE code.
{"title":"Rapid thermal modeling for smart-power and integrated multichip power circuit design","authors":"P. Dupuy, J. Dorkel, P. Tounsi, L. Borucki","doi":"10.1109/ISPSD.1996.509474","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509474","url":null,"abstract":"This paper recalls how the two-port network theory can be introduced to solve the 3D heat flow equation in a multilayered plane structure. In this paper we present two pieces of software based on the application of this theory, which are used to analyze the thermal behavior of SmartMos circuits with a fairly good accuracy and short computational times. Finally, an illustration is given and some comparisons are made with experiments and an FE code.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132326600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509491
D. Kinzer, J. Ajit, K. Wagers, D. Asselanis
The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.
{"title":"A high density self-aligned 4-mask planar VDMOS process","authors":"D. Kinzer, J. Ajit, K. Wagers, D. Asselanis","doi":"10.1109/ISPSD.1996.509491","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509491","url":null,"abstract":"The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131432078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509488
T. Fujihira, Y. Yano, S. Obinata, N. Kumagai, K. Sakurai
A new, cost-effective, high-voltage inter-connection technique for HVICs, named Self-Shielding, is proposed. To avoid the lowering of breakdown voltage of high-voltage devices affected by the electric potential of overlying interconnections, self-shielding technique utilizes only the native PN-junction structures of high-voltage devices themselves. No additional shielding structure is required even to realize a very high-voltage IC above 1000 V. Design concept and device structures are presented together with the experimental results on the operation of self-shielded 1200 V level-shifters.
{"title":"Self-shielding: new high-voltage inter-connection technique for HVICs","authors":"T. Fujihira, Y. Yano, S. Obinata, N. Kumagai, K. Sakurai","doi":"10.1109/ISPSD.1996.509488","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509488","url":null,"abstract":"A new, cost-effective, high-voltage inter-connection technique for HVICs, named Self-Shielding, is proposed. To avoid the lowering of breakdown voltage of high-voltage devices affected by the electric potential of overlying interconnections, self-shielding technique utilizes only the native PN-junction structures of high-voltage devices themselves. No additional shielding structure is required even to realize a very high-voltage IC above 1000 V. Design concept and device structures are presented together with the experimental results on the operation of self-shielded 1200 V level-shifters.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115848293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509472
R. Kurlagunda, B. J. Baliga
The Floating Base Thyristor (FBT) is a new thyristor structure proposed for obtaining a low on-state voltage drop during conduction and a good Forward Biased Safe Operating Area (FBSOA). This structure has highly doped P/sup +/ region in the floating P-base region to improve FBSOA. The FBT has two MOS gates-that will be hereafter referred to as the ON-gate and the OFF-gate. When both gates are biased positively, the device conducts with low forward voltage drop. When the OFF-gate is negatively biased the device operates in the IGBT mode and is able to saturate currents to high voltages. The effect of design parameters and temperature on latching current density and forward voltage drop of the FBT and the dependence of turnoff time with electron radiation dose are examined in this paper.
{"title":"The MOS-gated floating base thyristor: a new dual gate thyristor with improved forward biased safe operating area","authors":"R. Kurlagunda, B. J. Baliga","doi":"10.1109/ISPSD.1996.509472","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509472","url":null,"abstract":"The Floating Base Thyristor (FBT) is a new thyristor structure proposed for obtaining a low on-state voltage drop during conduction and a good Forward Biased Safe Operating Area (FBSOA). This structure has highly doped P/sup +/ region in the floating P-base region to improve FBSOA. The FBT has two MOS gates-that will be hereafter referred to as the ON-gate and the OFF-gate. When both gates are biased positively, the device conducts with low forward voltage drop. When the OFF-gate is negatively biased the device operates in the IGBT mode and is able to saturate currents to high voltages. The effect of design parameters and temperature on latching current density and forward voltage drop of the FBT and the dependence of turnoff time with electron radiation dose are examined in this paper.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124451427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509457
N. Yasuhara, H. Funaki, T. Matsudai, A. Nakagawa
This paper reports, for the first time, the experimentally obtained electrical characteristics of lateral injection enhanced insulated gate bipolar transistors (LIEGTs) on SOI. It is shown that optimized LIEGTs have twice as large a current capability as LIGBTs and attain the same turn-off characteristics. These results show that LIEGTs are attractive for the output devices of high voltage power ICs.
{"title":"Experimental verification of large current capability of lateral IEGTs on SOI","authors":"N. Yasuhara, H. Funaki, T. Matsudai, A. Nakagawa","doi":"10.1109/ISPSD.1996.509457","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509457","url":null,"abstract":"This paper reports, for the first time, the experimentally obtained electrical characteristics of lateral injection enhanced insulated gate bipolar transistors (LIEGTs) on SOI. It is shown that optimized LIEGTs have twice as large a current capability as LIGBTs and attain the same turn-off characteristics. These results show that LIEGTs are attractive for the output devices of high voltage power ICs.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115465318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509505
A. Chowdhury, B. Guenin, R. Groover, S. Anderson, E.J. Derian
Different design techniques to improve the thermal performance of a standard SOIC package have been evaluated and their thermal performance compared through thermal models by utilizing finite element analysis. It is shown that by enhancing the design of a standard SOIC package the thermal performance can be improved by as much as 46% over that of the standard design.
{"title":"Thermally-enhanced SOIC packages for power IC devices","authors":"A. Chowdhury, B. Guenin, R. Groover, S. Anderson, E.J. Derian","doi":"10.1109/ISPSD.1996.509505","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509505","url":null,"abstract":"Different design techniques to improve the thermal performance of a standard SOIC package have been evaluated and their thermal performance compared through thermal models by utilizing finite element analysis. It is shown that by enhancing the design of a standard SOIC package the thermal performance can be improved by as much as 46% over that of the standard design.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127198793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509468
T. R. Efland, P. Mei, D. Mosher, B. Todd
This paper discusses modeling and experimental development of self-aligned RESURF 60 V rated LDMOS power MOSFETs. The goals of this work were to provide state-of-the-art BV vs. R/sub sp/ performance RESURF devices using existing fabrication techniques capable of high current conduction. The devices were fabricated in a production environment with an additional RESURF implant added to the process. Best performance reported is BV=69 V, and R/sub sp/=0.82 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V which is the best to our knowledge in this voltage range. Large (18 m/spl Omega/) devices were demonstrated with linear performance up to 60 and 100 A @V/sub gs/=10 V and 15 V respectively. Thick third level metal was used to reduce surface interconnect debiasing.
{"title":"Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent R/sub sp/ vs BV performance","authors":"T. R. Efland, P. Mei, D. Mosher, B. Todd","doi":"10.1109/ISPSD.1996.509468","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509468","url":null,"abstract":"This paper discusses modeling and experimental development of self-aligned RESURF 60 V rated LDMOS power MOSFETs. The goals of this work were to provide state-of-the-art BV vs. R/sub sp/ performance RESURF devices using existing fabrication techniques capable of high current conduction. The devices were fabricated in a production environment with an additional RESURF implant added to the process. Best performance reported is BV=69 V, and R/sub sp/=0.82 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V which is the best to our knowledge in this voltage range. Large (18 m/spl Omega/) devices were demonstrated with linear performance up to 60 and 100 A @V/sub gs/=10 V and 15 V respectively. Thick third level metal was used to reduce surface interconnect debiasing.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128424225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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