Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509514
Y. Tomomatsu, E. Suekawa, T. Enjyoji, M. Takeda, H. Kondoh, H. Hagino, T. Yamada
Computer simulation for reverse recovery characteristics of a planar diode revealed that local heating occurred at the corner of the anode even when a surge voltage across the diode was lower than its static breakdown voltage. Analysis for origin of local heating resulted in a design principle for improving destruction immunity of the diode. Diodes designed according to the present principle showed excellent destruction immunity under high dIrr/dt condition.
{"title":"An analysis and improvement of destruction immunity during reverse recovery for high voltage planar diodes under high dIrr/dt condition","authors":"Y. Tomomatsu, E. Suekawa, T. Enjyoji, M. Takeda, H. Kondoh, H. Hagino, T. Yamada","doi":"10.1109/ISPSD.1996.509514","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509514","url":null,"abstract":"Computer simulation for reverse recovery characteristics of a planar diode revealed that local heating occurred at the corner of the anode even when a surge voltage across the diode was lower than its static breakdown voltage. Analysis for origin of local heating resulted in a design principle for improving destruction immunity of the diode. Diodes designed according to the present principle showed excellent destruction immunity under high dIrr/dt condition.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124914892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509486
M. S. Shekar, A. Hartular, B. Wrathall, R.K. Williams
This paper discusses the modeling of the thermal transient at the proximity of a dominant heat source in a 5 V Low Drop Out (LDO) regulator used in an automotive environment. The LDO regulator is designed using a 60 V BCD technology having a 2 /spl mu/m-linewidth and dual layer metal interconnect. A SPICE circuit model using spherical spreading of heat through silicon is developed to predict the transient thermal behavior of the LDO regulator. Simulations indicate a 65 mV drop in the output regulated voltage for a power pulse of 1.4 W through the output power transistor and are in excellent agreement with that obtained from experiments. The design of the thermal generator and the effect of the thermal resistance and capacitance on the output regulated voltage are also discussed.
本文讨论了汽车环境中使用的5v低降差(LDO)稳压器在主热源附近的热瞬态建模。LDO稳压器采用60 V BCD技术设计，线宽为2 /spl mu/m，采用双层金属互连。提出了一种利用热通过硅的球形扩散的SPICE电路模型来预测LDO调节器的瞬态热行为。仿真结果表明，当功率脉冲为1.4 W时，输出稳压降低65 mV，与实验结果非常吻合。讨论了热发生器的设计以及热阻和热容对输出稳压的影响。
{"title":"Modeling the thermal transients in automotive power ICs","authors":"M. S. Shekar, A. Hartular, B. Wrathall, R.K. Williams","doi":"10.1109/ISPSD.1996.509486","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509486","url":null,"abstract":"This paper discusses the modeling of the thermal transient at the proximity of a dominant heat source in a 5 V Low Drop Out (LDO) regulator used in an automotive environment. The LDO regulator is designed using a 60 V BCD technology having a 2 /spl mu/m-linewidth and dual layer metal interconnect. A SPICE circuit model using spherical spreading of heat through silicon is developed to predict the transient thermal behavior of the LDO regulator. Simulations indicate a 65 mV drop in the output regulated voltage for a power pulse of 1.4 W through the output power transistor and are in excellent agreement with that obtained from experiments. The design of the thermal generator and the effect of the thermal resistance and capacitance on the output regulated voltage are also discussed.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"9 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129978433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509491
D. Kinzer, J. Ajit, K. Wagers, D. Asselanis
The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.
{"title":"A high density self-aligned 4-mask planar VDMOS process","authors":"D. Kinzer, J. Ajit, K. Wagers, D. Asselanis","doi":"10.1109/ISPSD.1996.509491","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509491","url":null,"abstract":"The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131432078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509482
Nungpyo Hong, Yong-Woo Lee, Pil-Gyu Im, D. Cho, Jin-woong Hong
The high temperature-low expansion type epoxy resin used for molding material of power semiconductor elements is irradiated with an electron beam. It is found that the insulating characteristics of the molding material varied with electron beam irradiation conditions. The insulating characteristics of the molding material, such as dielectric breakdown voltage and volume resistivity, are investigated as a function of electron beam dose. As a result, the specimen which is irradiated with 4 Mrad has exhibited a high breakdown voltage and volume resistivity.
{"title":"The effect of electron beam irradiation on insulating characteristics of molding compound for power semiconductor modules","authors":"Nungpyo Hong, Yong-Woo Lee, Pil-Gyu Im, D. Cho, Jin-woong Hong","doi":"10.1109/ISPSD.1996.509482","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509482","url":null,"abstract":"The high temperature-low expansion type epoxy resin used for molding material of power semiconductor elements is irradiated with an electron beam. It is found that the insulating characteristics of the molding material varied with electron beam irradiation conditions. The insulating characteristics of the molding material, such as dielectric breakdown voltage and volume resistivity, are investigated as a function of electron beam dose. As a result, the specimen which is irradiated with 4 Mrad has exhibited a high breakdown voltage and volume resistivity.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"570 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509474
P. Dupuy, J. Dorkel, P. Tounsi, L. Borucki
This paper recalls how the two-port network theory can be introduced to solve the 3D heat flow equation in a multilayered plane structure. In this paper we present two pieces of software based on the application of this theory, which are used to analyze the thermal behavior of SmartMos circuits with a fairly good accuracy and short computational times. Finally, an illustration is given and some comparisons are made with experiments and an FE code.
{"title":"Rapid thermal modeling for smart-power and integrated multichip power circuit design","authors":"P. Dupuy, J. Dorkel, P. Tounsi, L. Borucki","doi":"10.1109/ISPSD.1996.509474","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509474","url":null,"abstract":"This paper recalls how the two-port network theory can be introduced to solve the 3D heat flow equation in a multilayered plane structure. In this paper we present two pieces of software based on the application of this theory, which are used to analyze the thermal behavior of SmartMos circuits with a fairly good accuracy and short computational times. Finally, an illustration is given and some comparisons are made with experiments and an FE code.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132326600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509472
R. Kurlagunda, B. J. Baliga
The Floating Base Thyristor (FBT) is a new thyristor structure proposed for obtaining a low on-state voltage drop during conduction and a good Forward Biased Safe Operating Area (FBSOA). This structure has highly doped P/sup +/ region in the floating P-base region to improve FBSOA. The FBT has two MOS gates-that will be hereafter referred to as the ON-gate and the OFF-gate. When both gates are biased positively, the device conducts with low forward voltage drop. When the OFF-gate is negatively biased the device operates in the IGBT mode and is able to saturate currents to high voltages. The effect of design parameters and temperature on latching current density and forward voltage drop of the FBT and the dependence of turnoff time with electron radiation dose are examined in this paper.
{"title":"The MOS-gated floating base thyristor: a new dual gate thyristor with improved forward biased safe operating area","authors":"R. Kurlagunda, B. J. Baliga","doi":"10.1109/ISPSD.1996.509472","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509472","url":null,"abstract":"The Floating Base Thyristor (FBT) is a new thyristor structure proposed for obtaining a low on-state voltage drop during conduction and a good Forward Biased Safe Operating Area (FBSOA). This structure has highly doped P/sup +/ region in the floating P-base region to improve FBSOA. The FBT has two MOS gates-that will be hereafter referred to as the ON-gate and the OFF-gate. When both gates are biased positively, the device conducts with low forward voltage drop. When the OFF-gate is negatively biased the device operates in the IGBT mode and is able to saturate currents to high voltages. The effect of design parameters and temperature on latching current density and forward voltage drop of the FBT and the dependence of turnoff time with electron radiation dose are examined in this paper.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124451427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509497
R. Sunkavalli, A. Tamba, B. J. Baliga
A new device called the DI Lateral insulated Field Controlled Thyristor (LIGFT) is introduced, which eliminates the parasitic thyristor latchup problem of the LIGBT. The LIGFT successfully integrates a high voltage lateral FCT with a series low voltage lateral MOSFET to create a unique MOS-gate controlled three terminal device. In comparison to the LIGBT, the LIGFT is experimentally shown to achieve a tremendous increase in maximum controllable current (RBSOA) and FBSOA by eliminating parasitic thyristor latchup, at the expense of an increase in on-state voltage drop.
{"title":"The DI lateral insulated gate field controlled thyristor (LIGFT)","authors":"R. Sunkavalli, A. Tamba, B. J. Baliga","doi":"10.1109/ISPSD.1996.509497","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509497","url":null,"abstract":"A new device called the DI Lateral insulated Field Controlled Thyristor (LIGFT) is introduced, which eliminates the parasitic thyristor latchup problem of the LIGBT. The LIGFT successfully integrates a high voltage lateral FCT with a series low voltage lateral MOSFET to create a unique MOS-gate controlled three terminal device. In comparison to the LIGBT, the LIGFT is experimentally shown to achieve a tremendous increase in maximum controllable current (RBSOA) and FBSOA by eliminating parasitic thyristor latchup, at the expense of an increase in on-state voltage drop.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130870636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509468
T. R. Efland, P. Mei, D. Mosher, B. Todd
This paper discusses modeling and experimental development of self-aligned RESURF 60 V rated LDMOS power MOSFETs. The goals of this work were to provide state-of-the-art BV vs. R/sub sp/ performance RESURF devices using existing fabrication techniques capable of high current conduction. The devices were fabricated in a production environment with an additional RESURF implant added to the process. Best performance reported is BV=69 V, and R/sub sp/=0.82 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V which is the best to our knowledge in this voltage range. Large (18 m/spl Omega/) devices were demonstrated with linear performance up to 60 and 100 A @V/sub gs/=10 V and 15 V respectively. Thick third level metal was used to reduce surface interconnect debiasing.
{"title":"Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent R/sub sp/ vs BV performance","authors":"T. R. Efland, P. Mei, D. Mosher, B. Todd","doi":"10.1109/ISPSD.1996.509468","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509468","url":null,"abstract":"This paper discusses modeling and experimental development of self-aligned RESURF 60 V rated LDMOS power MOSFETs. The goals of this work were to provide state-of-the-art BV vs. R/sub sp/ performance RESURF devices using existing fabrication techniques capable of high current conduction. The devices were fabricated in a production environment with an additional RESURF implant added to the process. Best performance reported is BV=69 V, and R/sub sp/=0.82 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V which is the best to our knowledge in this voltage range. Large (18 m/spl Omega/) devices were demonstrated with linear performance up to 60 and 100 A @V/sub gs/=10 V and 15 V respectively. Thick third level metal was used to reduce surface interconnect debiasing.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128424225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509457
N. Yasuhara, H. Funaki, T. Matsudai, A. Nakagawa
This paper reports, for the first time, the experimentally obtained electrical characteristics of lateral injection enhanced insulated gate bipolar transistors (LIEGTs) on SOI. It is shown that optimized LIEGTs have twice as large a current capability as LIGBTs and attain the same turn-off characteristics. These results show that LIEGTs are attractive for the output devices of high voltage power ICs.
{"title":"Experimental verification of large current capability of lateral IEGTs on SOI","authors":"N. Yasuhara, H. Funaki, T. Matsudai, A. Nakagawa","doi":"10.1109/ISPSD.1996.509457","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509457","url":null,"abstract":"This paper reports, for the first time, the experimentally obtained electrical characteristics of lateral injection enhanced insulated gate bipolar transistors (LIEGTs) on SOI. It is shown that optimized LIEGTs have twice as large a current capability as LIGBTs and attain the same turn-off characteristics. These results show that LIEGTs are attractive for the output devices of high voltage power ICs.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115465318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509505
A. Chowdhury, B. Guenin, R. Groover, S. Anderson, E.J. Derian
Different design techniques to improve the thermal performance of a standard SOIC package have been evaluated and their thermal performance compared through thermal models by utilizing finite element analysis. It is shown that by enhancing the design of a standard SOIC package the thermal performance can be improved by as much as 46% over that of the standard design.
{"title":"Thermally-enhanced SOIC packages for power IC devices","authors":"A. Chowdhury, B. Guenin, R. Groover, S. Anderson, E.J. Derian","doi":"10.1109/ISPSD.1996.509505","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509505","url":null,"abstract":"Different design techniques to improve the thermal performance of a standard SOIC package have been evaluated and their thermal performance compared through thermal models by utilizing finite element analysis. It is shown that by enhancing the design of a standard SOIC package the thermal performance can be improved by as much as 46% over that of the standard design.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127198793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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