Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399686
D. Brückmann, M. Hammes, A. Neubauer
A well-established receiver concept for wireless systems, e.g. according to the Bluetooth specification, is based on a low IF-architecture with a simple limiter used for digitization. This architecture can be applied with negligible performance degradation to simple 2-ary modulation schemes with constant envelope signals like GFSK. In order to achieve higher data rates, the wireless standards are enhanced with additional modes using more sophisticated modulation schemes like M-ary PSK. With respect to implementation costs and power consumption, it is desirable to realize a combined CPFSK/PSK-receiver, which performs digitization by simple comparators or 1-bit A/D-converters also for the higher data rate schemes. However, no severe performance degradation compared to a linear receiver can be accepted. In this contribution, it is shown how to achieve the required performance with a simple limiter in the receive path and optimized signal processing before and after quantization.
{"title":"A CPFSK/PSK-phase reconstruction-receiver for enhanced data rate Bluetooth systems","authors":"D. Brückmann, M. Hammes, A. Neubauer","doi":"10.1109/ICECS.2004.1399686","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399686","url":null,"abstract":"A well-established receiver concept for wireless systems, e.g. according to the Bluetooth specification, is based on a low IF-architecture with a simple limiter used for digitization. This architecture can be applied with negligible performance degradation to simple 2-ary modulation schemes with constant envelope signals like GFSK. In order to achieve higher data rates, the wireless standards are enhanced with additional modes using more sophisticated modulation schemes like M-ary PSK. With respect to implementation costs and power consumption, it is desirable to realize a combined CPFSK/PSK-receiver, which performs digitization by simple comparators or 1-bit A/D-converters also for the higher data rate schemes. However, no severe performance degradation compared to a linear receiver can be accepted. In this contribution, it is shown how to achieve the required performance with a simple limiter in the receive path and optimized signal processing before and after quantization.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89805864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399656
Zhichun Yang, Daoyi Xu, Jin Deng, Jianren Niu
Impulsive effects, which widely exist in various dynamical systems, including neural networks, can influence the dynamic behavior of systems just as delayed effects. A generalized model of neural networks involving variable delays and impulses is formulated. By introducing differential inequality with impulsive initial conditions and employing the properties of the M-matrix, we obtain new sufficient conditions ensuring global exponential stability of the impulsive delayed system. The results extend and improve those of earlier publications. An example and simulation are given to illustrate the theoretical results.
{"title":"New conditions for exponential stability of delay impulsive neural networks","authors":"Zhichun Yang, Daoyi Xu, Jin Deng, Jianren Niu","doi":"10.1109/ICECS.2004.1399656","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399656","url":null,"abstract":"Impulsive effects, which widely exist in various dynamical systems, including neural networks, can influence the dynamic behavior of systems just as delayed effects. A generalized model of neural networks involving variable delays and impulses is formulated. By introducing differential inequality with impulsive initial conditions and employing the properties of the M-matrix, we obtain new sufficient conditions ensuring global exponential stability of the impulsive delayed system. The results extend and improve those of earlier publications. An example and simulation are given to illustrate the theoretical results.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78547417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399659
E. Friedman
Summary form only given. Fundamental trends specific to high speed, high complexity systems are reviewed, emphasizing many of the primary issues that constrain existing and future digital and mixed-signal integrated systems. These issues are discussed in terms of the evolving criteria that affect each aspect of the VLSI design and synthesis process. Attention is placed on distinguishing between local and global issues. Topics such as dual V/sub t/ CMOS circuits and on-chip interconnect noise, determined by the local nature of the circuit structures, are compared and contrasted with larger issues that focus on the global nature of VLSI-based systems such as synchronization styles and clock and power distribution networks.
{"title":"Challenges in ultra deep submicrometer high performance VLSI circuits","authors":"E. Friedman","doi":"10.1109/ICECS.2004.1399659","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399659","url":null,"abstract":"Summary form only given. Fundamental trends specific to high speed, high complexity systems are reviewed, emphasizing many of the primary issues that constrain existing and future digital and mixed-signal integrated systems. These issues are discussed in terms of the evolving criteria that affect each aspect of the VLSI design and synthesis process. Attention is placed on distinguishing between local and global issues. Topics such as dual V/sub t/ CMOS circuits and on-chip interconnect noise, determined by the local nature of the circuit structures, are compared and contrasted with larger issues that focus on the global nature of VLSI-based systems such as synchronization styles and clock and power distribution networks.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75508645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399719
O. Cohen, Y. Nemirovsky
In this paper, we present a novel scheme for designing and fabricating a single axis scanning micro mirror. The device is the match of two chips using a flip chip bonder. In this paper, we describe mostly the top chip that includes the reflecting surface. The device is very low cost and electrostatically actuated with a relatively low voltage. We present the fabrication process scheme, based on wet etching of silicon wafers. We also present the motivation to use thin wafers, as much as 50 /spl mu/m thick, to reach a resonant frequency of 15-30 kHz, suitable for raster scanners such as retinal scan displays. Finally, we present a preliminary prototype produced by such a process.
本文提出了一种设计和制作单轴扫描微镜的新方案。该设备是使用倒装芯片键合器的两个芯片的匹配。本文主要描述包括反射面在内的顶部芯片。该装置成本非常低，并且采用相对较低的电压进行静电驱动。提出了基于湿法蚀刻硅片的制备工艺方案。我们还提出了使用厚度达50 /spl μ m /m的薄晶圆的动机，以达到15-30 kHz的谐振频率，适用于视网膜扫描显示器等光栅扫描仪。最后，我们给出了用这种工艺生产的一个初步样机。
{"title":"A novel design and fabrication method of scanning micro-mirror for retinal scan displays","authors":"O. Cohen, Y. Nemirovsky","doi":"10.1109/ICECS.2004.1399719","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399719","url":null,"abstract":"In this paper, we present a novel scheme for designing and fabricating a single axis scanning micro mirror. The device is the match of two chips using a flip chip bonder. In this paper, we describe mostly the top chip that includes the reflecting surface. The device is very low cost and electrostatically actuated with a relatively low voltage. We present the fabrication process scheme, based on wet etching of silicon wafers. We also present the motivation to use thin wafers, as much as 50 /spl mu/m thick, to reach a resonant frequency of 15-30 kHz, suitable for raster scanners such as retinal scan displays. Finally, we present a preliminary prototype produced by such a process.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74093410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399703
A. Barger, D. Goren, A. Kolodny
This paper presents an approach to physical design and modelling of network-on-chip interconnects using on-chip transmission lines. Design guidelines are presented allowing the use of simple models with frequency-independent RLCG parameters. Circuit simulation results demonstrate the validity of this approach in a real design environment.
{"title":"Design and modelling of network on chip interconnects using transmission lines","authors":"A. Barger, D. Goren, A. Kolodny","doi":"10.1109/ICECS.2004.1399703","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399703","url":null,"abstract":"This paper presents an approach to physical design and modelling of network-on-chip interconnects using on-chip transmission lines. Design guidelines are presented allowing the use of simple models with frequency-independent RLCG parameters. Circuit simulation results demonstrate the validity of this approach in a real design environment.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79278783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399665
C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry
This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.
{"title":"A 4 Gsps, 2-4 GHz input bandwidth, 3-bits flash A/D converter","authors":"C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry","doi":"10.1109/ICECS.2004.1399665","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399665","url":null,"abstract":"This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84403624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399711
H. Spitzer, Y. Zimmer
Medical ultrasonic B-scans often suffer from inherent artifacts that originate from the attenuation properties of the sonic beam in the living tissues. Common methods such as time gain compensation (TGC) do not yield satisfactory results. We tested a previous algorithm for compression of wide dynamic range in an attempt to address the above problem. This algorithm is based on a biological model that was also suggested for wide dynamic range and lightness constancy. It is based on retinal mechanisms of adaptation (gain control), both 'local', and 'remote', that enable also video image applications by taking into account the dynamics of human adaptation mechanisms. The results indicate that the algorithm succeeded in automatically exposing the details in very bright (i.e., saturated) and very dark zones in the same image. Such an exposure appears as a promising significant tool for better clinical diagnosis.
{"title":"Improvement of illumination artifacts in medical ultrasound images using a biologically based algorithm for compression of wide dynamic range","authors":"H. Spitzer, Y. Zimmer","doi":"10.1109/ICECS.2004.1399711","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399711","url":null,"abstract":"Medical ultrasonic B-scans often suffer from inherent artifacts that originate from the attenuation properties of the sonic beam in the living tissues. Common methods such as time gain compensation (TGC) do not yield satisfactory results. We tested a previous algorithm for compression of wide dynamic range in an attempt to address the above problem. This algorithm is based on a biological model that was also suggested for wide dynamic range and lightness constancy. It is based on retinal mechanisms of adaptation (gain control), both 'local', and 'remote', that enable also video image applications by taking into account the dynamics of human adaptation mechanisms. The results indicate that the algorithm succeeded in automatically exposing the details in very bright (i.e., saturated) and very dark zones in the same image. Such an exposure appears as a promising significant tool for better clinical diagnosis.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84594978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399622
I. Elhanany, O. Arazi, M. Kahane
This paper presents a performance analysis of output queued packet switch architectures employing virtual input queueing (VIQ), whereby arrival rates are nonuniformly distributed between the sources and the service intervals are bursty. In particular, we study the case of a two-state Markov-modulated service discipline, reflecting on several pragmatic scenarios such as noisy packet radio networks. We show that by exploiting an extended Markov-modulated service process and the Geo/GI/1 queueing model, closed-form expressions for the mean queueing latencies can be obtained. The methodology established in this paper can be extended to derive additional performance metrics and expected behavior of more complex packet switching architectures.
{"title":"Virtual input queued packet switches with non-uniform arrivals and bursty service","authors":"I. Elhanany, O. Arazi, M. Kahane","doi":"10.1109/ICECS.2004.1399622","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399622","url":null,"abstract":"This paper presents a performance analysis of output queued packet switch architectures employing virtual input queueing (VIQ), whereby arrival rates are nonuniformly distributed between the sources and the service intervals are bursty. In particular, we study the case of a two-state Markov-modulated service discipline, reflecting on several pragmatic scenarios such as noisy packet radio networks. We show that by exploiting an extended Markov-modulated service process and the Geo/GI/1 queueing model, closed-form expressions for the mean queueing latencies can be obtained. The methodology established in this paper can be extended to derive additional performance metrics and expected behavior of more complex packet switching architectures.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85226378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399660
A. Bruckstein
Summary form only given. The field of image processing and analysis is very broad, encompassing a wide variety of research issues, from efficient encoding of images and video sequences, through image enhancement and restoration to image segmentation, recovering spatial shape from shading and pattern distortions, learning about 3D from multiple unregistered 2D images, of image sequences, and high level image understanding topics. Consequently, researchers in this field rely on an amazingly wide variety of mathematical and computational techniques in their attempts to solve the many problems that arise. The grand challenges in image processing are therefore issues concerning syntheses and synergies between the variety of methods, however, the most important challenge remains the wise choice of problems worth focusing on.
{"title":"Grand challenges in image processing and analysis","authors":"A. Bruckstein","doi":"10.1109/ICECS.2004.1399660","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399660","url":null,"abstract":"Summary form only given. The field of image processing and analysis is very broad, encompassing a wide variety of research issues, from efficient encoding of images and video sequences, through image enhancement and restoration to image segmentation, recovering spatial shape from shading and pattern distortions, learning about 3D from multiple unregistered 2D images, of image sequences, and high level image understanding topics. Consequently, researchers in this field rely on an amazingly wide variety of mathematical and computational techniques in their attempts to solve the many problems that arise. The grand challenges in image processing are therefore issues concerning syntheses and synergies between the variety of methods, however, the most important challenge remains the wise choice of problems worth focusing on.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82418689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399624
Junhua Shen, K. Pun, O. Choy, C. Chan
A novel resistor time-sharing technique is proposed to achieve higher image rejection (IR) in the design of an intermediate frequency (IF) continuous time (CT) sigma delta (/spl Sigma//spl Delta/) modulator with integrated IF mixers. A third order CT /spl Sigma//spl Delta/ modulator with current feedforward compensation is designed, as well as current input comparator, digital tunable clock tree, etc. It is also found that, for the first stage of a modulator, the gain of input signal and feedback signal can be scaled down to relieve the harsh requirement of active components' input/output swing. This design is implemented in a 0.35 /spl mu/m double-poly four metal layer CMOS technology. Active area is 0.4 mm/sup 2/ and consumes 14.8 mW from a 3.3 V power supply. Postlayout simulation with 25 MHz IF shows no image signal is present for 4096 output data.
{"title":"An IF input continuous-time sigma-delta analog-digital converter with high image rejection","authors":"Junhua Shen, K. Pun, O. Choy, C. Chan","doi":"10.1109/ICECS.2004.1399624","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399624","url":null,"abstract":"A novel resistor time-sharing technique is proposed to achieve higher image rejection (IR) in the design of an intermediate frequency (IF) continuous time (CT) sigma delta (/spl Sigma//spl Delta/) modulator with integrated IF mixers. A third order CT /spl Sigma//spl Delta/ modulator with current feedforward compensation is designed, as well as current input comparator, digital tunable clock tree, etc. It is also found that, for the first stage of a modulator, the gain of input signal and feedback signal can be scaled down to relieve the harsh requirement of active components' input/output swing. This design is implemented in a 0.35 /spl mu/m double-poly four metal layer CMOS technology. Active area is 0.4 mm/sup 2/ and consumes 14.8 mW from a 3.3 V power supply. Postlayout simulation with 25 MHz IF shows no image signal is present for 4096 output data.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80472237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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